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Diffstat (limited to 'gcc/config/aarch64/aarch64-sve2.md')
-rw-r--r--gcc/config/aarch64/aarch64-sve2.md114
1 files changed, 99 insertions, 15 deletions
diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md
index 8c03e28..a3cbbce 100644
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -1346,12 +1346,12 @@
;; Predicated B16B16 binary operations.
(define_insn "@aarch64_pred_<optab><mode>"
- [(set (match_operand:VNx8BF_ONLY 0 "register_operand")
- (unspec:VNx8BF_ONLY
- [(match_operand:<VPRED> 1 "register_operand")
+ [(set (match_operand:SVE_BF 0 "register_operand")
+ (unspec:SVE_BF
+ [(match_operand:<VPRED> 1 "aarch64_predicate_operand")
(match_operand:SI 4 "aarch64_sve_gp_strictness")
- (match_operand:VNx8BF_ONLY 2 "register_operand")
- (match_operand:VNx8BF_ONLY 3 "register_operand")]
+ (match_operand:SVE_BF 2 "register_operand")
+ (match_operand:SVE_BF 3 "register_operand")]
SVE_COND_FP_BINARY_OPTAB))]
"TARGET_SSVE_B16B16 && <supports_bf16>"
{@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx , is_rev ]
@@ -2211,14 +2211,14 @@
;; - FDOT (2-way, indexed) (FP8DOT2)
;; -------------------------------------------------------------------------
(define_insn "@aarch64_sve_dot<mode>"
- [(set (match_operand:SVE_FULL_HSF 0 "register_operand")
- (unspec:SVE_FULL_HSF
- [(match_operand:SVE_FULL_HSF 1 "register_operand")
+ [(set (match_operand:SVE_FULL_HSF_FP8_FDOT 0 "register_operand")
+ (unspec:SVE_FULL_HSF_FP8_FDOT
+ [(match_operand:SVE_FULL_HSF_FP8_FDOT 1 "register_operand")
(match_operand:VNx16QI 2 "register_operand")
(match_operand:VNx16QI 3 "register_operand")
(reg:DI FPM_REGNUM)]
UNSPEC_DOT_FP8))]
- "TARGET_SSVE_FP8DOT4 && !(<MODE>mode == VNx8HFmode && !TARGET_SSVE_FP8DOT2)"
+ ""
{@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ]
[ w , 0 , w , w ; * ] fdot\t%0.<Vetype>, %2.b, %3.b
[ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;fdot\t%0.<Vetype>, %2.b, %3.b
@@ -2226,15 +2226,15 @@
)
(define_insn "@aarch64_sve_dot_lane<mode>"
- [(set (match_operand:SVE_FULL_HSF 0 "register_operand")
- (unspec:SVE_FULL_HSF
- [(match_operand:SVE_FULL_HSF 1 "register_operand")
+ [(set (match_operand:SVE_FULL_HSF_FP8_FDOT 0 "register_operand")
+ (unspec:SVE_FULL_HSF_FP8_FDOT
+ [(match_operand:SVE_FULL_HSF_FP8_FDOT 1 "register_operand")
(match_operand:VNx16QI 2 "register_operand")
(match_operand:VNx16QI 3 "register_operand")
(match_operand:SI 4 "const_int_operand")
(reg:DI FPM_REGNUM)]
UNSPEC_DOT_LANE_FP8))]
- "TARGET_SSVE_FP8DOT4 && !(<MODE>mode == VNx8HFmode && !TARGET_SSVE_FP8DOT2)"
+ ""
{@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ]
[ w , 0 , w , y ; * ] fdot\t%0.<Vetype>, %2.b, %3.b[%4]
[ ?&w , w , w , y ; yes ] movprfx\t%0, %1\;fdot\t%0.<Vetype>, %2.b, %3.b[%4]
@@ -4068,8 +4068,8 @@
[(match_operand:<VPRED> 1 "register_operand")
(match_operand:SI 2 "aarch64_sve_ptrue_flag")
(unspec:<VPRED>
- [(match_operand:SVE_FULL_BHI 3 "register_operand")
- (match_operand:SVE_FULL_BHI 4 "register_operand")]
+ [(match_operand:VNx16QI_ONLY 3 "register_operand")
+ (match_operand:VNx16QI_ONLY 4 "register_operand")]
SVE2_MATCH)]
UNSPEC_PRED_Z))
(clobber (reg:CC_NZC CC_REGNUM))]
@@ -4081,6 +4081,51 @@
}
)
+(define_expand "@aarch64_pred_<sve_int_op><mode>"
+ [(parallel
+ [(set (match_operand:VNx16BI 0 "register_operand")
+ (and:VNx16BI
+ (subreg:VNx16BI
+ (unspec:<VPRED>
+ [(match_operand:<VPRED> 1 "register_operand")
+ (match_operand:SI 2 "aarch64_sve_ptrue_flag")
+ (unspec:<VPRED>
+ [(match_operand:VNx8HI_ONLY 3 "register_operand")
+ (match_operand:VNx8HI_ONLY 4 "register_operand")]
+ SVE2_MATCH)]
+ UNSPEC_PRED_Z)
+ 0)
+ (match_dup 5)))
+ (clobber (reg:CC_NZC CC_REGNUM))])]
+ "TARGET_SVE2 && TARGET_NON_STREAMING"
+ {
+ operands[5] = aarch64_ptrue_all (GET_MODE_UNIT_SIZE (<MODE>mode));
+ }
+)
+
+(define_insn "*aarch64_pred_<sve_int_op><mode>"
+ [(set (match_operand:VNx16BI 0 "register_operand")
+ (and:VNx16BI
+ (subreg:VNx16BI
+ (unspec:<VPRED>
+ [(match_operand:<VPRED> 1 "register_operand")
+ (match_operand:SI 2 "aarch64_sve_ptrue_flag")
+ (unspec:<VPRED>
+ [(match_operand:VNx8HI_ONLY 3 "register_operand")
+ (match_operand:VNx8HI_ONLY 4 "register_operand")]
+ SVE2_MATCH)]
+ UNSPEC_PRED_Z)
+ 0)
+ (match_operand:<VPRED> 5 "aarch64_ptrue_all_operand")))
+ (clobber (reg:CC_NZC CC_REGNUM))]
+ "TARGET_SVE2 && TARGET_NON_STREAMING"
+ {@ [ cons: =0, 1 , 3, 4; attrs: pred_clobber ]
+ [ &Upa , Upl, w, w; yes ] <sve_int_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.<Vetype>
+ [ ?Upl , 0 , w, w; yes ] ^
+ [ Upa , Upl, w, w; no ] ^
+ }
+)
+
;; Predicated string matching in which both the flag and predicate results
;; are interesting.
(define_insn_and_rewrite "*aarch64_pred_<sve_int_op><mode>_cc"
@@ -4118,6 +4163,45 @@
}
)
+(define_insn_and_rewrite "*aarch64_pred_<sve_int_op><mode>_cc"
+ [(set (reg:CC_NZC CC_REGNUM)
+ (unspec:CC_NZC
+ [(match_operand:VNx16BI 1 "register_operand" "Upl")
+ (match_operand 4)
+ (match_operand:SI 5 "aarch64_sve_ptrue_flag")
+ (unspec:<VPRED>
+ [(match_operand 6)
+ (match_operand:SI 7 "aarch64_sve_ptrue_flag")
+ (unspec:<VPRED>
+ [(match_operand:VNx8HI_ONLY 2 "register_operand" "w")
+ (match_operand:VNx8HI_ONLY 3 "register_operand" "w")]
+ SVE2_MATCH)]
+ UNSPEC_PRED_Z)]
+ UNSPEC_PTEST))
+ (set (match_operand:VNx16BI 0 "register_operand" "=Upa")
+ (and:VNx16BI
+ (subreg:VNx16BI
+ (unspec:<VPRED>
+ [(match_dup 6)
+ (match_dup 7)
+ (unspec:<VPRED>
+ [(match_dup 2)
+ (match_dup 3)]
+ SVE2_MATCH)]
+ UNSPEC_PRED_Z)
+ 0)
+ (match_operand:<VPRED> 8 "aarch64_ptrue_all_operand")))]
+ "TARGET_SVE2
+ && TARGET_NON_STREAMING
+ && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])"
+ "<sve_int_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>"
+ "&& !rtx_equal_p (operands[4], operands[6])"
+ {
+ operands[6] = copy_rtx (operands[4]);
+ operands[7] = operands[5];
+ }
+)
+
;; Predicated string matching in which only the flags result is interesting.
(define_insn_and_rewrite "*aarch64_pred_<sve_int_op><mode>_ptest"
[(set (reg:CC_NZC CC_REGNUM)
generated by cgit v1.1 at 2025-08-09 00:21:32 +0000