diff options
96 files changed, 8208 insertions, 112 deletions
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 38c307c..36bd885 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -1020,7 +1020,7 @@ void aarch64_err_no_fpadvsimd (machine_mode); void aarch64_expand_epilogue (rtx_call_insn *); rtx aarch64_ptrue_all (unsigned int); opt_machine_mode aarch64_ptrue_all_mode (rtx); -rtx aarch64_convert_sve_data_to_pred (rtx, machine_mode, rtx); +rtx aarch64_convert_sve_data_to_pred (rtx, rtx); rtx aarch64_expand_sve_dupq (rtx, machine_mode, rtx); void aarch64_expand_mov_immediate (rtx, rtx); rtx aarch64_stack_protect_canary_mem (machine_mode, rtx, aarch64_salt_type); @@ -1039,6 +1039,7 @@ void aarch64_expand_sve_mem_move (rtx, rtx, machine_mode); bool aarch64_maybe_expand_sve_subreg_move (rtx, rtx); rtx aarch64_replace_reg_mode (rtx, machine_mode); void aarch64_split_sve_subreg_move (rtx, rtx, rtx); +void aarch64_emit_sve_pred_vec_duplicate (machine_mode, rtx, rtx); void aarch64_expand_prologue (void); void aarch64_decompose_vec_struct_index (machine_mode, rtx *, rtx *, bool); void aarch64_expand_vector_init (rtx, rtx); diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc index b439683..ecc0687 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc @@ -214,7 +214,8 @@ public: expand (function_expander &e) const override { e.add_ptrue_hint (0, e.gp_mode (0)); - insn_code icode = code_for_aarch64_pred_fac (m_unspec, e.vector_mode (0)); + insn_code icode = code_for_aarch64_pred_fac_acle (m_unspec, + e.vector_mode (0)); return e.use_exact_insn (icode); } @@ -497,10 +498,10 @@ public: { bool unsigned_p = e.type_suffix (0).unsigned_p; rtx_code code = get_rtx_code (m_code, unsigned_p); - return e.use_exact_insn (code_for_aarch64_pred_cmp (code, mode)); + return e.use_exact_insn (code_for_aarch64_pred_cmp_acle (code, mode)); } - insn_code icode = code_for_aarch64_pred_fcm (m_unspec_for_fp, mode); + insn_code icode = code_for_aarch64_pred_fcm_acle (m_unspec_for_fp, mode); return e.use_exact_insn (icode); } @@ -542,7 +543,7 @@ public: /* If the argument is a constant that the unwidened comparisons can handle directly, use them instead. */ - insn_code icode = code_for_aarch64_pred_cmp (code, mode); + insn_code icode = code_for_aarch64_pred_cmp_acle (code, mode); rtx op2 = unwrap_const_vec_duplicate (e.args[3]); if (CONSTANT_P (op2) && insn_data[icode].operand[4].predicate (op2, DImode)) @@ -581,7 +582,8 @@ public: expand (function_expander &e) const override { e.add_ptrue_hint (0, e.gp_mode (0)); - return e.use_exact_insn (code_for_aarch64_pred_fcmuo (e.vector_mode (0))); + auto mode = e.vector_mode (0); + return e.use_exact_insn (code_for_aarch64_pred_fcmuo_acle (mode)); } }; @@ -1048,6 +1050,23 @@ public: rtx expand (function_expander &e) const override { + machine_mode mode = e.vector_mode (0); + if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) + { + gcc_assert (e.pred == PRED_none); + + rtx src = e.args[0]; + if (GET_CODE (src) == CONST_INT) + return (src == const0_rtx + ? CONST0_RTX (VNx16BImode) + : aarch64_ptrue_all (e.type_suffix (0).element_bytes)); + + rtx dest = e.get_reg_target (); + src = force_reg (GET_MODE (src), src); + aarch64_emit_sve_pred_vec_duplicate (mode, dest, src); + return dest; + } + if (e.pred == PRED_none || e.pred == PRED_x) /* There's no benefit to using predicated instructions for _x here. */ return e.use_unpred_insn (e.direct_optab_handler (vec_duplicate_optab)); @@ -1056,7 +1075,6 @@ public: the duplicate of the function argument and the "false" value is the value of inactive lanes. */ insn_code icode; - machine_mode mode = e.vector_mode (0); if (valid_for_const_vector_p (GET_MODE_INNER (mode), e.args.last ())) /* Duplicate the constant to fill a vector. The pattern optimizes various cases involving constant operands, falling back to SEL @@ -1197,8 +1215,7 @@ public: if (mode != e.vector_mode (0)) { rtx data_dupq = aarch64_expand_sve_dupq (NULL, mode, vq_reg); - return aarch64_convert_sve_data_to_pred (e.possible_target, - e.vector_mode (0), data_dupq); + return aarch64_convert_sve_data_to_pred (e.possible_target, data_dupq); } return aarch64_expand_sve_dupq (e.possible_target, mode, vq_reg); @@ -1259,9 +1276,10 @@ public: index = target; } - e.args[0] = gen_lowpart (VNx2DImode, e.args[0]); + e.args[0] = aarch64_sve_reinterpret (VNx2DImode, e.args[0]); e.args[1] = index; - return e.use_exact_insn (CODE_FOR_aarch64_sve_tblvnx2di); + rtx res = e.use_exact_insn (CODE_FOR_aarch64_sve_tblvnx2di); + return aarch64_sve_reinterpret (mode, res); } }; @@ -2857,7 +2875,10 @@ public: rtx expand (function_expander &e) const override { - return e.use_exact_insn (code_for_aarch64_sve_rev (e.vector_mode (0))); + auto mode = e.vector_mode (0); + return e.use_exact_insn (e.type_suffix (0).bool_p + ? code_for_aarch64_sve_rev_acle (mode) + : code_for_aarch64_sve_rev (mode)); } }; @@ -3248,7 +3269,7 @@ public: unsigned int unpacks = m_high_p ? UNSPEC_UNPACKSHI : UNSPEC_UNPACKSLO; insn_code icode; if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) - icode = code_for_aarch64_sve_punpk (unpacku, mode); + icode = code_for_aarch64_sve_punpk_acle (unpacku); else { int unspec = e.type_suffix (0).unsigned_p ? unpacku : unpacks; diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h index 6f1c694..c05946d 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h +++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h @@ -630,7 +630,10 @@ public: rtx expand (function_expander &e) const override { - insn_code icode = code_for_aarch64_sve (m_unspec, e.vector_mode (0)); + auto mode = e.vector_mode (0); + insn_code icode = (e.type_suffix (0).bool_p + ? code_for_aarch64_sve_acle (m_unspec, mode) + : code_for_aarch64_sve (m_unspec, mode)); return e.use_exact_insn (icode); } @@ -838,7 +841,8 @@ public: machine_mode pred_mode = e.vector_mode (0); scalar_mode reg_mode = GET_MODE_INNER (e.vector_mode (1)); - return e.use_exact_insn (code_for_while (unspec, reg_mode, pred_mode)); + auto icode = code_for_aarch64_sve_while_acle (unspec, reg_mode, pred_mode); + return e.use_exact_insn (icode); } /* The unspec codes associated with signed and unsigned operations diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc index 73004a8..95c5ed8 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc @@ -881,7 +881,9 @@ public: { for (unsigned int i = 0; i < 2; ++i) e.args[i] = e.convert_to_pmode (e.args[i]); - return e.use_exact_insn (code_for_while (m_unspec, Pmode, e.gp_mode (0))); + auto icode = code_for_aarch64_sve_while_acle (m_unspec, Pmode, + e.gp_mode (0)); + return e.use_exact_insn (icode); } int m_unspec; diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc b/gcc/config/aarch64/aarch64-sve-builtins.cc index 01833a8..e394c9a 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins.cc @@ -4593,7 +4593,27 @@ function_expander::expand () gcc_assert (args.last ()->mode == DImode); emit_move_insn (gen_rtx_REG (DImode, FPM_REGNUM), args.last ()); } - return base->expand (*this); + rtx result = base->expand (*this); + if (function_returns_void_p ()) + gcc_assert (result == const0_rtx); + else + { + auto expected_mode = result_mode (); + if (GET_MODE_CLASS (expected_mode) == MODE_INT) + /* Scalar integer constants don't store a mode. + + It's OK for a variable result to have a different mode from the + function return type. In particular, some functions that return int + expand into instructions that have a DImode result, with all 64 bits + of the DImode being well-defined (usually zero). */ + gcc_assert (CONST_SCALAR_INT_P (result) + || GET_MODE_CLASS (GET_MODE (result)) == MODE_INT); + else + /* In other cases, the return value should have the same mode + as the return type. */ + gcc_assert (GET_MODE (result) == expected_mode); + } + return result; } /* Return a structure type that contains a single field of type FIELD_TYPE. diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 80a3288..88d323a 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -2990,10 +2990,7 @@ (vec_duplicate:PRED_ALL (match_operand:QI 1 "register_operand")))] "TARGET_SVE" { - rtx tmp = gen_reg_rtx (DImode); - rtx op1 = gen_lowpart (DImode, operands[1]); - emit_insn (gen_ashldi3 (tmp, op1, gen_int_mode (63, DImode))); - emit_insn (gen_while_ultdi<mode> (operands[0], const0_rtx, tmp)); + aarch64_emit_sve_pred_vec_duplicate (<MODE>mode, operands[0], operands[1]); DONE; } ) @@ -8361,6 +8358,71 @@ } ) +;; Likewise, but yield a VNx16BI result regardless of the element width. +;; The .b case is equivalent to the above. +(define_expand "@aarch64_pred_cmp<cmp_op><mode>_acle" + [(parallel + [(set (match_operand:<VPRED> 0 "register_operand") + (unspec:<VPRED> + [(match_operand:<VPRED> 1 "register_operand") + (match_operand:SI 2 "aarch64_sve_ptrue_flag") + (SVE_INT_CMP:<VPRED> + (match_operand:VNx16QI_ONLY 3 "register_operand") + (match_operand:VNx16QI_ONLY 4 "aarch64_sve_cmp_<sve_imm_con>_operand"))] + UNSPEC_PRED_Z)) + (clobber (reg:CC_NZC CC_REGNUM))])] + "TARGET_SVE" +) + +;; For wider elements, bitcast the predicate result to a VNx16BI and use +;; an (and ...) to indicate that only every second, fourth, or eighth bit +;; is set. +(define_expand "@aarch64_pred_cmp<cmp_op><mode>_acle" + [(parallel + [(set (match_operand:VNx16BI 0 "register_operand") + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_operand:<VPRED> 1 "register_operand") + (match_operand:SI 2 "aarch64_sve_ptrue_flag") + (SVE_INT_CMP:<VPRED> + (match_operand:SVE_FULL_HSDI 3 "register_operand") + (match_operand:SVE_FULL_HSDI 4 "aarch64_sve_cmp_<sve_imm_con>_operand"))] + UNSPEC_PRED_Z) + 0) + (match_dup 5))) + (clobber (reg:CC_NZC CC_REGNUM))])] + "TARGET_SVE" + { + operands[5] = aarch64_ptrue_all (GET_MODE_UNIT_SIZE (<MODE>mode)); + } +) + +(define_insn "*aarch64_pred_cmp<cmp_op><mode>_acle" + [(set (match_operand:VNx16BI 0 "register_operand") + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_operand:<VPRED> 1 "register_operand") + (match_operand:SI 2 "aarch64_sve_ptrue_flag") + (SVE_INT_CMP:<VPRED> + (match_operand:SVE_FULL_HSDI 3 "register_operand") + (match_operand:SVE_FULL_HSDI 4 "aarch64_sve_cmp_<sve_imm_con>_operand"))] + UNSPEC_PRED_Z) + 0) + (match_operand:<VPRED> 5 "aarch64_ptrue_all_operand"))) + (clobber (reg:CC_NZC CC_REGNUM))] + "TARGET_SVE" + {@ [ cons: =0 , 1 , 3 , 4 ; attrs: pred_clobber ] + [ &Upa , Upl, w , <sve_imm_con>; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, #%4 + [ ?Upl , 0 , w , <sve_imm_con>; yes ] ^ + [ Upa , Upl, w , <sve_imm_con>; no ] ^ + [ &Upa , Upl, w , w ; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.<Vetype> + [ ?Upl , 0 , w , w ; yes ] ^ + [ Upa , Upl, w , w ; no ] ^ + } +) + ;; Predicated integer comparisons in which both the flag and predicate ;; results are interesting. (define_insn_and_rewrite "*cmp<cmp_op><mode>_cc" @@ -8402,6 +8464,49 @@ } ) +(define_insn_and_rewrite "*cmp<cmp_op><mode>_acle_cc" + [(set (reg:CC_NZC CC_REGNUM) + (unspec:CC_NZC + [(match_operand:VNx16BI 1 "register_operand") + (match_operand 4) + (match_operand:SI 5 "aarch64_sve_ptrue_flag") + (unspec:<VPRED> + [(match_operand 6) + (match_operand:SI 7 "aarch64_sve_ptrue_flag") + (SVE_INT_CMP:<VPRED> + (match_operand:SVE_FULL_HSDI 2 "register_operand") + (match_operand:SVE_FULL_HSDI 3 "aarch64_sve_cmp_<sve_imm_con>_operand"))] + UNSPEC_PRED_Z)] + UNSPEC_PTEST)) + (set (match_operand:VNx16BI 0 "register_operand") + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_dup 6) + (match_dup 7) + (SVE_INT_CMP:<VPRED> + (match_dup 2) + (match_dup 3))] + UNSPEC_PRED_Z) + 0) + (match_operand:<VPRED> 8 "aarch64_ptrue_all_operand")))] + "TARGET_SVE + && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])" + {@ [ cons: =0 , 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upl, w , <sve_imm_con>; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, #%3 + [ ?Upl , 0 , w , <sve_imm_con>; yes ] ^ + [ Upa , Upl, w , <sve_imm_con>; no ] ^ + [ &Upa , Upl, w , w ; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype> + [ ?Upl , 0 , w , w ; yes ] ^ + [ Upa , Upl, w , w ; no ] ^ + } + "&& !rtx_equal_p (operands[4], operands[6])" + { + operands[6] = copy_rtx (operands[4]); + operands[7] = operands[5]; + } +) + ;; Predicated integer comparisons in which only the flags result is ;; interesting. (define_insn_and_rewrite "*cmp<cmp_op><mode>_ptest" @@ -8467,14 +8572,52 @@ (clobber (reg:CC_NZC CC_REGNUM))])] ) +(define_insn_and_split "*cmp<cmp_op><mode>_acle_and" + [(set (match_operand:VNx16BI 0 "register_operand" "=Upa, Upa") + (and:VNx16BI + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_operand 4) + (const_int SVE_KNOWN_PTRUE) + (SVE_INT_CMP:<VPRED> + (match_operand:SVE_FULL_HSDI 2 "register_operand" "w, w") + (match_operand:SVE_FULL_HSDI 3 "aarch64_sve_cmp_<sve_imm_con>_operand" "<sve_imm_con>, w"))] + UNSPEC_PRED_Z) + 0) + (match_operand:VNx16BI 1 "register_operand" "Upl, Upl")) + (match_operand:<VPRED> 5 "aarch64_ptrue_all_operand"))) + (clobber (reg:CC_NZC CC_REGNUM))] + "TARGET_SVE" + "#" + "&& 1" + [(parallel + [(set (match_dup 0) + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_dup 1) + (const_int SVE_MAYBE_NOT_PTRUE) + (SVE_INT_CMP:<VPRED> + (match_dup 2) + (match_dup 3))] + UNSPEC_PRED_Z) + 0) + (match_dup 5))) + (clobber (reg:CC_NZC CC_REGNUM))])] + { + operands[1] = gen_lowpart (<VPRED>mode, operands[1]); + } +) + ;; Predicated integer wide comparisons. (define_insn "@aarch64_pred_cmp<cmp_op><mode>_wide" [(set (match_operand:<VPRED> 0 "register_operand") (unspec:<VPRED> - [(match_operand:VNx16BI 1 "register_operand") + [(match_operand:<VPRED> 1 "register_operand") (match_operand:SI 2 "aarch64_sve_ptrue_flag") (unspec:<VPRED> - [(match_operand:SVE_FULL_BHSI 3 "register_operand") + [(match_operand:VNx16QI_ONLY 3 "register_operand") (match_operand:VNx2DI 4 "register_operand")] SVE_COND_INT_CMP_WIDE)] UNSPEC_PRED_Z)) @@ -8487,16 +8630,61 @@ } ) +(define_expand "@aarch64_pred_cmp<cmp_op><mode>_wide" + [(parallel + [(set (match_operand:VNx16BI 0 "register_operand") + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_operand:<VPRED> 1 "register_operand") + (match_operand:SI 2 "aarch64_sve_ptrue_flag") + (unspec:<VPRED> + [(match_operand:SVE_FULL_HSI 3 "register_operand") + (match_operand:VNx2DI 4 "register_operand")] + SVE_COND_INT_CMP_WIDE)] + UNSPEC_PRED_Z) + 0) + (match_dup 5))) + (clobber (reg:CC_NZC CC_REGNUM))])] + "TARGET_SVE" + { + operands[5] = aarch64_ptrue_all (GET_MODE_UNIT_SIZE (<MODE>mode)); + } +) + +(define_insn "*aarch64_pred_cmp<cmp_op><mode>_wide" + [(set (match_operand:VNx16BI 0 "register_operand") + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_operand:<VPRED> 1 "register_operand") + (match_operand:SI 2 "aarch64_sve_ptrue_flag") + (unspec:<VPRED> + [(match_operand:SVE_FULL_HSI 3 "register_operand") + (match_operand:VNx2DI 4 "register_operand")] + SVE_COND_INT_CMP_WIDE)] + UNSPEC_PRED_Z) + 0) + (match_operand:<VPRED> 5 "aarch64_ptrue_all_operand"))) + (clobber (reg:CC_NZC CC_REGNUM))] + "TARGET_SVE" + {@ [ cons: =0, 1 , 2, 3, 4; attrs: pred_clobber ] + [ &Upa , Upl, , w, w; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.d + [ ?Upl , 0 , , w, w; yes ] ^ + [ Upa , Upl, , w, w; no ] ^ + } +) + ;; Predicated integer wide comparisons in which both the flag and ;; predicate results are interesting. -(define_insn "*aarch64_pred_cmp<cmp_op><mode>_wide_cc" +(define_insn_and_rewrite "*aarch64_pred_cmp<cmp_op><mode>_wide_cc" [(set (reg:CC_NZC CC_REGNUM) (unspec:CC_NZC [(match_operand:VNx16BI 1 "register_operand") (match_operand 4) (match_operand:SI 5 "aarch64_sve_ptrue_flag") (unspec:<VPRED> - [(match_operand:VNx16BI 6 "register_operand") + [(match_operand:<VPRED> 6 "register_operand") (match_operand:SI 7 "aarch64_sve_ptrue_flag") (unspec:<VPRED> [(match_operand:SVE_FULL_BHSI 2 "register_operand") @@ -8520,18 +8708,65 @@ [ ?Upl , 0 , w, w, Upl; yes ] ^ [ Upa , Upl, w, w, Upl; no ] ^ } + "&& !rtx_equal_p (operands[4], operands[6])" + { + operands[6] = copy_rtx (operands[4]); + operands[7] = operands[5]; + } +) + +(define_insn_and_rewrite "*aarch64_pred_cmp<cmp_op><mode>_wide_cc" + [(set (reg:CC_NZC CC_REGNUM) + (unspec:CC_NZC + [(match_operand:VNx16BI 1 "register_operand") + (match_operand 4) + (match_operand:SI 5 "aarch64_sve_ptrue_flag") + (unspec:<VPRED> + [(match_operand:<VPRED> 6 "register_operand") + (match_operand:SI 7 "aarch64_sve_ptrue_flag") + (unspec:<VPRED> + [(match_operand:SVE_FULL_HSI 2 "register_operand") + (match_operand:VNx2DI 3 "register_operand")] + SVE_COND_INT_CMP_WIDE)] + UNSPEC_PRED_Z)] + UNSPEC_PTEST)) + (set (match_operand:VNx16BI 0 "register_operand") + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_dup 6) + (match_dup 7) + (unspec:<VPRED> + [(match_dup 2) + (match_dup 3)] + SVE_COND_INT_CMP_WIDE)] + UNSPEC_PRED_Z) + 0) + (match_operand:<VPRED> 8 "aarch64_ptrue_all_operand")))] + "TARGET_SVE + && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])" + {@ [ cons: =0, 1 , 2, 3, 6 ; attrs: pred_clobber ] + [ &Upa , Upl, w, w, Upl; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.d + [ ?Upl , 0 , w, w, Upl; yes ] ^ + [ Upa , Upl, w, w, Upl; no ] ^ + } + "&& !rtx_equal_p (operands[4], operands[6])" + { + operands[6] = copy_rtx (operands[4]); + operands[7] = operands[5]; + } ) ;; Predicated integer wide comparisons in which only the flags result ;; is interesting. -(define_insn "*aarch64_pred_cmp<cmp_op><mode>_wide_ptest" +(define_insn_and_rewrite "*aarch64_pred_cmp<cmp_op><mode>_wide_ptest" [(set (reg:CC_NZC CC_REGNUM) (unspec:CC_NZC [(match_operand:VNx16BI 1 "register_operand") (match_operand 4) (match_operand:SI 5 "aarch64_sve_ptrue_flag") (unspec:<VPRED> - [(match_operand:VNx16BI 6 "register_operand") + [(match_operand:<VPRED> 6 "register_operand") (match_operand:SI 7 "aarch64_sve_ptrue_flag") (unspec:<VPRED> [(match_operand:SVE_FULL_BHSI 2 "register_operand") @@ -8547,6 +8782,11 @@ [ ?Upl , 0 , w, w, Upl; yes ] ^ [ Upa , Upl, w, w, Upl; no ] ^ } + "&& !rtx_equal_p (operands[4], operands[6])" + { + operands[6] = copy_rtx (operands[4]); + operands[7] = operands[5]; + } ) ;; ------------------------------------------------------------------------- @@ -8584,6 +8824,58 @@ "while<cmp_op>\t%0.<PRED_ALL:Vetype>, %<w>1, %<w>2" ) +;; Likewise, but yield a VNx16BI result regardless of the element width. +;; The .b case is equivalent to the above. +(define_expand "@aarch64_sve_while_<while_optab_cmp><GPI:mode><VNx16BI_ONLY:mode>_acle" + [(parallel + [(set (match_operand:VNx16BI_ONLY 0 "register_operand") + (unspec:VNx16BI_ONLY + [(const_int SVE_WHILE_B) + (match_operand:GPI 1 "aarch64_reg_or_zero") + (match_operand:GPI 2 "aarch64_reg_or_zero")] + SVE_WHILE)) + (clobber (reg:CC_NZC CC_REGNUM))])] + "TARGET_SVE" +) + +;; For wider elements, bitcast the predicate result to a VNx16BI and use +;; an (and ...) to indicate that only every second, fourth, or eighth bit +;; is set. +(define_expand "@aarch64_sve_while_<while_optab_cmp><GPI:mode><PRED_HSD:mode>_acle" + [(parallel + [(set (match_operand:VNx16BI 0 "register_operand") + (and:VNx16BI + (subreg:VNx16BI + (unspec:PRED_HSD + [(const_int SVE_WHILE_B) + (match_operand:GPI 1 "aarch64_reg_or_zero") + (match_operand:GPI 2 "aarch64_reg_or_zero")] + SVE_WHILE) + 0) + (match_dup 3))) + (clobber (reg:CC_NZC CC_REGNUM))])] + "TARGET_SVE" + { + operands[3] = aarch64_ptrue_all (<data_bytes>); + } +) + +(define_insn "*aarch64_sve_while_<while_optab_cmp><GPI:mode><PRED_HSD:mode>_acle" + [(set (match_operand:VNx16BI 0 "register_operand" "=Upa") + (and:VNx16BI + (subreg:VNx16BI + (unspec:PRED_HSD + [(const_int SVE_WHILE_B) + (match_operand:GPI 1 "aarch64_reg_or_zero" "rZ") + (match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")] + SVE_WHILE) + 0) + (match_operand:PRED_HSD 3 "aarch64_ptrue_all_operand"))) + (clobber (reg:CC_NZC CC_REGNUM))] + "TARGET_SVE" + "while<cmp_op>\t%0.<PRED_HSD:Vetype>, %<w>1, %<w>2" +) + ;; The WHILE instructions set the flags in the same way as a PTEST with ;; a PTRUE GP. Handle the case in which both results are useful. The GP ;; operands to the PTEST aren't needed, so we allow them to be anything. @@ -8615,6 +8907,38 @@ } ) +(define_insn_and_rewrite "*while_<while_optab_cmp><GPI:mode><PRED_HSD:mode>_acle_cc" + [(set (reg:CC_NZC CC_REGNUM) + (unspec:CC_NZC + [(match_operand 3) + (match_operand 4) + (const_int SVE_KNOWN_PTRUE) + (unspec:PRED_HSD + [(const_int SVE_WHILE_B) + (match_operand:GPI 1 "aarch64_reg_or_zero" "rZ") + (match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")] + SVE_WHILE)] + UNSPEC_PTEST)) + (set (match_operand:VNx16BI 0 "register_operand" "=Upa") + (and:VNx16BI + (subreg:VNx16BI + (unspec:PRED_HSD [(const_int SVE_WHILE_B) + (match_dup 1) + (match_dup 2)] + SVE_WHILE) + 0) + (match_operand:PRED_HSD 5 "aarch64_ptrue_all_operand")))] + "TARGET_SVE" + "while<cmp_op>\t%0.<PRED_HSD:Vetype>, %<w>1, %<w>2" + ;; Force the compiler to drop the unused predicate operand, so that we + ;; don't have an unnecessary PTRUE. + "&& (!CONSTANT_P (operands[3]) || !CONSTANT_P (operands[4]))" + { + operands[3] = CONSTM1_RTX (VNx16BImode); + operands[4] = CONSTM1_RTX (<PRED_HSD:MODE>mode); + } +) + ;; Same, but handle the case in which only the flags result is useful. (define_insn_and_rewrite "@while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>_ptest" [(set (reg:CC_NZC CC_REGNUM) @@ -8685,6 +9009,43 @@ } ) +(define_expand "@aarch64_pred_fcm<cmp_op><mode>_acle" + [(set (match_operand:VNx16BI 0 "register_operand") + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_operand:<VPRED> 1 "aarch64_predicate_operand") + (match_operand:SI 2 "aarch64_sve_ptrue_flag") + (match_operand:SVE_F 3 "register_operand") + (match_operand:SVE_F 4 "aarch64_simd_reg_or_zero")] + SVE_COND_FP_CMP_I0) + 0) + (match_dup 5)))] + "TARGET_SVE" + { + operands[5] = aarch64_ptrue_all (GET_MODE_UNIT_SIZE (<MODE>mode)); + } +) + +(define_insn "*aarch64_pred_fcm<cmp_op><mode>_acle" + [(set (match_operand:VNx16BI 0 "register_operand") + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_operand:<VPRED> 1 "aarch64_predicate_operand") + (match_operand:SI 2 "aarch64_sve_ptrue_flag") + (match_operand:SVE_F 3 "register_operand") + (match_operand:SVE_F 4 "aarch64_simd_reg_or_zero")] + SVE_COND_FP_CMP_I0) + 0) + (match_operand:<VPRED> 5 "aarch64_ptrue_all_operand")))] + "TARGET_SVE" + {@ [ cons: =0 , 1 , 3 , 4 ] + [ Upa , Upl , w , Dz ] fcm<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, #0.0 + [ Upa , Upl , w , w ] fcm<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.<Vetype> + } +) + ;; Same for unordered comparisons. (define_insn "@aarch64_pred_fcmuo<mode>" [(set (match_operand:<VPRED> 0 "register_operand" "=Upa") @@ -8698,6 +9059,40 @@ "fcmuo\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.<Vetype>" ) +(define_expand "@aarch64_pred_fcmuo<mode>_acle" + [(set (match_operand:VNx16BI 0 "register_operand") + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_operand:<VPRED> 1 "aarch64_predicate_operand") + (match_operand:SI 2 "aarch64_sve_ptrue_flag") + (match_operand:SVE_F 3 "register_operand") + (match_operand:SVE_F 4 "register_operand")] + UNSPEC_COND_FCMUO) + 0) + (match_dup 5)))] + "TARGET_SVE" + { + operands[5] = aarch64_ptrue_all (GET_MODE_UNIT_SIZE (<MODE>mode)); + } +) + +(define_insn "*aarch64_pred_fcmuo<mode>_acle" + [(set (match_operand:VNx16BI 0 "register_operand" "=Upa") + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_operand:<VPRED> 1 "aarch64_predicate_operand" "Upl") + (match_operand:SI 2 "aarch64_sve_ptrue_flag") + (match_operand:SVE_F 3 "register_operand" "w") + (match_operand:SVE_F 4 "register_operand" "w")] + UNSPEC_COND_FCMUO) + 0) + (match_operand:<VPRED> 5 "aarch64_ptrue_all_operand")))] + "TARGET_SVE" + "fcmuo\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.<Vetype>" +) + ;; Floating-point comparisons predicated on a PTRUE, with the results ANDed ;; with another predicate P. This does not have the same trapping behavior ;; as predicating the comparison itself on P, but it's a legitimate fold, @@ -8916,23 +9311,30 @@ ;; ------------------------------------------------------------------------- ;; Predicated floating-point absolute comparisons. -(define_expand "@aarch64_pred_fac<cmp_op><mode>" - [(set (match_operand:<VPRED> 0 "register_operand") - (unspec:<VPRED> - [(match_operand:<VPRED> 1 "register_operand") - (match_operand:SI 2 "aarch64_sve_ptrue_flag") - (unspec:SVE_FULL_F - [(match_dup 1) - (match_dup 2) - (match_operand:SVE_FULL_F 3 "register_operand")] - UNSPEC_COND_FABS) - (unspec:SVE_FULL_F - [(match_dup 1) - (match_dup 2) - (match_operand:SVE_FULL_F 4 "register_operand")] - UNSPEC_COND_FABS)] - SVE_COND_FP_ABS_CMP))] +(define_expand "@aarch64_pred_fac<cmp_op><mode>_acle" + [(set (match_operand:VNx16BI 0 "register_operand") + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_operand:<VPRED> 1 "register_operand") + (match_operand:SI 2 "aarch64_sve_ptrue_flag") + (unspec:SVE_FULL_F + [(match_dup 1) + (match_dup 2) + (match_operand:SVE_FULL_F 3 "register_operand")] + UNSPEC_COND_FABS) + (unspec:SVE_FULL_F + [(match_dup 1) + (match_dup 2) + (match_operand:SVE_FULL_F 4 "register_operand")] + UNSPEC_COND_FABS)] + SVE_COND_FP_ABS_CMP) + 0) + (match_dup 5)))] "TARGET_SVE" + { + operands[5] = aarch64_ptrue_all (GET_MODE_UNIT_SIZE (<MODE>mode)); + } ) (define_insn_and_rewrite "*aarch64_pred_fac<cmp_op><mode>_relaxed" @@ -8981,6 +9383,30 @@ "fac<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>" ) +(define_insn "*aarch64_pred_fac<cmp_op><mode>_strict_acle" + [(set (match_operand:VNx16BI 0 "register_operand" "=Upa") + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_operand:<VPRED> 1 "register_operand" "Upl") + (match_operand:SI 4 "aarch64_sve_ptrue_flag") + (unspec:SVE_FULL_F + [(match_dup 1) + (match_operand:SI 5 "aarch64_sve_gp_strictness") + (match_operand:SVE_FULL_F 2 "register_operand" "w")] + UNSPEC_COND_FABS) + (unspec:SVE_FULL_F + [(match_dup 1) + (match_operand:SI 6 "aarch64_sve_gp_strictness") + (match_operand:SVE_FULL_F 3 "register_operand" "w")] + UNSPEC_COND_FABS)] + SVE_COND_FP_ABS_CMP) + 0) + (match_operand:<VPRED> 7 "aarch64_ptrue_all_operand")))] + "TARGET_SVE" + "fac<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>" +) + ;; ------------------------------------------------------------------------- ;; ---- [PRED] Select ;; ------------------------------------------------------------------------- @@ -9429,7 +9855,30 @@ (unspec:PRED_ALL [(match_operand:PRED_ALL 1 "register_operand" "Upa")] UNSPEC_REV))] "TARGET_SVE" - "rev\t%0.<Vetype>, %1.<Vetype>") + "rev\t%0.<Vetype>, %1.<Vetype>" +) + +(define_expand "@aarch64_sve_rev<mode>_acle" + [(set (match_operand:VNx16BI 0 "register_operand") + (unspec:VNx16BI + [(match_operand:VNx16BI 1 "register_operand") + (match_dup:PRED_ALL 2)] + UNSPEC_REV_PRED))] + "TARGET_SVE" + { + operands[2] = CONST0_RTX (<MODE>mode); + } +) + +(define_insn "*aarch64_sve_rev<mode>_acle" + [(set (match_operand:VNx16BI 0 "register_operand" "=Upa") + (unspec:VNx16BI + [(match_operand:VNx16BI 1 "register_operand" "Upa") + (match_operand:PRED_ALL 2 "aarch64_simd_imm_zero")] + UNSPEC_REV_PRED))] + "TARGET_SVE" + "rev\t%0.<Vetype>, %1.<Vetype>" +) ;; ------------------------------------------------------------------------- ;; ---- [PRED] Special-purpose binary permutes @@ -9454,18 +9903,39 @@ "<perm_insn>\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype>" ) -;; Special purpose permute used by the predicate generation instructions. -;; Unlike the normal permute patterns, these instructions operate on VNx16BI -;; regardless of the element size, so that all input and output bits are -;; well-defined. Operand 3 then indicates the size of the permute. -(define_insn "@aarch64_sve_trn1_conv<mode>" +;; Special-purpose permutes used by the ACLE intrinsics and predicate +;; generation instructions. Unlike the normal permute patterns, these +;; instructions operate on VNx16BI regardless of the element size, so that +;; all input and output bits are well-defined. Operand 3 then indicates +;; the size of the permute. +;; +;; To make generation easier, this pattern embeds the permute type as the +;; fourth operand to the unspec. On the one hand, this avoids overloading +;; unspecs like UNSPEC_ZIP1 to represent two different operations. On the +;; other hand, it avoids having a separate unspec for each variant, and +;; having to map from one kind of unspec to the other. +(define_expand "@aarch64_sve_<perm_insn><mode>_acle" + [(set (match_operand:VNx16BI 0 "register_operand") + (unspec:VNx16BI [(match_operand:VNx16BI 1 "register_operand") + (match_operand:VNx16BI 2 "register_operand") + (match_dup:PRED_ALL 3) + (const_int PERMUTE)] + UNSPEC_PERMUTE_PRED))] + "TARGET_SVE" + { + operands[3] = CONST0_RTX (<MODE>mode); + } +) + +(define_insn "*aarch64_sve_<perm_insn><mode>_acle" [(set (match_operand:VNx16BI 0 "register_operand" "=Upa") (unspec:VNx16BI [(match_operand:VNx16BI 1 "register_operand" "Upa") (match_operand:VNx16BI 2 "register_operand" "Upa") - (match_operand:PRED_ALL 3 "aarch64_simd_imm_zero")] - UNSPEC_TRN1_CONV))] + (match_operand:PRED_ALL 3 "aarch64_simd_imm_zero") + (const_int PERMUTE)] + UNSPEC_PERMUTE_PRED))] "TARGET_SVE" - "trn1\t%0.<PRED_ALL:Vetype>, %1.<PRED_ALL:Vetype>, %2.<PRED_ALL:Vetype>" + "<perm_insn>\t%0.<PRED_ALL:Vetype>, %1.<PRED_ALL:Vetype>, %2.<PRED_ALL:Vetype>" ) ;; ========================================================================= @@ -10454,6 +10924,34 @@ "punpk<perm_hilo>\t%0.h, %1.b" ) +(define_expand "@aarch64_sve_punpk<perm_hilo>_acle" + [(set (match_operand:VNx16BI 0 "register_operand") + (and:VNx16BI + (subreg:VNx16BI + (unspec:VNx8BI + [(match_operand:VNx16BI 1 "register_operand")] + UNPACK_UNSIGNED) + 0) + (match_dup 2)))] + "TARGET_SVE" + { + operands[2] = aarch64_ptrue_all (2); + } +) + +(define_insn "*aarch64_sve_punpk<perm_hilo>_acle" + [(set (match_operand:VNx16BI 0 "register_operand" "=Upa") + (and:VNx16BI + (subreg:VNx16BI + (unspec:VNx8BI + [(match_operand:VNx16BI 1 "register_operand" "Upa")] + UNPACK_UNSIGNED) + 0) + (match_operand:VNx8BI 2 "aarch64_ptrue_all_operand")))] + "TARGET_SVE" + "punpk<perm_hilo>\t%0.h, %1.b" +) + ;; ========================================================================= ;; == Vector partitioning ;; ========================================================================= @@ -10678,14 +11176,49 @@ ;; ------------------------------------------------------------------------- (define_insn "@aarch64_sve_<sve_pred_op><mode>" - [(set (match_operand:PRED_ALL 0 "register_operand" "=Upa") - (unspec:PRED_ALL - [(match_operand:PRED_ALL 1 "register_operand" "Upa") + [(set (match_operand:VNx16BI_ONLY 0 "register_operand" "=Upa") + (unspec:VNx16BI_ONLY + [(match_operand:VNx16BI_ONLY 1 "register_operand" "Upa") (match_operand:SI 2 "aarch64_sve_ptrue_flag") - (match_operand:PRED_ALL 3 "register_operand" "0")] + (match_operand:VNx16BI_ONLY 3 "register_operand" "0")] SVE_PITER)) (clobber (reg:CC_NZC CC_REGNUM))] - "TARGET_SVE && <max_elem_bits> >= <elem_bits>" + "TARGET_SVE" + "<sve_pred_op>\t%0.<Vetype>, %1, %0.<Vetype>" +) + +(define_expand "@aarch64_sve_<sve_pred_op><mode>" + [(parallel + [(set (match_operand:VNx16BI 0 "register_operand") + (and:VNx16BI + (subreg:VNx16BI + (unspec:PRED_HSD + [(match_operand:PRED_HSD 1 "register_operand") + (match_operand:SI 2 "aarch64_sve_ptrue_flag") + (match_operand:PRED_HSD 3 "register_operand")] + PNEXT_ONLY) + 0) + (match_dup 4))) + (clobber (reg:CC_NZC CC_REGNUM))])] + "TARGET_SVE" + { + operands[4] = aarch64_ptrue_all (<data_bytes>); + } +) + +(define_insn "*aarch64_sve_<sve_pred_op><mode>" + [(set (match_operand:VNx16BI 0 "register_operand" "=Upa") + (and:VNx16BI + (subreg:VNx16BI + (unspec:PRED_HSD + [(match_operand:PRED_HSD 1 "register_operand" "Upa") + (match_operand:SI 2 "aarch64_sve_ptrue_flag") + (match_operand:PRED_HSD 3 "register_operand" "0")] + PNEXT_ONLY) + 0) + (match_operand:PRED_HSD 4 "aarch64_ptrue_all_operand"))) + (clobber (reg:CC_NZC CC_REGNUM))] + "TARGET_SVE" "<sve_pred_op>\t%0.<Vetype>, %1, %0.<Vetype>" ) @@ -10719,6 +11252,38 @@ } ) +(define_insn_and_rewrite "*aarch64_sve_<sve_pred_op><mode>_cc" + [(set (reg:CC_NZC CC_REGNUM) + (unspec:CC_NZC + [(match_operand:VNx16BI 1 "register_operand" "Upa") + (match_operand 2) + (match_operand:SI 3 "aarch64_sve_ptrue_flag") + (unspec:PRED_HSD + [(match_operand 4) + (match_operand:SI 5 "aarch64_sve_ptrue_flag") + (match_operand:PRED_HSD 6 "register_operand" "0")] + PNEXT_ONLY)] + UNSPEC_PTEST)) + (set (match_operand:VNx16BI 0 "register_operand" "=Upa") + (and:VNx16BI + (subreg:VNx16BI + (unspec:PRED_HSD + [(match_dup 4) + (match_dup 5) + (match_dup 6)] + PNEXT_ONLY) + 0) + (match_operand:PRED_HSD 7 "aarch64_ptrue_all_operand")))] + "TARGET_SVE + && aarch64_sve_same_pred_for_ptest_p (&operands[2], &operands[4])" + "<sve_pred_op>\t%0.<Vetype>, %1, %0.<Vetype>" + "&& !rtx_equal_p (operands[2], operands[4])" + { + operands[4] = operands[2]; + operands[5] = operands[3]; + } +) + ;; Same, but with only the flags result being interesting. (define_insn_and_rewrite "*aarch64_sve_<sve_pred_op><mode>_ptest" [(set (reg:CC_NZC CC_REGNUM) diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index 31bdd85..a4c3257 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -4068,8 +4068,8 @@ [(match_operand:<VPRED> 1 "register_operand") (match_operand:SI 2 "aarch64_sve_ptrue_flag") (unspec:<VPRED> - [(match_operand:SVE_FULL_BHI 3 "register_operand") - (match_operand:SVE_FULL_BHI 4 "register_operand")] + [(match_operand:VNx16QI_ONLY 3 "register_operand") + (match_operand:VNx16QI_ONLY 4 "register_operand")] SVE2_MATCH)] UNSPEC_PRED_Z)) (clobber (reg:CC_NZC CC_REGNUM))] @@ -4081,6 +4081,51 @@ } ) +(define_expand "@aarch64_pred_<sve_int_op><mode>" + [(parallel + [(set (match_operand:VNx16BI 0 "register_operand") + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_operand:<VPRED> 1 "register_operand") + (match_operand:SI 2 "aarch64_sve_ptrue_flag") + (unspec:<VPRED> + [(match_operand:VNx8HI_ONLY 3 "register_operand") + (match_operand:VNx8HI_ONLY 4 "register_operand")] + SVE2_MATCH)] + UNSPEC_PRED_Z) + 0) + (match_dup 5))) + (clobber (reg:CC_NZC CC_REGNUM))])] + "TARGET_SVE2 && TARGET_NON_STREAMING" + { + operands[5] = aarch64_ptrue_all (GET_MODE_UNIT_SIZE (<MODE>mode)); + } +) + +(define_insn "*aarch64_pred_<sve_int_op><mode>" + [(set (match_operand:VNx16BI 0 "register_operand") + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_operand:<VPRED> 1 "register_operand") + (match_operand:SI 2 "aarch64_sve_ptrue_flag") + (unspec:<VPRED> + [(match_operand:VNx8HI_ONLY 3 "register_operand") + (match_operand:VNx8HI_ONLY 4 "register_operand")] + SVE2_MATCH)] + UNSPEC_PRED_Z) + 0) + (match_operand:<VPRED> 5 "aarch64_ptrue_all_operand"))) + (clobber (reg:CC_NZC CC_REGNUM))] + "TARGET_SVE2 && TARGET_NON_STREAMING" + {@ [ cons: =0, 1 , 3, 4; attrs: pred_clobber ] + [ &Upa , Upl, w, w; yes ] <sve_int_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.<Vetype> + [ ?Upl , 0 , w, w; yes ] ^ + [ Upa , Upl, w, w; no ] ^ + } +) + ;; Predicated string matching in which both the flag and predicate results ;; are interesting. (define_insn_and_rewrite "*aarch64_pred_<sve_int_op><mode>_cc" @@ -4118,6 +4163,45 @@ } ) +(define_insn_and_rewrite "*aarch64_pred_<sve_int_op><mode>_cc" + [(set (reg:CC_NZC CC_REGNUM) + (unspec:CC_NZC + [(match_operand:VNx16BI 1 "register_operand" "Upl") + (match_operand 4) + (match_operand:SI 5 "aarch64_sve_ptrue_flag") + (unspec:<VPRED> + [(match_operand 6) + (match_operand:SI 7 "aarch64_sve_ptrue_flag") + (unspec:<VPRED> + [(match_operand:VNx8HI_ONLY 2 "register_operand" "w") + (match_operand:VNx8HI_ONLY 3 "register_operand" "w")] + SVE2_MATCH)] + UNSPEC_PRED_Z)] + UNSPEC_PTEST)) + (set (match_operand:VNx16BI 0 "register_operand" "=Upa") + (and:VNx16BI + (subreg:VNx16BI + (unspec:<VPRED> + [(match_dup 6) + (match_dup 7) + (unspec:<VPRED> + [(match_dup 2) + (match_dup 3)] + SVE2_MATCH)] + UNSPEC_PRED_Z) + 0) + (match_operand:<VPRED> 8 "aarch64_ptrue_all_operand")))] + "TARGET_SVE2 + && TARGET_NON_STREAMING + && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])" + "<sve_int_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>" + "&& !rtx_equal_p (operands[4], operands[6])" + { + operands[6] = copy_rtx (operands[4]); + operands[7] = operands[5]; + } +) + ;; Predicated string matching in which only the flags result is interesting. (define_insn_and_rewrite "*aarch64_pred_<sve_int_op><mode>_ptest" [(set (reg:CC_NZC CC_REGNUM) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index f4a2062..d30c9c7 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -3962,16 +3962,24 @@ aarch64_sve_emit_masked_fp_pred (machine_mode data_mode, rtx pred) /* Emit a comparison CMP between OP0 and OP1, both of which have mode DATA_MODE, and return the result in a predicate of mode PRED_MODE. - Use TARGET as the target register if nonnull and convenient. */ + Use TARGET as the target register if nonnull and convenient. + + PRED_MODE can be either VNx16BI or the natural predicate mode for + DATA_MODE. */ static rtx aarch64_sve_emit_int_cmp (rtx target, machine_mode pred_mode, rtx_code cmp, machine_mode data_mode, rtx op1, rtx op2) { - insn_code icode = code_for_aarch64_pred_cmp (cmp, data_mode); + auto src_pred_mode = aarch64_sve_pred_mode (data_mode); + insn_code icode; + if (known_eq (GET_MODE_NUNITS (pred_mode), GET_MODE_NUNITS (data_mode))) + icode = code_for_aarch64_pred_cmp (cmp, data_mode); + else + icode = code_for_aarch64_pred_cmp_acle (cmp, data_mode); expand_operand ops[5]; create_output_operand (&ops[0], target, pred_mode); - create_input_operand (&ops[1], CONSTM1_RTX (pred_mode), pred_mode); + create_input_operand (&ops[1], CONSTM1_RTX (src_pred_mode), src_pred_mode); create_integer_operand (&ops[2], SVE_KNOWN_PTRUE); create_input_operand (&ops[3], op1, data_mode); create_input_operand (&ops[4], op2, data_mode); @@ -3979,15 +3987,14 @@ aarch64_sve_emit_int_cmp (rtx target, machine_mode pred_mode, rtx_code cmp, return ops[0].value; } -/* Use a comparison to convert integer vector SRC into MODE, which is - the corresponding SVE predicate mode. Use TARGET for the result - if it's nonnull and convenient. */ +/* Use a comparison to convert integer vector SRC into VNx16BI. + Use TARGET for the result if it's nonnull and convenient. */ rtx -aarch64_convert_sve_data_to_pred (rtx target, machine_mode mode, rtx src) +aarch64_convert_sve_data_to_pred (rtx target, rtx src) { machine_mode src_mode = GET_MODE (src); - return aarch64_sve_emit_int_cmp (target, mode, NE, src_mode, + return aarch64_sve_emit_int_cmp (target, VNx16BImode, NE, src_mode, src, CONST0_RTX (src_mode)); } @@ -6069,9 +6076,9 @@ aarch64_sve_move_pred_via_while (rtx target, machine_mode mode, unsigned int vl) { rtx limit = force_reg (DImode, gen_int_mode (vl, DImode)); - target = aarch64_target_reg (target, mode); - emit_insn (gen_while (UNSPEC_WHILELO, DImode, mode, - target, const0_rtx, limit)); + target = aarch64_target_reg (target, VNx16BImode); + emit_insn (gen_aarch64_sve_while_acle (UNSPEC_WHILELO, DImode, mode, + target, const0_rtx, limit)); return target; } @@ -6217,8 +6224,7 @@ aarch64_expand_sve_const_pred_trn (rtx target, rtx_vector_builder &builder, operands but permutes them as though they had mode MODE. */ machine_mode mode = aarch64_sve_pred_mode (permute_size).require (); target = aarch64_target_reg (target, GET_MODE (a)); - rtx type_reg = CONST0_RTX (mode); - emit_insn (gen_aarch64_sve_trn1_conv (mode, target, a, b, type_reg)); + emit_insn (gen_aarch64_sve_acle (UNSPEC_TRN1, mode, target, a, b)); return target; } @@ -6300,8 +6306,7 @@ aarch64_expand_sve_const_pred (rtx target, rtx_vector_builder &builder) for (unsigned int i = 0; i < builder.encoded_nelts (); ++i) int_builder.quick_push (INTVAL (builder.elt (i)) ? constm1_rtx : const0_rtx); - return aarch64_convert_sve_data_to_pred (target, VNx16BImode, - int_builder.build ()); + return aarch64_convert_sve_data_to_pred (target, int_builder.build ()); } /* Set DEST to immediate IMM. */ @@ -6753,6 +6758,27 @@ aarch64_split_sve_subreg_move (rtx dest, rtx ptrue, rtx src) dest, ptrue, src)); } +/* Set predicate register DEST such that every element has the scalar + boolean value in SRC, with any nonzero source counting as "true". + MODE is a MODE_VECTOR_BOOL that determines the element size; + DEST can have this mode or VNx16BImode. In the latter case, + the upper bits of each element are defined to be zero, as for + the .H, .S, and .D forms of PTRUE. */ + +void +aarch64_emit_sve_pred_vec_duplicate (machine_mode mode, rtx dest, rtx src) +{ + rtx tmp = gen_reg_rtx (DImode); + emit_insn (gen_ashldi3 (tmp, gen_lowpart (DImode, src), + gen_int_mode (63, DImode))); + if (GET_MODE (dest) == VNx16BImode) + emit_insn (gen_aarch64_sve_while_acle (UNSPEC_WHILELO, DImode, mode, + dest, const0_rtx, tmp)); + else + emit_insn (gen_while (UNSPEC_WHILELO, DImode, mode, + dest, const0_rtx, tmp)); +} + static bool aarch64_function_ok_for_sibcall (tree, tree exp) { diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index a4ae685..dc2be81 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -280,6 +280,7 @@ UNSPEC_PACIBSP UNSPEC_PRLG_STK UNSPEC_REV + UNSPEC_REV_PRED UNSPEC_SADALP UNSPEC_SCVTF UNSPEC_SET_LANE diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 8533912..8f8237e 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -455,6 +455,7 @@ (define_mode_iterator VCVTFPM [V4HF V8HF V4SF]) ;; Iterators for single modes, for "@" patterns. +(define_mode_iterator VNx16BI_ONLY [VNx16BI]) (define_mode_iterator VNx16QI_ONLY [VNx16QI]) (define_mode_iterator VNx16SI_ONLY [VNx16SI]) (define_mode_iterator VNx8HI_ONLY [VNx8HI]) @@ -930,7 +931,6 @@ UNSPEC_UZP2Q ; Used in aarch64-sve.md. UNSPEC_ZIP1Q ; Used in aarch64-sve.md. UNSPEC_ZIP2Q ; Used in aarch64-sve.md. - UNSPEC_TRN1_CONV ; Used in aarch64-sve.md. UNSPEC_COND_CMPEQ_WIDE ; Used in aarch64-sve.md. UNSPEC_COND_CMPGE_WIDE ; Used in aarch64-sve.md. UNSPEC_COND_CMPGT_WIDE ; Used in aarch64-sve.md. @@ -1185,6 +1185,9 @@ UNSPEC_LUTI2 ; Used in aarch64-simd.md. UNSPEC_LUTI4 ; Used in aarch64-simd.md. + ;; All used in aarch64-sve.md + UNSPEC_PERMUTE_PRED + ;; All used in aarch64-sve2.md UNSPEC_ADDQV UNSPEC_ANDQV @@ -3877,6 +3880,8 @@ (define_int_iterator SVE_PITER [UNSPEC_PFIRST UNSPEC_PNEXT]) +(define_int_iterator PNEXT_ONLY [UNSPEC_PNEXT]) + (define_int_iterator MATMUL [UNSPEC_SMATMUL UNSPEC_UMATMUL UNSPEC_USMATMUL]) diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 32056da..4d5d57f 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -1078,3 +1078,9 @@ (define_predicate "aarch64_maskload_else_operand" (and (match_code "const_vector") (match_test "op == CONST0_RTX (GET_MODE (op))"))) + +;; Check for a VNx16BI predicate that is a canonical PTRUE for the given +;; predicate mode. +(define_special_predicate "aarch64_ptrue_all_operand" + (and (match_code "const_vector") + (match_test "aarch64_ptrue_all_mode (op) == mode"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index c1e708b..105a60d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -20612,18 +20612,22 @@ LTO output files. @opindex fdump-rtl-@var{pass} @item -d@var{letters} @itemx -fdump-rtl-@var{pass} -@itemx -fdump-rtl-@var{pass}=@var{filename} +@itemx -fdump-rtl-@var{pass}-@var{options} +@itemx -fdump-rtl-@var{pass}-@var{options}=@var{filename} Says to make debugging dumps during compilation at times specified by -@var{letters}. This is used for debugging the RTL-based passes of the +@var{letters} when using @option{-d} or by @var{pass} when using +@option{-fdump-rtl}. This is used for debugging the RTL-based passes of the compiler. Some @option{-d@var{letters}} switches have different meaning when @option{-E} is used for preprocessing. @xref{Preprocessor Options}, for information about preprocessor-specific dump options. -Debug dumps can be enabled with a @option{-fdump-rtl} switch or some -@option{-d} option @var{letters}. Here are the possible -letters for use in @var{pass} and @var{letters}, and their meanings: +The @samp{-@var{options}} form allows greater control over the details of the +dump. See @option{-fdump-tree}. + +Here are actual instances of command-line options following these patterns and +their meanings: @table @gcctabopt @@ -21150,8 +21154,7 @@ GraphViz to @file{@var{file}.@var{passid}.@var{pass}.dot}. Each function in the file is pretty-printed as a subgraph, so that GraphViz can render them all in a single plot. -This option currently only works for RTL dumps, and the RTL is always -dumped in slim form. +RTL is always dumped in slim form. @item vops Enable showing virtual operands for every statement. @item lineno diff --git a/gcc/testsuite/g++.dg/DRs/dr2578.C b/gcc/testsuite/g++.dg/DRs/dr2578.C new file mode 100644 index 0000000..0dce23b --- /dev/null +++ b/gcc/testsuite/g++.dg/DRs/dr2578.C @@ -0,0 +1,10 @@ +// DR 2578 - Undefined behavior when creating an invalid string literal via stringizing +// { dg-do preprocess } +// { dg-options "-pedantic-errors" } + +#define A(a) #a +#define B(a) A(a) +#define C \\ + +const char *x = B(C); // { dg-warning "invalid string literal, ignoring final '\\\\'" "" { target c++23_down } } +// { dg-error "invalid string literal, ignoring final '\\\\'" "" { target c++26 } .-1 } diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-105.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-105.c new file mode 100644 index 0000000..61b93c0 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-105.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fno-tree-sra -fdump-tree-fre1-details" } */ + +struct s1 +{ + int t, t1; +}; + +struct s3 +{ + struct s1 t; +}; + +struct s2 +{ + struct s3 t; +}; + +void f(int, int); +void l(); +void g(int a, int b, int *p) +{ + struct s2 c; + { + struct s1 tmp = {a,b}; + struct s3 *t = &c.t; + t->t = tmp; + } + f(c.t.t.t, c.t.t.t1); +} + +/* { dg-final { scan-tree-dump "Replaced c.t.t.t1 with b" "fre1" } } */ +/* { dg-final { scan-tree-dump "Replaced c.t.t.t with a" "fre1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-106.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-106.c new file mode 100644 index 0000000..6da4201 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-106.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fno-tree-sra -fdump-tree-fre1-details" } */ + +struct s1 +{ + int t, t1; +}; + +struct s3 +{ + struct s1 t; +}; + +struct s2 +{ + struct s3 t; +}; + +void f(int, int); +void l(); +void g(int a, int b, int *p) +{ + struct s2 c; + { + struct s1 tmp = {a,b}; + c.t.t = tmp; + } + struct s1 *t = &c.t.t; + f(t->t, t->t1); +} + +/* { dg-final { scan-tree-dump "Replaced \[^\r\n\]*.t1 with b" "fre1" } } */ +/* { dg-final { scan-tree-dump "Replaced \[^\r\n\]*.t with a" "fre1" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acge_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acge_1.c new file mode 100644 index 0000000..37428a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acge_1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** facge p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svacge (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** facge p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svacge (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** facge p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svacge (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** facge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svacge (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** facge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svacge (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** facge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svacge (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** facge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svacge (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acgt_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acgt_1.c new file mode 100644 index 0000000..5829369 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acgt_1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** facgt p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svacgt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** facgt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svacgt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** facgt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svacgt (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** facgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svacgt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** facgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svacgt (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** facgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svacgt (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** facgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svacgt (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acle_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acle_1.c new file mode 100644 index 0000000..bd5200e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/acle_1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** facle p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svacle (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** facle p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svacle (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** facle p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svacle (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** facle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svacle (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** facle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svacle (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** facle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svacle (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** facle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svacle (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/aclt_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/aclt_1.c new file mode 100644 index 0000000..876aba9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/aclt_1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** faclt p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svaclt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** faclt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svaclt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** faclt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svaclt (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** faclt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svaclt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** faclt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svaclt (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** faclt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svaclt (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** faclt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svaclt (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_1.c index dd8f6c4..d6aabc8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_1.c @@ -18,5 +18,57 @@ test2 (svbool_t pg, svint8_t x, svint64_t y, int *any) return svptest_any (pg, res); } -/* { dg-final { scan-assembler-times {\tcmpeq\t} 2 } } */ +void +test3 (svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpeq_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svint8_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpeq_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpeq_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpeq_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint32_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpeq_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint32_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpeq_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpeq\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ /* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_2.c index 028d375..df98d27 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_2.c @@ -33,6 +33,108 @@ test4 (svbool_t pg, svint8_t x, int *any) return svptest_any (pg, res); } -/* { dg-final { scan-assembler-times {\tcmpeq\t} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\t[^\n]*, #10} 2 } } */ +void +test5 (svint16_t x, svint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpeq (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpeq (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpeq (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpeq (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svint32_t x, svint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpeq (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpeq (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpeq (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpeq (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svint64_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpeq (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpeq (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpeq (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpeq (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpeq\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\t[^\n]*, #10} 8 } } */ /* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_4.c new file mode 100644 index 0000000..8e4b931 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_4.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpeq p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpeq (pg, x, y), p0); +} + +/* +** test2: +** cmpeq p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpeq (pg, x, y), p0); +} + +/* +** test3: +** cmpeq p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpeq (pg, x, y), pg); +} + +/* +** test4: +** cmpeq p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test4 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpeq (pg, x, 10), p0); +} + +/* +** test5: +** cmpeq p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test5 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpeq (pg, x, 10), p0); +} + +/* +** test6: +** cmpeq p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test6 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpeq (pg, x, 10), pg); +} + +/* +** test7: +** cmpeq p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpeq (pg, x, y), p0); +} + +/* +** test8: +** cmpeq p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpeq (pg, x, 10), p0); +} + +/* +** test9: +** cmpeq p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpeq (pg, x, y), p0); +} + +/* +** test10: +** cmpeq p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpeq (pg, x, 10), p0); +} + +/* +** test11: +** cmpeq p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpeq (pg, x, y), p0); +} + +/* +** test12: +** cmpeq p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpeq (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_5.c new file mode 100644 index 0000000..2958bc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_5.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpeq p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svint16_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmpeq p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmpeq p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_6.c new file mode 100644 index 0000000..9233de9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_6.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** fcmeq p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** fcmeq p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** fcmeq p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** fcmeq p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** fcmeq p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpeq (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** fcmeq p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpeq (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** fcmeq p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpeq (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_1.c new file mode 100644 index 0000000..f6bb3c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_1.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint8_t y, int *any) +{ + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svint8_t x, int *any) +{ + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svint32_t x, svint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svint64_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpge\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_2.c new file mode 100644 index 0000000..fc92291 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_2.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint8_t y, int *any) +{ + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svuint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svuint8_t x, int *any) +{ + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svuint32_t x, svuint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svuint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svuint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svuint64_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svuint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svuint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpge (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmphs\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmphs\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_3.c new file mode 100644 index 0000000..6d50df5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_3.c @@ -0,0 +1,169 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpge p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test2: +** cmpge p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, y), p0); +} + +/* +** test3: +** cmpge p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, y), pg); +} + +/* +** test4: +** ( +** cmpge p0\.b, p0/z, z0\.b, #10 +** | +** cmpgt p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test4 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +/* +** test5: +** ( +** cmpge p0\.b, p0/z, z0\.b, #10 +** | +** cmpgt p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test5 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, 10), p0); +} + +/* +** test6: +** ( +** cmpge p0\.b, p0/z, z0\.b, #10 +** | +** cmpgt p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test6 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, 10), pg); +} + +/* +** test7: +** cmpge p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test8: +** cmpge p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +/* +** test9: +** cmpge p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test10: +** cmpge p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +/* +** test11: +** cmpge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test12: +** cmpge p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_4.c new file mode 100644 index 0000000..2430e80 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_4.c @@ -0,0 +1,169 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmphs p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test2: +** cmphs p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, y), p0); +} + +/* +** test3: +** cmphs p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, y), pg); +} + +/* +** test4: +** ( +** cmphs p0\.b, p0/z, z0\.b, #10 +** | +** cmphi p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test4 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +/* +** test5: +** ( +** cmphs p0\.b, p0/z, z0\.b, #10 +** | +** cmphi p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test5 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, 10), p0); +} + +/* +** test6: +** ( +** cmphs p0\.b, p0/z, z0\.b, #10 +** | +** cmphi p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test6 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpge (pg, x, 10), pg); +} + +/* +** test7: +** cmphs p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test8: +** cmphs p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +/* +** test9: +** cmphs p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test10: +** cmphs p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svuint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +/* +** test11: +** cmphs p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpge (pg, x, y), p0); +} + +/* +** test12: +** cmphs p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svuint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpge (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_5.c new file mode 100644 index 0000000..f4fa758 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_5.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint64_t y, int *any) +{ + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svint8_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint32_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint32_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpge\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_6.c new file mode 100644 index 0000000..979db4c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_6.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint64_t y, int *any) +{ + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svuint8_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint32_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint32_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpge_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmphs\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_7.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_7.c new file mode 100644 index 0000000..d6abab0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_7.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpge p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svint16_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmpge p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmpge p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_8.c new file mode 100644 index 0000000..70be917 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_8.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmphs p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svuint16_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmphs p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmphs p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_9.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_9.c new file mode 100644 index 0000000..0d4140e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_9.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** fcmge p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** fcmge p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** fcmge p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** fcmge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** fcmge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpge (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** fcmge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpge (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** fcmge p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpge (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_1.c new file mode 100644 index 0000000..6c28d6f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_1.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint8_t y, int *any) +{ + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svint8_t x, int *any) +{ + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svint32_t x, svint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svint64_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpgt\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_2.c new file mode 100644 index 0000000..2160484 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_2.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint8_t y, int *any) +{ + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svuint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svuint8_t x, int *any) +{ + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svuint32_t x, svuint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svuint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svuint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svuint64_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svuint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svuint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpgt (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmphi\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_3.c new file mode 100644 index 0000000..cc48b7e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpgt p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test2: +** cmpgt p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, y), p0); +} + +/* +** test3: +** cmpgt p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, y), pg); +} + +/* +** test4: +** cmpgt p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test4 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +/* +** test5: +** cmpgt p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test5 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, 10), p0); +} + +/* +** test6: +** cmpgt p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test6 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, 10), pg); +} + +/* +** test7: +** cmpgt p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test8: +** cmpgt p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +/* +** test9: +** cmpgt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test10: +** cmpgt p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +/* +** test11: +** cmpgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test12: +** cmpgt p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_4.c new file mode 100644 index 0000000..bd49fe8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_4.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmphi p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test2: +** cmphi p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, y), p0); +} + +/* +** test3: +** cmphi p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, y), pg); +} + +/* +** test4: +** cmphi p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test4 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +/* +** test5: +** cmphi p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test5 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, 10), p0); +} + +/* +** test6: +** cmphi p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test6 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpgt (pg, x, 10), pg); +} + +/* +** test7: +** cmphi p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test8: +** cmphi p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +/* +** test9: +** cmphi p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test10: +** cmphi p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svuint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +/* +** test11: +** cmphi p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpgt (pg, x, y), p0); +} + +/* +** test12: +** cmphi p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svuint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpgt (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_5.c new file mode 100644 index 0000000..f9f4c7d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_5.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint64_t y, int *any) +{ + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svint8_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint32_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint32_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpgt\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_6.c new file mode 100644 index 0000000..6df15b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_6.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint64_t y, int *any) +{ + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svuint8_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint32_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint32_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpgt_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmphi\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_7.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_7.c new file mode 100644 index 0000000..0656b29 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_7.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpgt p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svint16_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmpgt p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmpgt p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_8.c new file mode 100644 index 0000000..b0a9ac8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_8.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmphi p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svuint16_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmphi p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmphi p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_9.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_9.c new file mode 100644 index 0000000..dcd84f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_9.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** fcmgt p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** fcmgt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** fcmgt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** fcmgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** fcmgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpgt (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** fcmgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpgt (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** fcmgt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpgt (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_1.c new file mode 100644 index 0000000..f2d7d2b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_1.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint8_t y, int *any) +{ + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svint8_t x, int *any) +{ + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svint32_t x, svint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svint64_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmple\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmple\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_2.c new file mode 100644 index 0000000..9d13d7a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_2.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint8_t y, int *any) +{ + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svuint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svuint8_t x, int *any) +{ + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svuint32_t x, svuint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svuint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svuint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svuint64_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svuint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svuint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmple (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpls\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_3.c new file mode 100644 index 0000000..7a9326c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_3.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmple p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test2: +** cmple p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, y), p0); +} + +/* +** test3: +** cmple p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, y), pg); +} + +/* +** test4: +** cmple p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test4 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +/* +** test5: +** cmple p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test5 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, 10), p0); +} + +/* +** test6: +** cmple p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test6 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, 10), pg); +} + +/* +** test7: +** cmple p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test8: +** cmple p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +/* +** test9: +** cmple p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test10: +** cmple p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +/* +** test11: +** cmple p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test12: +** cmple p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_4.c new file mode 100644 index 0000000..aca4385 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_4.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpls p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test2: +** cmpls p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, y), p0); +} + +/* +** test3: +** cmpls p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, y), pg); +} + +/* +** test4: +** cmpls p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test4 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +/* +** test5: +** cmpls p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test5 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, 10), p0); +} + +/* +** test6: +** cmpls p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test6 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmple (pg, x, 10), pg); +} + +/* +** test7: +** cmpls p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test8: +** cmpls p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +/* +** test9: +** cmpls p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test10: +** cmpls p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svuint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +/* +** test11: +** cmpls p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmple (pg, x, y), p0); +} + +/* +** test12: +** cmpls p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svuint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmple (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_5.c new file mode 100644 index 0000000..1caf496 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_5.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint64_t y, int *any) +{ + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svint8_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint32_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint32_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmple\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_6.c new file mode 100644 index 0000000..ae85e89 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_6.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint64_t y, int *any) +{ + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svuint8_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint32_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint32_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmple_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpls\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_7.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_7.c new file mode 100644 index 0000000..3f3ea53 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_7.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmple p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svint16_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmple p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmple p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_8.c new file mode 100644 index 0000000..01281ca --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_8.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpls p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svuint16_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmpls p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmpls p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_9.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_9.c new file mode 100644 index 0000000..8d008b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_9.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** fcmle p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svcmple (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** fcmle p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmple (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** fcmle p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmple (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** fcmle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** fcmle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmple (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** fcmle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmple (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** fcmle p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmple (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_1.c new file mode 100644 index 0000000..a15bb4a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_1.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint8_t y, int *any) +{ + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svint8_t x, int *any) +{ + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svint32_t x, svint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svint64_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmplt\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_2.c new file mode 100644 index 0000000..43c53a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_2.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint8_t y, int *any) +{ + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svuint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svuint8_t x, int *any) +{ + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svuint32_t x, svuint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svuint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svuint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svuint64_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svuint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svuint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmplt (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmplo\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmplo\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_3.c new file mode 100644 index 0000000..bddbbeb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_3.c @@ -0,0 +1,169 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmplt p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test2: +** cmplt p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, y), p0); +} + +/* +** test3: +** cmplt p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, y), pg); +} + +/* +** test4: +** ( +** cmplt p0\.b, p0/z, z0\.b, #10 +** | +** cmple p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test4 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +/* +** test5: +** ( +** cmplt p0\.b, p0/z, z0\.b, #10 +** | +** cmple p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test5 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, 10), p0); +} + +/* +** test6: +** ( +** cmplt p0\.b, p0/z, z0\.b, #10 +** | +** cmple p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test6 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, 10), pg); +} + +/* +** test7: +** cmplt p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test8: +** cmplt p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +/* +** test9: +** cmplt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test10: +** cmplt p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +/* +** test11: +** cmplt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test12: +** cmplt p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_4.c new file mode 100644 index 0000000..b71c8e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_4.c @@ -0,0 +1,169 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmplo p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test2: +** cmplo p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, y), p0); +} + +/* +** test3: +** cmplo p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svuint8_t x, svuint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, y), pg); +} + +/* +** test4: +** ( +** cmplo p0\.b, p0/z, z0\.b, #10 +** | +** cmpls p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test4 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +/* +** test5: +** ( +** cmplo p0\.b, p0/z, z0\.b, #10 +** | +** cmpls p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test5 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, 10), p0); +} + +/* +** test6: +** ( +** cmplo p0\.b, p0/z, z0\.b, #10 +** | +** cmpls p0\.b, p0/z, z0\.b, #9 +** ) +** ret +*/ +svbool_t +test6 (svbool_t p0, svuint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmplt (pg, x, 10), pg); +} + +/* +** test7: +** cmplo p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svuint16_t x, svuint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test8: +** cmplo p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svuint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +/* +** test9: +** cmplo p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svuint32_t x, svuint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test10: +** cmplo p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svuint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +/* +** test11: +** cmplo p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svuint64_t x, svuint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmplt (pg, x, y), p0); +} + +/* +** test12: +** cmplo p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svuint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmplt (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_5.c new file mode 100644 index 0000000..6885e4d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_5.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint64_t y, int *any) +{ + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svint8_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint32_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint32_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmplt\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_6.c new file mode 100644 index 0000000..e9be9e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_6.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svuint8_t x, svuint64_t y, int *any) +{ + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svuint8_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svuint8_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svuint16_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svuint16_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svuint32_t x, svuint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svuint32_t x, svuint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmplt_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmplo\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_7.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_7.c new file mode 100644 index 0000000..a4de6ab --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_7.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmplt p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svint16_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmplt p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmplt p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_8.c new file mode 100644 index 0000000..0a095eb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_8.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmplo p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svuint16_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmplo p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmplo p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svuint32_t x, svuint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_9.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_9.c new file mode 100644 index 0000000..4f4b7b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_9.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** fcmlt p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** fcmlt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** fcmlt p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** fcmlt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** fcmlt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmplt (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** fcmlt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmplt (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** fcmlt p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmplt (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_1.c new file mode 100644 index 0000000..61f7718 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_1.c @@ -0,0 +1,140 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint8_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpne (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint8_t y, int *any) +{ + svbool_t res = svcmpne (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svbool_t pg, svint8_t x, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpne (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svbool_t pg, svint8_t x, int *any) +{ + svbool_t res = svcmpne (pg, x, 10); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint16_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpne (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpne (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint16_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpne (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpne (pg, x, 10); + return svptest_any (pg, res); +} + +void +test9 (svint32_t x, svint32_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpne (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test10 (svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpne (pg, x, y); + return svptest_any (pg, res); +} + +void +test11 (svint32_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpne (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test12 (svint32_t x) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpne (pg, x, 10); + return svptest_any (pg, res); +} + +void +test13 (svint64_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpne (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test14 (svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpne (pg, x, y); + return svptest_any (pg, res); +} + +void +test15 (svint64_t x, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpne (pg, x, 10); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test16 (svint64_t x) +{ + svbool_t pg = svptrue_b64 (); + svbool_t res = svcmpne (pg, x, 10); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpne\t} 16 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\t[^\n]*, #10} 8 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_2.c new file mode 100644 index 0000000..53cedb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_2.c @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpne p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test1 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpne (pg, x, y), p0); +} + +/* +** test2: +** cmpne p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test2 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpne (pg, x, y), p0); +} + +/* +** test3: +** cmpne p0\.b, p0/z, z0\.b, z1\.b +** ret +*/ +svbool_t +test3 (svbool_t p0, svint8_t x, svint8_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpne (pg, x, y), pg); +} + +/* +** test4: +** cmpne p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test4 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpne (pg, x, 10), p0); +} + +/* +** test5: +** cmpne p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test5 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpne (pg, x, 10), p0); +} + +/* +** test6: +** cmpne p0\.b, p0/z, z0\.b, #10 +** ret +*/ +svbool_t +test6 (svbool_t p0, svint8_t x) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (p0, svcmpne (pg, x, 10), pg); +} + +/* +** test7: +** cmpne p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test7 (svbool_t p0, svint16_t x, svint16_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpne (pg, x, y), p0); +} + +/* +** test8: +** cmpne p0\.h, p0/z, z0\.h, #10 +** ret +*/ +svbool_t +test8 (svbool_t p0, svint16_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpne (pg, x, 10), p0); +} + +/* +** test9: +** cmpne p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test9 (svbool_t p0, svint32_t x, svint32_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpne (pg, x, y), p0); +} + +/* +** test10: +** cmpne p0\.s, p0/z, z0\.s, #10 +** ret +*/ +svbool_t +test10 (svbool_t p0, svint32_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpne (pg, x, 10), p0); +} + +/* +** test11: +** cmpne p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test11 (svbool_t p0, svint64_t x, svint64_t y) +{ + svbool_t pg = svptrue_b8 (); + return svand_z (pg, svcmpne (pg, x, y), p0); +} + +/* +** test12: +** cmpne p0\.d, p0/z, z0\.d, #10 +** ret +*/ +svbool_t +test12 (svbool_t p0, svint64_t x) +{ + svbool_t pg = svptrue_b16 (); + return svand_z (pg, svcmpne (pg, x, 10), p0); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_3.c new file mode 100644 index 0000000..c5c3936 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_3.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +void +test1 (svbool_t pg, svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t res = svcmpne_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test2 (svbool_t pg, svint8_t x, svint64_t y, int *any) +{ + svbool_t res = svcmpne_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test3 (svint8_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpne_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test4 (svint8_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b8 (); + svbool_t res = svcmpne_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test5 (svint16_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpne_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test6 (svint16_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b16 (); + svbool_t res = svcmpne_wide (pg, x, y); + return svptest_any (pg, res); +} + +void +test7 (svint32_t x, svint64_t y, int *any, svbool_t *ptr) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpne_wide (pg, x, y); + *any = svptest_any (pg, res); + *ptr = res; +} + +int +test8 (svint32_t x, svint64_t y, int *any) +{ + svbool_t pg = svptrue_b32 (); + svbool_t res = svcmpne_wide (pg, x, y); + return svptest_any (pg, res); +} + +/* { dg-final { scan-assembler-times {\tcmpne\t} 8 } } */ +/* { dg-final { scan-assembler-times {\tptrue\t} 6 } } */ +/* { dg-final { scan-assembler-not {\tptest\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_4.c new file mode 100644 index 0000000..595e024 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_4.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** cmpne p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +svbool_t +test1 (svbool_t pg, svint16_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** cmpne p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test2 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne_wide (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** cmpne p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +svbool_t +test3 (svbool_t pg, svint32_t x, svint64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne_wide (pg, x, y), + svptrue_b32 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_5.c new file mode 100644 index 0000000..94fecd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_5.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** fcmne p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** fcmne p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** fcmne p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** fcmne p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** fcmne p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpne (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** fcmne p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpne (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** fcmne p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpne (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpuo_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpuo_1.c new file mode 100644 index 0000000..4b124b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpuo_1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** fcmuo p0\.h, p0/z, z0\.h, z1\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svfloat16_t x, svfloat16_t y) +{ + return svand_z (svptrue_b8 (), + svcmpuo (pg, x, y), + svptrue_b16 ()); +} + +/* +** test2: +** fcmuo p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test2 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpuo (pg, x, y), + svptrue_b16 ()); +} + +/* +** test3: +** fcmuo p0\.s, p0/z, z0\.s, z1\.s +** ret +*/ +svbool_t +test3 (svbool_t pg, svfloat32_t x, svfloat32_t y) +{ + return svand_z (svptrue_b8 (), + svcmpuo (pg, x, y), + svptrue_b32 ()); +} + +/* +** test4: +** fcmuo p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test4 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpuo (pg, x, y), + svptrue_b16 ()); +} + +/* +** test5: +** fcmuo p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test5 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpuo (pg, x, y), + svptrue_b8 ()); +} + +/* +** test6: +** fcmuo p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test6 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b8 (), + svcmpuo (pg, x, y), + svptrue_b64 ()); +} + +/* +** test7: +** fcmuo p0\.d, p0/z, z0\.d, z1\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svfloat64_t x, svfloat64_t y) +{ + return svand_z (svptrue_b32 (), + svcmpuo (pg, x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dup_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dup_1.c new file mode 100644 index 0000000..c3c4e2d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dup_1.c @@ -0,0 +1,47 @@ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +svbool_t +test1 (int x) +{ + return svand_z (svptrue_b16 (), svdup_b16 (x), svptrue_b16 ()); +} + +svbool_t +test2 (int x) +{ + return svand_z (svptrue_b8 (), svdup_b32 (x), svptrue_b16 ()); +} + +svbool_t +test3 (int x) +{ + return svand_z (svptrue_b32 (), svdup_b32 (x), svptrue_b16 ()); +} + +svbool_t +test4 (int x) +{ + return svand_z (svptrue_b32 (), svdup_b32 (x), svptrue_b32 ()); +} + +svbool_t +test5 (int x) +{ + return svand_z (svptrue_b8 (), svdup_b64 (x), svptrue_b32 ()); +} + +svbool_t +test6 (int x) +{ + return svand_z (svptrue_b16 (), svdup_b64 (x), svptrue_b8 ()); +} + +svbool_t +test7 (int x) +{ + return svand_z (svptrue_b16 (), svdup_b64 (x), svptrue_b64 ()); +} + +/* { dg-final { scan-assembler-not {\tand\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_13.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_13.c new file mode 100644 index 0000000..6d702b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_13.c @@ -0,0 +1,45 @@ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +svbool_t +test1 (int x0, int x1) +{ + return svand_z (svptrue_b8 (), svdupq_b64 (x0, x1), svptrue_b16 ()); +} + +svbool_t +test2 (int x0, int x1, int x2, int x3) +{ + return svand_z (svptrue_b8 (), svdupq_b32 (x0, x1, x2, x3), svptrue_b16 ()); +} + +svbool_t +test3 (int x0, int x1, int x2, int x3) +{ + return svand_z (svptrue_b32 (), svdupq_b32 (x0, x1, x2, x3), svptrue_b16 ()); +} + +svbool_t +test4 (int x0, int x1, int x2, int x3) +{ + return svand_z (svptrue_b32 (), svdupq_b32 (x0, x1, x2, x3), svptrue_b32 ()); +} + +svbool_t +test5 (int x0, int x1, int x2, int x3) +{ + return svand_z (svptrue_b8 (), + svdupq_b16 (x0, x1, x2, x3, x2, x0, x1, x3), + svptrue_b32 ()); +} + +svbool_t +test6 (int x0, int x1, int x2, int x3) +{ + return svand_z (svptrue_b64 (), + svdupq_b16 (x0, x1, x2, x3, x2, x0, x1, x3), + svptrue_b16 ()); +} + +/* { dg-final { scan-assembler-not {\tand\tp} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_lane_9.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_lane_9.c new file mode 100644 index 0000000..e3f352b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_lane_9.c @@ -0,0 +1,8 @@ +/* { dg-options "-O2 -mbig-endian" } */ + +#pragma GCC aarch64 "arm_sve.h" + +svint32_t f(svint32_t x) { return svdupq_lane (x, 17); } +void g(svint32_t *a, svint32_t *b) { *a = svdupq_lane (*b, 17); } + +/* { dg-final { scan-assembler-not {\trevw\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_2.c new file mode 100644 index 0000000..9b3daaa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_2.c @@ -0,0 +1,96 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** ... +** ptrue (p[0-3])\.h, all +** ... +** trn1 p0\.h, p[0-3]\.h, \1\.h +** ret +*/ +svbool_t +test1 () +{ + return svtrn1_b16 (svptrue_b8 (), svptrue_b16 ()); +} + +/* +** test2: +** ... +** ptrue (p[0-3])\.h, all +** ... +** trn1 p0\.h, \1\.h, p[0-3]\.h +** ret +*/ +svbool_t +test2 () +{ + return svtrn1_b16 (svptrue_b16 (), svptrue_b8 ()); +} + +/* +** test3: +** ... +** ptrue (p[0-3])\.s, all +** ... +** trn1 p0\.s, p[0-3]\.s, \1\.s +** ret +*/ +svbool_t +test3 () +{ + return svtrn1_b32 (svptrue_b8 (), svptrue_b32 ()); +} + +/* +** test4: +** ... +** ptrue (p[0-3])\.s, all +** ... +** trn1 p0\.s, \1\.s, p[0-3]\.s +** ret +*/ +svbool_t +test4 () +{ + return svtrn1_b32 (svptrue_b32 (), svptrue_b8 ()); +} + +/* +** test5: +** ... +** ptrue (p[0-3])\.d, all +** ... +** trn1 p0\.d, p[0-3]\.d, \1\.d +** ret +*/ +svbool_t +test5 () +{ + return svtrn1_b64 (svptrue_b8 (), svptrue_b64 ()); +} + +/* +** test6: +** ... +** ptrue (p[0-3])\.d, all +** ... +** trn1 p0\.d, \1\.d, p[0-3]\.d +** ret +*/ +svbool_t +test6 () +{ + return svtrn1_b64 (svptrue_b64 (), svptrue_b8 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_3.c new file mode 100644 index 0000000..678c541 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_3.c @@ -0,0 +1,96 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** ... +** ptrue (p[0-3])\.h, all +** ... +** trn2 p0\.h, p[0-3]\.h, \1\.h +** ret +*/ +svbool_t +test1 () +{ + return svtrn2_b16 (svptrue_b8 (), svptrue_b16 ()); +} + +/* +** test2: +** ... +** ptrue (p[0-3])\.h, all +** ... +** trn2 p0\.h, \1\.h, p[0-3]\.h +** ret +*/ +svbool_t +test2 () +{ + return svtrn2_b16 (svptrue_b16 (), svptrue_b8 ()); +} + +/* +** test3: +** ... +** ptrue (p[0-3])\.s, all +** ... +** trn2 p0\.s, p[0-3]\.s, \1\.s +** ret +*/ +svbool_t +test3 () +{ + return svtrn2_b32 (svptrue_b8 (), svptrue_b32 ()); +} + +/* +** test4: +** ... +** ptrue (p[0-3])\.s, all +** ... +** trn2 p0\.s, \1\.s, p[0-3]\.s +** ret +*/ +svbool_t +test4 () +{ + return svtrn2_b32 (svptrue_b32 (), svptrue_b8 ()); +} + +/* +** test5: +** ... +** ptrue (p[0-3])\.d, all +** ... +** trn2 p0\.d, p[0-3]\.d, \1\.d +** ret +*/ +svbool_t +test5 () +{ + return svtrn2_b64 (svptrue_b8 (), svptrue_b64 ()); +} + +/* +** test6: +** ... +** ptrue (p[0-3])\.d, all +** ... +** trn2 p0\.d, \1\.d, p[0-3]\.d +** ret +*/ +svbool_t +test6 () +{ + return svtrn2_b64 (svptrue_b64 (), svptrue_b8 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_4.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_4.c new file mode 100644 index 0000000..28c6018 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_4.c @@ -0,0 +1,96 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** ... +** ptrue (p[0-3])\.h, all +** ... +** zip1 p0\.h, p[0-3]\.h, \1\.h +** ret +*/ +svbool_t +test1 () +{ + return svzip1_b16 (svptrue_b8 (), svptrue_b16 ()); +} + +/* +** test2: +** ... +** ptrue (p[0-3])\.h, all +** ... +** zip1 p0\.h, \1\.h, p[0-3]\.h +** ret +*/ +svbool_t +test2 () +{ + return svzip1_b16 (svptrue_b16 (), svptrue_b8 ()); +} + +/* +** test3: +** ... +** ptrue (p[0-3])\.s, all +** ... +** zip1 p0\.s, p[0-3]\.s, \1\.s +** ret +*/ +svbool_t +test3 () +{ + return svzip1_b32 (svptrue_b8 (), svptrue_b32 ()); +} + +/* +** test4: +** ... +** ptrue (p[0-3])\.s, all +** ... +** zip1 p0\.s, \1\.s, p[0-3]\.s +** ret +*/ +svbool_t +test4 () +{ + return svzip1_b32 (svptrue_b32 (), svptrue_b8 ()); +} + +/* +** test5: +** ... +** ptrue (p[0-3])\.d, all +** ... +** zip1 p0\.d, p[0-3]\.d, \1\.d +** ret +*/ +svbool_t +test5 () +{ + return svzip1_b64 (svptrue_b8 (), svptrue_b64 ()); +} + +/* +** test6: +** ... +** ptrue (p[0-3])\.d, all +** ... +** zip1 p0\.d, \1\.d, p[0-3]\.d +** ret +*/ +svbool_t +test6 () +{ + return svzip1_b64 (svptrue_b64 (), svptrue_b8 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_5.c new file mode 100644 index 0000000..a8aec2b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_5.c @@ -0,0 +1,96 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** ... +** ptrue (p[0-3])\.h, all +** ... +** zip2 p0\.h, p[0-3]\.h, \1\.h +** ret +*/ +svbool_t +test1 () +{ + return svzip2_b16 (svptrue_b8 (), svptrue_b16 ()); +} + +/* +** test2: +** ... +** ptrue (p[0-3])\.h, all +** ... +** zip2 p0\.h, \1\.h, p[0-3]\.h +** ret +*/ +svbool_t +test2 () +{ + return svzip2_b16 (svptrue_b16 (), svptrue_b8 ()); +} + +/* +** test3: +** ... +** ptrue (p[0-3])\.s, all +** ... +** zip2 p0\.s, p[0-3]\.s, \1\.s +** ret +*/ +svbool_t +test3 () +{ + return svzip2_b32 (svptrue_b8 (), svptrue_b32 ()); +} + +/* +** test4: +** ... +** ptrue (p[0-3])\.s, all +** ... +** zip2 p0\.s, \1\.s, p[0-3]\.s +** ret +*/ +svbool_t +test4 () +{ + return svzip2_b32 (svptrue_b32 (), svptrue_b8 ()); +} + +/* +** test5: +** ... +** ptrue (p[0-3])\.d, all +** ... +** zip2 p0\.d, p[0-3]\.d, \1\.d +** ret +*/ +svbool_t +test5 () +{ + return svzip2_b64 (svptrue_b8 (), svptrue_b64 ()); +} + +/* +** test6: +** ... +** ptrue (p[0-3])\.d, all +** ... +** zip2 p0\.d, \1\.d, p[0-3]\.d +** ret +*/ +svbool_t +test6 () +{ + return svzip2_b64 (svptrue_b64 (), svptrue_b8 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_6.c new file mode 100644 index 0000000..3405004 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_6.c @@ -0,0 +1,96 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** ... +** ptrue (p[0-3])\.h, all +** ... +** uzp1 p0\.h, p[0-3]\.h, \1\.h +** ret +*/ +svbool_t +test1 () +{ + return svuzp1_b16 (svptrue_b8 (), svptrue_b16 ()); +} + +/* +** test2: +** ... +** ptrue (p[0-3])\.h, all +** ... +** uzp1 p0\.h, \1\.h, p[0-3]\.h +** ret +*/ +svbool_t +test2 () +{ + return svuzp1_b16 (svptrue_b16 (), svptrue_b8 ()); +} + +/* +** test3: +** ... +** ptrue (p[0-3])\.s, all +** ... +** uzp1 p0\.s, p[0-3]\.s, \1\.s +** ret +*/ +svbool_t +test3 () +{ + return svuzp1_b32 (svptrue_b8 (), svptrue_b32 ()); +} + +/* +** test4: +** ... +** ptrue (p[0-3])\.s, all +** ... +** uzp1 p0\.s, \1\.s, p[0-3]\.s +** ret +*/ +svbool_t +test4 () +{ + return svuzp1_b32 (svptrue_b32 (), svptrue_b8 ()); +} + +/* +** test5: +** ... +** ptrue (p[0-3])\.d, all +** ... +** uzp1 p0\.d, p[0-3]\.d, \1\.d +** ret +*/ +svbool_t +test5 () +{ + return svuzp1_b64 (svptrue_b8 (), svptrue_b64 ()); +} + +/* +** test6: +** ... +** ptrue (p[0-3])\.d, all +** ... +** uzp1 p0\.d, \1\.d, p[0-3]\.d +** ret +*/ +svbool_t +test6 () +{ + return svuzp1_b64 (svptrue_b64 (), svptrue_b8 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_7.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_7.c new file mode 100644 index 0000000..1758d00 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_7.c @@ -0,0 +1,96 @@ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** ... +** ptrue (p[0-3])\.h, all +** ... +** uzp2 p0\.h, p[0-3]\.h, \1\.h +** ret +*/ +svbool_t +test1 () +{ + return svuzp2_b16 (svptrue_b8 (), svptrue_b16 ()); +} + +/* +** test2: +** ... +** ptrue (p[0-3])\.h, all +** ... +** uzp2 p0\.h, \1\.h, p[0-3]\.h +** ret +*/ +svbool_t +test2 () +{ + return svuzp2_b16 (svptrue_b16 (), svptrue_b8 ()); +} + +/* +** test3: +** ... +** ptrue (p[0-3])\.s, all +** ... +** uzp2 p0\.s, p[0-3]\.s, \1\.s +** ret +*/ +svbool_t +test3 () +{ + return svuzp2_b32 (svptrue_b8 (), svptrue_b32 ()); +} + +/* +** test4: +** ... +** ptrue (p[0-3])\.s, all +** ... +** uzp2 p0\.s, \1\.s, p[0-3]\.s +** ret +*/ +svbool_t +test4 () +{ + return svuzp2_b32 (svptrue_b32 (), svptrue_b8 ()); +} + +/* +** test5: +** ... +** ptrue (p[0-3])\.d, all +** ... +** uzp2 p0\.d, p[0-3]\.d, \1\.d +** ret +*/ +svbool_t +test5 () +{ + return svuzp2_b64 (svptrue_b8 (), svptrue_b64 ()); +} + +/* +** test6: +** ... +** ptrue (p[0-3])\.d, all +** ... +** uzp2 p0\.d, \1\.d, p[0-3]\.d +** ret +*/ +svbool_t +test6 () +{ + return svuzp2_b64 (svptrue_b64 (), svptrue_b8 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pnext_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pnext_3.c new file mode 100644 index 0000000..d9c0090 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pnext_3.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** pnext p0\.h, p1, p0\.h +** ret +*/ +svbool_t +test1 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b8 (), + svpnext_b16 (prev, pg), + svptrue_b16 ()); +} + +/* +** test2: +** pnext p0\.h, p1, p0\.h +** ret +*/ +svbool_t +test2 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b16 (), + svpnext_b16 (prev, pg), + svptrue_b8 ()); +} + +/* +** test3: +** pnext p0\.h, p1, p0\.h +** ret +*/ +svbool_t +test3 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b16 (), + svpnext_b16 (prev, pg), + svptrue_b16 ()); +} + +/* +** test4: +** pnext p0\.s, p1, p0\.s +** ret +*/ +svbool_t +test4 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b32 (), + svpnext_b32 (prev, pg), + svptrue_b8 ()); +} + +/* +** test5: +** pnext p0\.s, p1, p0\.s +** ret +*/ +svbool_t +test5 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b16 (), + svpnext_b32 (prev, pg), + svptrue_b8 ()); +} + +/* +** test6: +** pnext p0\.s, p1, p0\.s +** ret +*/ +svbool_t +test6 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b8 (), + svpnext_b32 (prev, pg), + svptrue_b32 ()); +} + +/* +** test7: +** pnext p0\.d, p1, p0\.d +** ret +*/ +svbool_t +test7 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b16 (), + svpnext_b64 (prev, pg), + svptrue_b8 ()); +} + +/* +** test8: +** pnext p0\.d, p1, p0\.d +** ret +*/ +svbool_t +test8 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b32 (), + svpnext_b64 (prev, pg), + svptrue_b8 ()); +} + +/* +** test9: +** pnext p0\.d, p1, p0\.d +** ret +*/ +svbool_t +test9 (svbool_t pg, svbool_t prev) +{ + return svand_z (svptrue_b8 (), + svpnext_b64 (prev, pg), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr121118_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr121118_1.c new file mode 100644 index 0000000..b59a972 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr121118_1.c @@ -0,0 +1,16 @@ +/* { dg-options "-O2 -msve-vector-bits=512" } */ + +typedef __SVBool_t fixed_bool __attribute__((arm_sve_vector_bits(512))); + +#define TEST_CONST(NAME, CONST) \ + fixed_bool \ + NAME () \ + { \ + union { unsigned long long i; fixed_bool pg; } u = { CONST }; \ + return u.pg; \ + } + +TEST_CONST (test1, 0x02aaaaaaaa) +TEST_CONST (test2, 0x0155555557) +TEST_CONST (test3, 0x0013333333333333ULL) +TEST_CONST (test4, 0x0011111111111113ULL) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/rev_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/rev_2.c new file mode 100644 index 0000000..3dc4eb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/rev_2.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +svbool_t test1() +{ + return svrev_b16 (svptrue_b16 ()); +} + +svbool_t test2() +{ + return svrev_b32 (svptrue_b32 ()); +} + +svbool_t test3() +{ + return svrev_b64 (svptrue_b64 ()); +} + +/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.h} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.b} } } */ +/* { dg-final { scan-assembler {\trev\tp0\.h} } } */ +/* { dg-final { scan-assembler {\trev\tp0\.s} } } */ +/* { dg-final { scan-assembler {\trev\tp0\.d} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/unpkhi_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/unpkhi_1.c new file mode 100644 index 0000000..9c7b4bc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/unpkhi_1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +svbool_t +test1 (svbool_t p) +{ + return svand_z (svptrue_b8 (), svunpkhi (p), svptrue_b16 ()); +} + +svbool_t +test2 (svbool_t p) +{ + return svand_z (svptrue_b16 (), svunpkhi (p), svptrue_b8 ()); +} + +svbool_t +test3 (svbool_t p) +{ + return svand_z (svptrue_b16 (), svunpkhi (p), svptrue_b16 ()); +} + +/* { dg-final { scan-assembler-not {\tand\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/unpklo_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/unpklo_1.c new file mode 100644 index 0000000..f072a2f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/unpklo_1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +svbool_t +test1 (svbool_t p) +{ + return svand_z (svptrue_b8 (), svunpklo (p), svptrue_b16 ()); +} + +svbool_t +test2 (svbool_t p) +{ + return svand_z (svptrue_b16 (), svunpklo (p), svptrue_b8 ()); +} + +svbool_t +test3 (svbool_t p) +{ + return svand_z (svptrue_b16 (), svunpklo (p), svptrue_b16 ()); +} + +/* { dg-final { scan-assembler-not {\tand\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_13.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_13.c new file mode 100644 index 0000000..cf50dc1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_13.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** whilele p0\.h, w0, w1 +** ret +*/ +svbool_t +test1 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilele_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test2: +** whilele p0\.h, x0, x1 +** ret +*/ +svbool_t +test2 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilele_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test3: +** whilels p0\.s, w0, w1 +** ret +*/ +svbool_t +test3 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilele_b32 (x, y), + svptrue_b16 ()); +} + +/* +** test4: +** whilels p0\.s, x0, x1 +** ret +*/ +svbool_t +test4 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b8 (), + svwhilele_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test5: +** whilele p0\.s, w0, w1 +** ret +*/ +svbool_t +test5 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b16 (), + svwhilele_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test6: +** whilels p0\.s, w0, w1 +** ret +*/ +svbool_t +test6 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b32 (), + svwhilele_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test7: +** whilels p0\.d, w0, w1 +** ret +*/ +svbool_t +test7 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilele_b64 (x, y), + svptrue_b64 ()); +} + +/* +** test8: +** whilele p0\.d, x0, x1 +** ret +*/ +svbool_t +test8 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilele_b64 (x, y), + svptrue_b32 ()); +} + +/* +** test9: +** whilels p0\.d, x0, x1 +** ret +*/ +svbool_t +test9 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b64 (), + svwhilele_b64 (x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_6.c new file mode 100644 index 0000000..27bf0c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_6.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** whilelt p0\.h, w0, w1 +** ret +*/ +svbool_t +test1 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilelt_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test2: +** whilelt p0\.h, x0, x1 +** ret +*/ +svbool_t +test2 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilelt_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test3: +** whilelo p0\.s, w0, w1 +** ret +*/ +svbool_t +test3 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilelt_b32 (x, y), + svptrue_b16 ()); +} + +/* +** test4: +** whilelo p0\.s, x0, x1 +** ret +*/ +svbool_t +test4 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b8 (), + svwhilelt_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test5: +** whilelt p0\.s, w0, w1 +** ret +*/ +svbool_t +test5 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b16 (), + svwhilelt_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test6: +** whilelo p0\.s, w0, w1 +** ret +*/ +svbool_t +test6 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b32 (), + svwhilelt_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test7: +** whilelo p0\.d, w0, w1 +** ret +*/ +svbool_t +test7 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilelt_b64 (x, y), + svptrue_b64 ()); +} + +/* +** test8: +** whilelt p0\.d, x0, x1 +** ret +*/ +svbool_t +test8 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilelt_b64 (x, y), + svptrue_b32 ()); +} + +/* +** test9: +** whilelo p0\.d, x0, x1 +** ret +*/ +svbool_t +test9 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b64 (), + svwhilelt_b64 (x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_1.c index 38dfdd4..e777f03 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=neoverse-n2" } */ +/* { dg-options "-O2 -mcpu=neoverse-n2 -fdisable-rtl-combine" } */ /* { dg-final { check-function-bodies "**" "" } } */ #pragma GCC target "+sve" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_2.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_2.c index 45363cc..41182e1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=neoverse-v2" } */ +/* { dg-options "-O2 -mcpu=neoverse-v2 -fdisable-rtl-combine" } */ /* { dg-final { check-function-bodies "**" "" } } */ #pragma GCC target "+sve" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_3.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_3.c index c50a581..04a9023 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=neoverse-v1" } */ +/* { dg-options "-O2 -mcpu=neoverse-v1 -fdisable-rtl-combine" } */ /* { dg-final { check-function-bodies "**" "" } } */ #pragma GCC target "+sve" diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/match_4.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/match_4.c new file mode 100644 index 0000000..57f625b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/match_4.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +svbool_t +test1 (svbool_t pg, svint16_t x, svint16_t y) +{ + return svand_z (svptrue_b8 (), + svmatch (pg, x, y), + svptrue_b16 ()); +} + +svbool_t +test2 (svbool_t pg, svint16_t x, svint16_t y) +{ + return svand_z (svptrue_b16 (), + svmatch (pg, x, y), + svptrue_b8 ()); +} + +svbool_t +test3 (svbool_t pg, svint16_t x, svint16_t y) +{ + return svand_z (svptrue_b16 (), + svmatch (pg, x, y), + svptrue_b16 ()); +} + +/* { dg-final { scan-assembler-not {\tand\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/nmatch_1.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/nmatch_1.c new file mode 100644 index 0000000..a3b1e2d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/nmatch_1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <arm_sve.h> + +svbool_t +test1 (svbool_t pg, svint16_t x, svint16_t y) +{ + return svand_z (svptrue_b8 (), + svnmatch (pg, x, y), + svptrue_b16 ()); +} + +svbool_t +test2 (svbool_t pg, svint16_t x, svint16_t y) +{ + return svand_z (svptrue_b16 (), + svnmatch (pg, x, y), + svptrue_b8 ()); +} + +svbool_t +test3 (svbool_t pg, svint16_t x, svint16_t y) +{ + return svand_z (svptrue_b16 (), + svnmatch (pg, x, y), + svptrue_b16 ()); +} + +/* { dg-final { scan-assembler-not {\tand\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilege_1.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilege_1.c new file mode 100644 index 0000000..07b56a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilege_1.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** whilege p0\.h, w0, w1 +** ret +*/ +svbool_t +test1 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilege_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test2: +** whilege p0\.h, x0, x1 +** ret +*/ +svbool_t +test2 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilege_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test3: +** whilehs p0\.s, w0, w1 +** ret +*/ +svbool_t +test3 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilege_b32 (x, y), + svptrue_b16 ()); +} + +/* +** test4: +** whilehs p0\.s, x0, x1 +** ret +*/ +svbool_t +test4 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b8 (), + svwhilege_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test5: +** whilege p0\.s, w0, w1 +** ret +*/ +svbool_t +test5 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b16 (), + svwhilege_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test6: +** whilehs p0\.s, w0, w1 +** ret +*/ +svbool_t +test6 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b32 (), + svwhilege_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test7: +** whilehs p0\.d, w0, w1 +** ret +*/ +svbool_t +test7 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilege_b64 (x, y), + svptrue_b64 ()); +} + +/* +** test8: +** whilege p0\.d, x0, x1 +** ret +*/ +svbool_t +test8 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilege_b64 (x, y), + svptrue_b32 ()); +} + +/* +** test9: +** whilehs p0\.d, x0, x1 +** ret +*/ +svbool_t +test9 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b64 (), + svwhilege_b64 (x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilegt_1.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilegt_1.c new file mode 100644 index 0000000..df707c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilegt_1.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** whilegt p0\.h, w0, w1 +** ret +*/ +svbool_t +test1 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilegt_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test2: +** whilegt p0\.h, x0, x1 +** ret +*/ +svbool_t +test2 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilegt_b16 (x, y), + svptrue_b16 ()); +} + +/* +** test3: +** whilehi p0\.s, w0, w1 +** ret +*/ +svbool_t +test3 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilegt_b32 (x, y), + svptrue_b16 ()); +} + +/* +** test4: +** whilehi p0\.s, x0, x1 +** ret +*/ +svbool_t +test4 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b8 (), + svwhilegt_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test5: +** whilegt p0\.s, w0, w1 +** ret +*/ +svbool_t +test5 (int32_t x, int32_t y) +{ + return svand_z (svptrue_b16 (), + svwhilegt_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test6: +** whilehi p0\.s, w0, w1 +** ret +*/ +svbool_t +test6 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b32 (), + svwhilegt_b32 (x, y), + svptrue_b32 ()); +} + +/* +** test7: +** whilehi p0\.d, w0, w1 +** ret +*/ +svbool_t +test7 (uint32_t x, uint32_t y) +{ + return svand_z (svptrue_b8 (), + svwhilegt_b64 (x, y), + svptrue_b64 ()); +} + +/* +** test8: +** whilegt p0\.d, x0, x1 +** ret +*/ +svbool_t +test8 (int64_t x, int64_t y) +{ + return svand_z (svptrue_b16 (), + svwhilegt_b64 (x, y), + svptrue_b32 ()); +} + +/* +** test9: +** whilehi p0\.d, x0, x1 +** ret +*/ +svbool_t +test9 (uint64_t x, uint64_t y) +{ + return svand_z (svptrue_b64 (), + svwhilegt_b64 (x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilerw_5.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilerw_5.c new file mode 100644 index 0000000..0c24199 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilerw_5.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** whilerw p0\.h, x0, x1 +** ret +*/ +svbool_t +test1 (int16_t *x, int16_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilerw (x, y), + svptrue_b16 ()); +} + +/* +** test2: +** whilerw p0\.h, x0, x1 +** ret +*/ +svbool_t +test2 (uint16_t *x, uint16_t *y) +{ + return svand_z (svptrue_b16 (), + svwhilerw (x, y), + svptrue_b16 ()); +} + +/* +** test3: +** whilerw p0\.s, x0, x1 +** ret +*/ +svbool_t +test3 (int32_t *x, int32_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilerw (x, y), + svptrue_b16 ()); +} + +/* +** test4: +** whilerw p0\.s, x0, x1 +** ret +*/ +svbool_t +test4 (uint32_t *x, uint32_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilerw (x, y), + svptrue_b32 ()); +} + +/* +** test5: +** whilerw p0\.s, x0, x1 +** ret +*/ +svbool_t +test5 (float32_t *x, float32_t *y) +{ + return svand_z (svptrue_b16 (), + svwhilerw (x, y), + svptrue_b32 ()); +} + +/* +** test6: +** whilerw p0\.s, x0, x1 +** ret +*/ +svbool_t +test6 (int32_t *x, int32_t *y) +{ + return svand_z (svptrue_b32 (), + svwhilerw (x, y), + svptrue_b32 ()); +} + +/* +** test7: +** whilerw p0\.d, x0, x1 +** ret +*/ +svbool_t +test7 (int64_t *x, int64_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilerw (x, y), + svptrue_b64 ()); +} + +/* +** test8: +** whilerw p0\.d, x0, x1 +** ret +*/ +svbool_t +test8 (uint64_t *x, uint64_t *y) +{ + return svand_z (svptrue_b16 (), + svwhilerw (x, y), + svptrue_b32 ()); +} + +/* +** test9: +** whilerw p0\.d, x0, x1 +** ret +*/ +svbool_t +test9 (float64_t *x, float64_t *y) +{ + return svand_z (svptrue_b64 (), + svwhilerw (x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilewr_5.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilewr_5.c new file mode 100644 index 0000000..38db9af --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/whilewr_5.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** test1: +** whilewr p0\.h, x0, x1 +** ret +*/ +svbool_t +test1 (int16_t *x, int16_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilewr (x, y), + svptrue_b16 ()); +} + +/* +** test2: +** whilewr p0\.h, x0, x1 +** ret +*/ +svbool_t +test2 (uint16_t *x, uint16_t *y) +{ + return svand_z (svptrue_b16 (), + svwhilewr (x, y), + svptrue_b16 ()); +} + +/* +** test3: +** whilewr p0\.s, x0, x1 +** ret +*/ +svbool_t +test3 (int32_t *x, int32_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilewr (x, y), + svptrue_b16 ()); +} + +/* +** test4: +** whilewr p0\.s, x0, x1 +** ret +*/ +svbool_t +test4 (uint32_t *x, uint32_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilewr (x, y), + svptrue_b32 ()); +} + +/* +** test5: +** whilewr p0\.s, x0, x1 +** ret +*/ +svbool_t +test5 (float32_t *x, float32_t *y) +{ + return svand_z (svptrue_b16 (), + svwhilewr (x, y), + svptrue_b32 ()); +} + +/* +** test6: +** whilewr p0\.s, x0, x1 +** ret +*/ +svbool_t +test6 (int32_t *x, int32_t *y) +{ + return svand_z (svptrue_b32 (), + svwhilewr (x, y), + svptrue_b32 ()); +} + +/* +** test7: +** whilewr p0\.d, x0, x1 +** ret +*/ +svbool_t +test7 (int64_t *x, int64_t *y) +{ + return svand_z (svptrue_b8 (), + svwhilewr (x, y), + svptrue_b64 ()); +} + +/* +** test8: +** whilewr p0\.d, x0, x1 +** ret +*/ +svbool_t +test8 (uint64_t *x, uint64_t *y) +{ + return svand_z (svptrue_b16 (), + svwhilewr (x, y), + svptrue_b32 ()); +} + +/* +** test9: +** whilewr p0\.d, x0, x1 +** ret +*/ +svbool_t +test9 (float64_t *x, float64_t *y) +{ + return svand_z (svptrue_b64 (), + svwhilewr (x, y), + svptrue_b64 ()); +} + +#ifdef __cplusplus +} +#endif diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc index 3974c4d..00315d1 100644 --- a/gcc/tree-ssa-sccvn.cc +++ b/gcc/tree-ssa-sccvn.cc @@ -3549,8 +3549,95 @@ vn_reference_lookup_3 (ao_ref *ref, tree vuse, void *data_, /* Find the common base of ref and the lhs. lhs_ops already contains valueized operands for the lhs. */ + poly_int64 extra_off = 0; i = vr->operands.length () - 1; j = lhs_ops.length () - 1; + + /* The base should be always equal due to the above check. */ + if (! vn_reference_op_eq (&vr->operands[i], &lhs_ops[j])) + return (void *)-1; + i--, j--; + + /* The 2nd component should always exist and be a MEM_REF. */ + if (!(i >= 0 && j >= 0)) + ; + else if (vn_reference_op_eq (&vr->operands[i], &lhs_ops[j])) + i--, j--; + else if (vr->operands[i].opcode == MEM_REF + && lhs_ops[j].opcode == MEM_REF + && known_ne (lhs_ops[j].off, -1) + && known_ne (vr->operands[i].off, -1)) + { + bool found = false; + /* When we ge a mismatch at a MEM_REF that is not the sole component + try finding a match in one of the outer components and continue + stripping there. This happens when addresses of components get + forwarded into dereferences. */ + if (j > 0) + { + int temi = i - 1; + extra_off = vr->operands[i].off; + while (temi >= 0 + && known_ne (vr->operands[temi].off, -1)) + { + if (vr->operands[temi].type + && lhs_ops[j].type + && (TYPE_MAIN_VARIANT (vr->operands[temi].type) + == TYPE_MAIN_VARIANT (lhs_ops[j].type))) + { + i = temi; + /* Strip the component that was type matched to + the MEM_REF. */ + extra_off += vr->operands[i].off - lhs_ops[j].off; + i--, j--; + /* Strip further equal components. */ + found = true; + break; + } + extra_off += vr->operands[temi].off; + temi--; + } + } + if (!found && i > 0) + { + int temj = j - 1; + extra_off = -lhs_ops[j].off; + while (temj >= 0 + && known_ne (lhs_ops[temj].off, -1)) + { + if (vr->operands[i].type + && lhs_ops[temj].type + && (TYPE_MAIN_VARIANT (vr->operands[i].type) + == TYPE_MAIN_VARIANT (lhs_ops[temj].type))) + { + j = temj; + /* Strip the component that was type matched to + the MEM_REF. */ + extra_off += vr->operands[i].off - lhs_ops[j].off; + i--, j--; + /* Strip further equal components. */ + found = true; + break; + } + extra_off += -lhs_ops[temj].off; + temj--; + } + } + /* When the LHS is already at the outermost level simply + adjust for any offset difference. Further lookups + will fail when there's too gross of a type compatibility + issue. */ + if (!found && j == 0) + { + extra_off = vr->operands[i].off - lhs_ops[j].off; + i--, j--; + } + } + else + return (void *)-1; + + /* Strip further common components, attempting to consume lhs_ops + in full. */ while (j >= 0 && i >= 0 && vn_reference_op_eq (&vr->operands[i], &lhs_ops[j])) { @@ -3558,27 +3645,6 @@ vn_reference_lookup_3 (ao_ref *ref, tree vuse, void *data_, j--; } - /* ??? The innermost op should always be a MEM_REF and we already - checked that the assignment to the lhs kills vr. Thus for - aggregate copies using char[] types the vn_reference_op_eq - may fail when comparing types for compatibility. But we really - don't care here - further lookups with the rewritten operands - will simply fail if we messed up types too badly. */ - poly_int64 extra_off = 0; - if (j == 0 && i >= 0 - && lhs_ops[0].opcode == MEM_REF - && maybe_ne (lhs_ops[0].off, -1)) - { - if (known_eq (lhs_ops[0].off, vr->operands[i].off)) - i--, j--; - else if (vr->operands[i].opcode == MEM_REF - && maybe_ne (vr->operands[i].off, -1)) - { - extra_off = vr->operands[i].off - lhs_ops[0].off; - i--, j--; - } - } - /* i now points to the first additional op. ??? LHS may not be completely contained in VR, one or more VIEW_CONVERT_EXPRs could be in its way. We could at least diff --git a/libcpp/macro.cc b/libcpp/macro.cc index be25710..d869b02 100644 --- a/libcpp/macro.cc +++ b/libcpp/macro.cc @@ -1003,7 +1003,10 @@ stringify_arg (cpp_reader *pfile, const cpp_token **first, unsigned int count) /* Ignore the final \ of invalid string literals. */ if (backslash_count & 1) { - cpp_error (pfile, CPP_DL_WARNING, + cpp_error (pfile, + CPP_OPTION (pfile, cplusplus) + && CPP_OPTION (pfile, lang) >= CLK_GNUCXX26 + ? CPP_DL_PEDWARN : CPP_DL_WARNING, "invalid string literal, ignoring final %<\\%>"); dest--; } diff --git a/libstdc++-v3/include/bits/indirect.h b/libstdc++-v3/include/bits/indirect.h index e8000d7..89fa8c8 100644 --- a/libstdc++-v3/include/bits/indirect.h +++ b/libstdc++-v3/include/bits/indirect.h @@ -286,8 +286,11 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION constexpr auto&& operator*(this _Self&& __self) noexcept { - __glibcxx_assert(__self._M_objp != nullptr); - return std::forward_like<_Self>(*((_Self)__self)._M_objp); + // n.b. [allocator.requirements.general] p22 implies + // dereferencing const pointer is same as pointer + const indirect& __iself = (const indirect&)__self; + __glibcxx_assert(__iself._M_objp != nullptr); + return std::forward_like<_Self>(*__iself._M_objp); } constexpr const_pointer diff --git a/libstdc++-v3/testsuite/std/memory/indirect/access.cc b/libstdc++-v3/testsuite/std/memory/indirect/access.cc new file mode 100644 index 0000000..cf21275 --- /dev/null +++ b/libstdc++-v3/testsuite/std/memory/indirect/access.cc @@ -0,0 +1,58 @@ +// { dg-do run { target c++26 } } + +#include <memory> +#include <vector> + +#include <testsuite_hooks.h> + +template<template<typename> class Indirect> +constexpr void +test_access() +{ + const std::vector<int> src{1, 2, 3, 4, 5}; + Indirect<std::vector<int>> i(src); + auto const& ci = i; + VERIFY( *i == src ); + VERIFY( *ci == src ); + VERIFY( *std::move(ci) == src ); + + std::vector<int>&& vr = *std::move(i); + VERIFY( vr == src ); + VERIFY( *i == src ); + + std::vector<int> vc = *std::move(i); + VERIFY( vc == src ); + VERIFY( vr.empty() ); + VERIFY( i->empty() ); + VERIFY( ci->empty() ); +} + +template<typename T> +struct PublicBase : std::indirect<T> +{ + using std::indirect<T>::indirect; +}; + +template<typename T> +class PrivateBase : std::indirect<T> +{ +public: + using std::indirect<T>::indirect; + using std::indirect<T>::operator*; + using std::indirect<T>::operator->; +}; + +constexpr bool +test_all() +{ + test_access<std::indirect>(); + test_access<PublicBase>(); + test_access<PrivateBase>(); + return true; +} + +int main() +{ + test_all(); + static_assert(test_all()); +} diff --git a/libstdc++-v3/testsuite/std/memory/polymorphic/access.cc b/libstdc++-v3/testsuite/std/memory/polymorphic/access.cc new file mode 100644 index 0000000..7b95bb1 --- /dev/null +++ b/libstdc++-v3/testsuite/std/memory/polymorphic/access.cc @@ -0,0 +1,53 @@ +// { dg-do run { target c++26 } } + +#include <memory> +#include <vector> + +#include <testsuite_hooks.h> + +template<template<typename> class Polymorhpic> +constexpr void +test_access() +{ + const std::vector<int> src{1, 2, 3, 4, 5}; + Polymorhpic<std::vector<int>> i(src); + auto const& ci = i; + VERIFY( *i == src ); + VERIFY( *ci == src ); + VERIFY( *std::move(ci) == src ); + + auto&& vr = *std::move(i); + static_assert( std::is_same_v<decltype(vr), std::vector<int>&> ); + VERIFY( vr == src ); + VERIFY( *i == src ); +} + +template<typename T> +struct PublicBase : std::polymorphic<T> +{ + using std::polymorphic<T>::polymorphic; +}; + +template<typename T> +class PrivateBase : std::polymorphic<T> +{ +public: + using std::polymorphic<T>::polymorphic; + using std::polymorphic<T>::operator*; + using std::polymorphic<T>::operator->; +}; + +constexpr bool +test_all() +{ + test_access<std::polymorphic>(); + test_access<PublicBase>(); + test_access<PrivateBase>(); + return true; +} + +int main() +{ + test_all(); +// static_assert(test_all()); +} |