simplify-rtx: Simplify subregs of logic ops

This patch adds a new rule for distributing lowpart subregs through
ANDs, IORs, and XORs with a constant, in cases where one of the terms
then disappears.  For example:

  (lowart-subreg:QI (and:HI x 0x100))

simplifies to zero and

  (lowart-subreg:QI (and:HI x 0xff))

simplifies to (lowart-subreg:QI x).

This would often be handled at some point using nonzero bits.  However,
the specific case I want the optimisation for is SVE predicates,
where nonzero bit tracking isn't currently an option.  Specifically:
the predicate modes VNx8BI, VNx4BI and VNx2BI have the same size as
VNx16BI, but treat only every second, fourth, or eighth bit as
significant.  Thus if we have:

  (subreg:VNx8BI (and:VNx16BI x C))

where C is the repeating constant { 1, 0, 1, 0, ... }, then the
AND only clears bits that are made insignificant by the subreg,
and so the result is equal to (subreg:VNx8BI x).  Later patches
rely on this.

gcc/
	* simplify-rtx.cc (simplify_context::simplify_subreg): Distribute
	lowpart subregs through AND/IOR/XOR, if doing so eliminates one
	of the terms.
	(test_scalar_int_ext_ops): Add some tests of the above for integers.
	* config/aarch64/aarch64.cc (aarch64_test_sve_folding): Likewise
	add tests for predicate modes.

0 files changed, 0 insertions, 0 deletions