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| author | Soumya AR <soumyaa@nvidia.com> | 2024-10-08 14:37:24 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2024-10-08 14:37:24 +0100 |
| commit | c94adf02d31028a25bb7b20ec77aade9d502430b (patch) | |
| tree | e1b70dc936921376f50dc567ee85dd2b078d2174 /libcpp/generated_cpp_wcwidth.h | |
| parent | 34ae3a992a0cc3240d07d69ff12a664cbb5c8be0 (diff) | |
| download | gcc-c94adf02d31028a25bb7b20ec77aade9d502430b.zip gcc-c94adf02d31028a25bb7b20ec77aade9d502430b.tar.gz gcc-c94adf02d31028a25bb7b20ec77aade9d502430b.tar.bz2 | |
aarch64: Expand CTZ to RBIT + CLZ for SVE [PR109498]
Currently, we vectorize CTZ for SVE by using the following operation:
.CTZ (X) = (PREC - 1) - .CLZ (X & -X)
Instead, this patch expands CTZ to RBIT + CLZ for SVE, as suggested in PR109498.
The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression.
OK for mainline?
Signed-off-by: Soumya AR <soumyaa@nvidia.com>
gcc/ChangeLog:
PR target/109498
* config/aarch64/aarch64-sve.md (ctz<mode>2): Added pattern to expand
CTZ to RBIT + CLZ for SVE.
gcc/testsuite/ChangeLog:
PR target/109498
* gcc.target/aarch64/sve/ctz.c: New test.
Diffstat (limited to 'libcpp/generated_cpp_wcwidth.h')
0 files changed, 0 insertions, 0 deletions