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| author | Kito Cheng <kito.cheng@sifive.com> | 2025-05-12 14:36:07 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2025-05-19 11:37:33 +0800 |
| commit | c9eb473fb9946f642506d24f4131d7c83855fd78 (patch) | |
| tree | 528dcd147ba974577d37fc25f37b2e0c1e976407 /gcc | |
| parent | 3fc902e738bbf3f4b842ae0faa9313c7aee49e98 (diff) | |
| download | gcc-c9eb473fb9946f642506d24f4131d7c83855fd78.zip gcc-c9eb473fb9946f642506d24f4131d7c83855fd78.tar.gz gcc-c9eb473fb9946f642506d24f4131d7c83855fd78.tar.bz2 | |
RISC-V: Add new operand constraint: cR
This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose register
(x8-x15) in inline asm.
Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102
gcc/ChangeLog:
* config/riscv/constraints.md (cR): New constraint.
* doc/md.texi (Machine Constraints::RISC-V): Document the new cR
constraint.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/constraint-cR-pair.c: New test case.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/constraints.md | 4 | ||||
| -rw-r--r-- | gcc/doc/md.texi | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c | 13 |
3 files changed, 20 insertions, 0 deletions
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 18556a5..58355cf 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -43,6 +43,10 @@ (define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : (TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)" "RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use zfinx.") +(define_register_constraint "cR" "RVC_GR_REGS" + "Even-odd RVC general purpose register (x8-x15)." + "regno % 2 == 0") + ;; General constraints (define_constraint "I" diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index f6314af..1a1c1b7 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3694,6 +3694,9 @@ RVC general purpose register (x8-x15). RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use zfinx. +@item cR +Even-odd RVC general purpose register pair. + @item R Even-odd general purpose register pair. diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c new file mode 100644 index 0000000..479246b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int m0, int m1) { +/* +** foo: +** ... +** addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0) +** ... +*/ + __asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory"); +} |