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| author | Pan Li <pan2.li@intel.com> | 2025-06-05 11:04:33 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2025-06-05 21:24:36 +0800 |
| commit | 8cf31de8c8fec295c5f627b399d9e015df266297 (patch) | |
| tree | 1cecd6d197b7ebc453aa77ed1ab800af5cf232bd /gcc | |
| parent | 1d90f8c7933eb225e26b7598960bc220a582c452 (diff) | |
| download | gcc-8cf31de8c8fec295c5f627b399d9e015df266297.zip gcc-8cf31de8c8fec295c5f627b399d9e015df266297.tar.gz gcc-8cf31de8c8fec295c5f627b399d9e015df266297.tar.bz2 | |
RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
The div of rvv has not such insn v2 = div (vec_dup (x), v1), thus
the generated rtl like that hit the unreachable assert when
expand insn. This patch would like to remove op div from
the binary op form (vec_dup (x), v) to avoid pattern matching
by mistake.
No new test introduced as pr33576.c covered already.
The below test suites are passed for this patch series.
* The rv64gcv fully regression test.
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Leverage vdup_v and v_vdup
binary op for different patterns.
* config/riscv/vector-iterators.md: Add vdup_v and v_vdup
binary op iterators.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/autovec-opt.md | 4 | ||||
| -rw-r--r-- | gcc/config/riscv/vector-iterators.md | 6 |
2 files changed, 7 insertions, 3 deletions
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 19eb16c..4465eb2 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -1682,7 +1682,7 @@ ;; ============================================================================= (define_insn_and_split "*<optab>_vx_<mode>" [(set (match_operand:V_VLSI 0 "register_operand") - (any_int_binop_no_shift_vx:V_VLSI + (any_int_binop_no_shift_vdup_v:V_VLSI (vec_duplicate:V_VLSI (match_operand:<VEL> 1 "register_operand")) (match_operand:V_VLSI 2 "<binop_rhs2_predicate>")))] @@ -1699,7 +1699,7 @@ (define_insn_and_split "*<optab>_vx_<mode>" [(set (match_operand:V_VLSI 0 "register_operand") - (any_int_binop_no_shift_vx:V_VLSI + (any_int_binop_no_shift_v_vdup:V_VLSI (match_operand:V_VLSI 1 "<binop_rhs2_predicate>") (vec_duplicate:V_VLSI (match_operand:<VEL> 2 "register_operand"))))] diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 62fd1c0..86f31f3 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -4041,10 +4041,14 @@ smax umax smin umin mult div udiv mod umod ]) -(define_code_iterator any_int_binop_no_shift_vx [ +(define_code_iterator any_int_binop_no_shift_v_vdup [ plus minus and ior xor mult div ]) +(define_code_iterator any_int_binop_no_shift_vdup_v [ + plus minus and ior xor mult +]) + (define_code_iterator any_int_unop [neg not]) (define_code_iterator any_commutative_binop [plus and ior xor |