RISC-V: Add patterns for vector-scalar IEEE floating-point min

This pattern enables the combine pass (or late-combine, depending on the case)
to merge a vec_duplicate into an unspec_vfmin RTL instruction.

Before this patch, we have two instructions, e.g.:
  vfmv.v.f       v2,fa0
  vfmin.vv       v1,v1,v2

After, we get only one:
  vfmin.vf       v1,v1,fa0

gcc/ChangeLog:

	* config/riscv/autovec-opt.md
	(*vfmin_vf_ieee_<mode>): Add new patterns to combine vec_duplicate +
	vfmin.vv (unspec) into vfmin.vf.
	(*vfmul_vf_<mode>, *vfrdiv_vf_<mode>, *vfmin_vf_<mode>): Fix attribute
	types.
	* config/riscv/vector.md (@pred_<ieee_fmaxmin_op><mode>_scalar): Allow
	VLS modes.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Add vfmin.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c: New test.

17 files changed, 139 insertions, 14 deletions

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index c66de7d..9695fdc 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -2066,7 +2066,7 @@
 				   riscv_vector::BINARY_OP_FRM_DYN, operands);
     DONE;
   }
-  [(set_attr "type" "vfmuladd")]
+  [(set_attr "type" "vfmul")]
 )
 
 ;; vfrdiv.vf
@@ -2085,7 +2085,7 @@
 				   riscv_vector::BINARY_OP_FRM_DYN, operands);
     DONE;
   }
-  [(set_attr "type" "vfmuladd")]
+  [(set_attr "type" "vfdiv")]
 )
 
 ;; vfmin.vf
@@ -2104,5 +2104,43 @@
 				   riscv_vector::BINARY_OP, operands);
     DONE;
   }
-  [(set_attr "type" "vfmuladd")]
+  [(set_attr "type" "vfminmax")]
+)
+
+(define_insn_and_split "*vfmin_vf_ieee_<mode>"
+  [(set (match_operand:V_VLSF 0 "register_operand")
+    (unspec:V_VLSF [
+      (vec_duplicate:V_VLSF
+	(match_operand:<VEL> 2 "register_operand"))
+      (match_operand:V_VLSF 1 "register_operand")
+      ] UNSPEC_VFMIN))]
+  "TARGET_VECTOR && !HONOR_SNANS (<MODE>mode) && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+  {
+    riscv_vector::emit_vlmax_insn (code_for_pred_scalar (UNSPEC_VFMIN, <MODE>mode),
+				   riscv_vector::BINARY_OP, operands);
+    DONE;
+  }
+  [(set_attr "type" "vfminmax")]
+)
+
+(define_insn_and_split "*vfmin_vf_ieee_<mode>"
+  [(set (match_operand:V_VLSF 0 "register_operand")
+    (unspec:V_VLSF [
+      (match_operand:V_VLSF 1 "register_operand")
+      (vec_duplicate:V_VLSF
+	(match_operand:<VEL> 2 "register_operand"))
+      ] UNSPEC_VFMIN))]
+  "TARGET_VECTOR && !HONOR_SNANS (<MODE>mode) && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+  {
+    riscv_vector::emit_vlmax_insn (code_for_pred_scalar (UNSPEC_VFMIN, <MODE>mode),
+				   riscv_vector::BINARY_OP, operands);
+    DONE;
+  }
+  [(set_attr "type" "vfminmax")]
 )
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 057c3f5..603d2b8 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6462,22 +6462,22 @@
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_<ieee_fmaxmin_op><mode>_scalar"
-  [(set (match_operand:VF 0 "register_operand"           "=vd, vd, vr, vr")
-	(if_then_else:VF
+  [(set (match_operand:V_VLSF 0 "register_operand"         "=vd, vd, vr, vr")
+	(if_then_else:V_VLSF
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
-	     (match_operand 5 "vector_length_operand"    "rvl,rvl,rvl,rvl")
-	     (match_operand 6 "const_int_operand"        "  i,  i,  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i,  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"   " vm, vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"      "rvl,rvl,rvl,rvl")
+	     (match_operand 6 "const_int_operand"          "  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"          "  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"          "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (unspec:VF
-	    [(match_operand:VF 3 "register_operand"        " vr, vr, vr, vr")
-	      (vec_duplicate:VF
+	  (unspec:V_VLSF
+	    [(match_operand:V_VLSF 3 "register_operand"    " vr, vr, vr, vr")
+	      (vec_duplicate:V_VLSF
 		(match_operand:<VEL> 4 "register_operand"  "  f,  f,  f,  f"))]
 	      UNSPEC_VFMAXMIN)
-	  (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
+	  (match_operand:V_VLSF 2 "vector_merge_operand"   " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "v<ieee_fmaxmin_op>.vf\t%0,%3,%4%p1"
   [(set_attr "type" "vfminmax")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
index b6ad62c..9db8736 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
@@ -17,4 +17,5 @@
 /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
 /* { dg-final { scan-assembler-not {vfmul.vf} } } */
 /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler-not {vfmin.vf} } } */
 /* { dg-final { scan-assembler {fcvt.s.h} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
index 14843d1..577ad8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
@@ -17,4 +17,5 @@
 /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
 /* { dg-final { scan-assembler-not {vfmul.vf} } } */
 /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler-not {vfmin.vf} } } */
 /* { dg-final { scan-assembler {fcvt.d.s} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
index 7d67525..30e5660 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
@@ -13,3 +13,4 @@
 /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */
 /* { dg-final { scan-assembler-not {vfmul.vf} } } */
 /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler-not {vfmin.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c
new file mode 100644
index 0000000..1a20ee7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+
+DEF_VF_BINOP_CASE_2_WRAP (_Float16, __builtin_fminf16, min)
+
+/* { dg-final { scan-assembler-times {vfmin.vf} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c
new file mode 100644
index 0000000..1e0f7f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+
+DEF_VF_BINOP_CASE_2_WRAP (float, __builtin_fminf, min)
+
+/* { dg-final { scan-assembler-times {vfmin.vf} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c
new file mode 100644
index 0000000..61db2df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+
+DEF_VF_BINOP_CASE_2_WRAP (double, __builtin_fmin, min)
+
+/* { dg-final { scan-assembler-times {vfmin.vf} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c
new file mode 100644
index 0000000..392580a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=1" } */
+
+#include "vf-5-f16.c"
+
+/* { dg-final { scan-assembler-not {vfmin.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c
new file mode 100644
index 0000000..9dbd226
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=1" } */
+
+#include "vf-5-f32.c"
+
+/* { dg-final { scan-assembler-not {vfmin.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c
new file mode 100644
index 0000000..44a17cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=1" } */
+
+#include "vf-5-f64.c"
+
+/* { dg-final { scan-assembler-not {vfmin.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c
new file mode 100644
index 0000000..0883c882
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+
+DEF_VF_BINOP_CASE_3_WRAP (_Float16, __builtin_fminf16, min, VF_BINOP_FUNC_BODY_X128)
+
+/* { dg-final { scan-assembler {vfmin.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c
new file mode 100644
index 0000000..8528240
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+
+DEF_VF_BINOP_CASE_3_WRAP (float, __builtin_fminf, min, VF_BINOP_FUNC_BODY_X128)
+
+/* { dg-final { scan-assembler {vfmin.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c
new file mode 100644
index 0000000..474b339
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+
+DEF_VF_BINOP_CASE_3_WRAP (double, __builtin_fmin, min, VF_BINOP_FUNC_BODY_X128)
+
+/* { dg-final { scan-assembler {vfmin.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c
new file mode 100644
index 0000000..bd68b3c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=4" } */
+
+#include "vf-7-f16.c"
+
+/* { dg-final { scan-assembler-not {vfmin.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c
new file mode 100644
index 0000000..000402c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */
+
+#include "vf-7-f32.c"
+
+/* { dg-final { scan-assembler-not {vfmin.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c
new file mode 100644
index 0000000..89dec81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */
+
+#include "vf-7-f64.c"
+
+/* { dg-final { scan-assembler-not {vfmin.vf} } } */