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| author | Jiawei <jiawei@iscas.ac.cn> | 2025-05-10 19:26:35 +0800 |
|---|---|---|
| committer | Jiawei <jiawei@iscas.ac.cn> | 2025-05-11 11:45:56 +0800 |
| commit | 66d17ba3cb47980455ee9d6b4123dce61aef2fa2 (patch) | |
| tree | b552dee84e624dc71f1de528153cfabc8d991821 /gcc | |
| parent | 43b450e3f72a53c744e77f55393962f1d349373a (diff) | |
| download | gcc-66d17ba3cb47980455ee9d6b4123dce61aef2fa2.zip gcc-66d17ba3cb47980455ee9d6b4123dce61aef2fa2.tar.gz gcc-66d17ba3cb47980455ee9d6b4123dce61aef2fa2.tar.bz2 | |
RISC-V: Support RISC-V Profiles 23.
This patch introduces support for RISC-V Profiles RV23A and RV23B [1],
enabling developers to utilize these profiles through the -march option.
[1] https://github.com/riscv/riscv-profiles/releases/tag/rva23-rvb23-ratified
Version log:
Update the testcases, using lowercase letter.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New profile.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-53.c: New test.
* gcc.target/riscv/arch-54.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/common/config/riscv/riscv-common.cc | 16 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/arch-53.c | 11 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/arch-54.c | 10 |
3 files changed, 37 insertions, 0 deletions
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 0fa2e21..e06cd5f 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -527,6 +527,22 @@ static const riscv_profiles riscv_profiles_table[] = "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" "_zicboz_zfhmin_zkt"}, + /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension + 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory + extensions. */ + {"rva23u64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb" + "_zfa_zawrs"}, + + /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension + 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory + extensions. */ + {"rvb23u64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb" + "_zfa_zawrs"}, + /* Currently we do not define S/M mode Profiles in gcc part. */ /* Terminate the list. */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-53.c b/gcc/testsuite/gcc.target/riscv/arch-53.c new file mode 100644 index 0000000..8210978 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-53.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rva23u64 -mabi=lp64d" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" +"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0" +_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0" +_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0" +_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0" +_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-54.c b/gcc/testsuite/gcc.target/riscv/arch-54.c new file mode 100644 index 0000000..6d242df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-54.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rvb23u64 -mabi=lp64d" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" +"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0" +"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0" +"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0" +"_zbb1p0_zbs1p0_zkt1p0\"" } } */ |