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| author | Alexey Merzlyakov <alexey.merzlyakov@samsung.com> | 2025-07-02 11:29:00 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2025-07-02 11:29:00 -0600 |
| commit | 9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3 (patch) | |
| tree | 37bf3614bef72123654558ce4e6875ef89d2b8eb /gcc/vmsdbg.h | |
| parent | 6596f5ab7465336d8466f2310cb612ae1bfbc7f3 (diff) | |
| download | gcc-9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3.zip gcc-9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3.tar.gz gcc-9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3.tar.bz2 | |
[PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]
It corrects the shift type of interleaved stepped patterns for const vector
expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems
still should be the same type for both LRA and other cases.
PR target/120356
gcc/ChangeLog:
* config/riscv/riscv-v.cc
(expand_const_vector_interleaved_stepped_npatterns):
Fix ASHIFT to LSHIFTRT insn.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr120356.c: New test.
Diffstat (limited to 'gcc/vmsdbg.h')
0 files changed, 0 insertions, 0 deletions