[RISC-V] Improve initial RTL generation for SImode adds on rv64

So this is the next chunk of Shreya's work to adjust our add expanders. In this
patch we're adding support for adding a 2*s12 immediate in SI for rv64.

To recap, the basic idea is reduce our reliance on the define_insn_and_split
that was added a year or so ago by synthesizing the more efficient sequence at
expansion time.  By handling this early rather than late the synthesized
sequence participates in the various optimizer passes in the natural way.  In
contrast using the define_insn_and_split bypasses the cost modeling in combine
and hides the synthesis until after reload as completed (which in turn leads to
the problems seen in pr120811).

This doesn't solve pr120811, but it is the last prerequisite patch before
directly tackling pr120811.

This has been bootstrapped & regression tested on the pioneer & bpi and been
through the usual testing on riscv32-elf and riscv64-elf.  Waiting on
pre-commit CI before moving forward.

gcc/
	* config/riscv/riscv-protos.h (synthesize_add_extended): Prototype.
	* config/riscv/riscv.cc (synthesize_add_extended): New function.
	* config/riscv/riscv.md (addsi3): For RV64, try synthesize_add_extended.

gcc/testsuite/
	* gcc.target/riscv/add-synthesis-2.c: New test.

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