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| author | Jin Ma <jinma@linux.alibaba.com> | 2025-04-07 14:21:50 +0800 |
|---|---|---|
| committer | Jin Ma <jinma@linux.alibaba.com> | 2025-04-08 10:13:52 +0800 |
| commit | 196b45caca0aae57a95bffcdd5c188994317de08 (patch) | |
| tree | 2f73cc18b68cb67e00f60e40593095cefa3b4b5d /gcc/rust/backend/rust-compile-expr.cc | |
| parent | 0980a6ff7ae318e4310be717327ee08b5ed914d0 (diff) | |
| download | gcc-196b45caca0aae57a95bffcdd5c188994317de08.zip gcc-196b45caca0aae57a95bffcdd5c188994317de08.tar.gz gcc-196b45caca0aae57a95bffcdd5c188994317de08.tar.bz2 | |
RISC-V: Disable unsupported vsext/vzext patterns for XTheadVector.
XThreadVector does not support the vsext/vzext instructions; however,
due to the reuse of RVV optimizations, it may generate these instructions
in certain cases. To prevent the error "Unknown opcode 'th.vsext.vf2',"
we should disable these patterns.
V2:
Change the value of dg-do in the test case from assemble to compile, and
remove the -save-temps option.
gcc/ChangeLog:
* config/riscv/vector.md: Disable vsext/vzext for XTheadVector.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xtheadvector/vsext.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vzext.c: New test.
Diffstat (limited to 'gcc/rust/backend/rust-compile-expr.cc')
0 files changed, 0 insertions, 0 deletions