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authorGeorg-Johann Lay <avr@gjlay.de>2025-08-01 15:42:53 +0200
committerGeorg-Johann Lay <avr@gjlay.de>2025-08-03 10:47:57 +0200
commit835595d43eb8fe19b6cf5a5f381d3dc458350c95 (patch)
treef06a6f32b6cb9f01550cd3067a9874523a9d9270 /gcc/config
parentd0e62f3783f34c6591628ca771f46fd30d8b4b7b (diff)
downloadgcc-master.zip
gcc-master.tar.gz
gcc-master.tar.bz2
AVR: Use avr_add_ccclobber / DONE_ADD_CCC in md instead of repeats.HEADtrunkmaster
There are many post-reload define_insn_and_split's that just append a (clobber (reg:CC REG_CC)) to the pattern. Instead of repeating the original patterns, avr_add_ccclobber (curr_insn) is used to do that job. This avoids repeating patterns all over the place, and splits that do something different (like using a canonical form) stand out clearly. gcc/ * config/avr/avr.md (define_insn_and_split) [reload_completed]: For splits that just append a (clobber (reg:CC REG_CC)) to the pattern, use avr_add_ccclobber (curr_insn) instead of repeating the original pattern. * config/avr/avr-dimode.md: Same. * config/avr/avr-fixed.md: Same.
Diffstat (limited to 'gcc/config')
-rw-r--r--gcc/config/avr/avr-dimode.md87
-rw-r--r--gcc/config/avr/avr-fixed.md129
-rw-r--r--gcc/config/avr/avr.md1181
3 files changed, 436 insertions, 961 deletions
diff --git a/gcc/config/avr/avr-dimode.md b/gcc/config/avr/avr-dimode.md
index 903bfbf..66ba5a9 100644
--- a/gcc/config/avr/avr-dimode.md
+++ b/gcc/config/avr/avr-dimode.md
@@ -101,10 +101,8 @@
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8 ACC_A)
- (plus:ALL8 (reg:ALL8 ACC_A)
- (reg:ALL8 ACC_B)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*add<mode>3_insn"
[(set (reg:ALL8 ACC_A)
@@ -122,10 +120,8 @@
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:DI ACC_A)
- (plus:DI (reg:DI ACC_A)
- (sign_extend:DI (reg:QI REG_X))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*adddi3_const8_insn"
[(set (reg:DI ACC_A)
@@ -146,12 +142,10 @@
(match_operand:ALL8 0 "const_operand" "n Ynn")))]
"avr_have_dimode
&& !s8_operand (operands[0], VOIDmode)"
- "#"
- "&& reload_completed"
- [(parallel [(set (reg:ALL8 ACC_A)
- (plus:ALL8 (reg:ALL8 ACC_A)
- (match_dup 0)))
- (clobber (reg:CC REG_CC))])])
+ "#"
+ "&& reload_completed"
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*add<mode>3_const_insn"
[(set (reg:ALL8 ACC_A)
@@ -211,10 +205,8 @@
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8 ACC_A)
- (minus:ALL8 (reg:ALL8 ACC_A)
- (reg:ALL8 ACC_B)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sub<mode>3_insn"
[(set (reg:ALL8 ACC_A)
@@ -236,10 +228,8 @@
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8 ACC_A)
- (minus:ALL8 (reg:ALL8 ACC_A)
- (match_dup 0)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sub<mode>3_const_insn"
[(set (reg:ALL8 ACC_A)
@@ -288,10 +278,8 @@
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8S ACC_A)
- (ss_addsub:ALL8S (reg:ALL8S ACC_A)
- (reg:ALL8S ACC_B)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3_insn"
[(set (reg:ALL8S ACC_A)
@@ -309,10 +297,8 @@
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8S ACC_A)
- (ss_addsub:ALL8S (reg:ALL8S ACC_A)
- (match_dup 0)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3_const_insn"
[(set (reg:ALL8S ACC_A)
@@ -361,10 +347,8 @@
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8U ACC_A)
- (us_addsub:ALL8U (reg:ALL8U ACC_A)
- (reg:ALL8U ACC_B)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3_insn"
[(set (reg:ALL8U ACC_A)
@@ -382,10 +366,8 @@
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8U ACC_A)
- (us_addsub:ALL8U (reg:ALL8U ACC_A)
- (match_operand:ALL8U 0 "const_operand" "n Ynn")))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3_const_insn"
[(set (reg:ALL8U ACC_A)
@@ -421,9 +403,8 @@
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:DI ACC_A)
- (neg:DI (reg:DI ACC_A)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*negdi2_insn"
[(set (reg:DI ACC_A)
@@ -500,7 +481,7 @@
"avr_have_dimode"
"#"
"&& reload_completed"
- [(const_int 0)]
+ [(scratch)]
{
emit_insn (gen_compare_<mode>2 ());
emit_jump_insn (gen_conditional_jump (operands[0], operands[1]));
@@ -529,7 +510,7 @@
"avr_have_dimode"
"#"
"&& reload_completed"
- [(const_int 0)]
+ [(scratch)]
{
emit_insn (gen_compare_const8_di2 ());
emit_jump_insn (gen_conditional_jump (operands[0], operands[1]));
@@ -556,7 +537,7 @@
&& !s8_operand (operands[1], VOIDmode)"
"#"
"&& reload_completed"
- [(const_int 0)]
+ [(scratch)]
{
emit_insn (gen_compare_const_<mode>2 (operands[1], operands[3]));
emit_jump_insn (gen_conditional_jump (operands[0], operands[2]));
@@ -629,10 +610,8 @@
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8 ACC_A)
- (di_shifts:ALL8 (reg:ALL8 ACC_A)
- (reg:QI 16)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3_insn"
[(set (reg:ALL8 ACC_A)
@@ -674,14 +653,10 @@
(clobber (reg:HI REG_Z))]
"avr_have_dimode
&& AVR_HAVE_MUL"
- "#"
- "&& reload_completed"
- [(parallel [(set (reg:DI ACC_A)
- (mult:DI (any_extend:DI (reg:SI 18))
- (any_extend:DI (reg:SI 22))))
- (clobber (reg:HI REG_X))
- (clobber (reg:HI REG_Z))
- (clobber (reg:CC REG_CC))])])
+ "#"
+ "&& reload_completed"
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<extend_u>mulsidi3_insn"
[(set (reg:DI ACC_A)
diff --git a/gcc/config/avr/avr-fixed.md b/gcc/config/avr/avr-fixed.md
index ce46beb..22061fc 100644
--- a/gcc/config/avr/avr-fixed.md
+++ b/gcc/config/avr/avr-fixed.md
@@ -62,10 +62,8 @@
"<FIXED_B:MODE>mode != <FIXED_A:MODE>mode"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (fract_convert:FIXED_A
- (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fract<FIXED_B:mode><FIXED_A:mode>2"
[(set (match_operand:FIXED_A 0 "register_operand" "=r")
@@ -86,10 +84,8 @@
"<FIXED_B:MODE>mode != <FIXED_A:MODE>mode"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (unsigned_fract_convert:FIXED_A
- (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fractuns<FIXED_B:mode><FIXED_A:mode>2"
[(set (match_operand:FIXED_A 0 "register_operand" "=r")
@@ -124,10 +120,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ss_addsub:ALL124S (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3"
[(set (match_operand:ALL124S 0 "register_operand" "=??d,d")
@@ -149,10 +143,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (us_addsub:ALL124U (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3"
[(set (match_operand:ALL124U 0 "register_operand" "=??r,d")
@@ -189,9 +181,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ss_neg:QQ (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ssnegqq2"
[(set (match_operand:QQ 0 "register_operand" "=r")
@@ -207,9 +198,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ss_abs:QQ (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ssabsqq2"
[(set (match_operand:QQ 0 "register_operand" "=r")
@@ -241,9 +231,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL2S 24)
- (ss_abs_neg:ALL2S (reg:ALL2S 24)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>2"
[(set (reg:ALL2S 24)
@@ -261,9 +250,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL4S 22)
- (ss_abs_neg:ALL4S (reg:ALL4S 22)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>2"
[(set (reg:ALL4S 22)
@@ -296,10 +284,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:QQ (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulqq3_enh"
[(set (match_operand:QQ 0 "register_operand" "=r")
@@ -317,10 +303,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:UQQ (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*muluqq3_enh"
[(set (match_operand:UQQ 0 "register_operand" "=r")
@@ -377,12 +361,8 @@
"!AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:QQ 23)
- (mult:QQ (reg:QQ 24)
- (reg:QQ 25)))
- (clobber (reg:QI 22))
- (clobber (reg:HI 24))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulqq3.call"
[(set (reg:QQ 23)
@@ -425,11 +405,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL2QA 24)
- (mult:ALL2QA (reg:ALL2QA 18)
- (reg:ALL2QA 26)))
- (clobber (reg:HI 22))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mul<mode>3.call"
[(set (reg:ALL2QA 24)
@@ -468,10 +445,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL4A 24)
- (mult:ALL4A (reg:ALL4A 16)
- (reg:ALL4A 20)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mul<mode>3.call"
[(set (reg:ALL4A 24)
@@ -514,11 +489,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL1Q 24)
- (usdiv:ALL1Q (reg:ALL1Q 25)
- (reg:ALL1Q 22)))
- (clobber (reg:QI 25))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code><mode>3.call"
[(set (reg:ALL1Q 24)
@@ -560,12 +532,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL2QA 24)
- (usdiv:ALL2QA (reg:ALL2QA 26)
- (reg:ALL2QA 22)))
- (clobber (reg:HI 26))
- (clobber (reg:QI 21))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code><mode>3.call"
[(set (reg:ALL2QA 24)
@@ -608,12 +576,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL4A 22)
- (usdiv:ALL4A (reg:ALL4A 24)
- (reg:ALL4A 18)))
- (clobber (reg:HI 26))
- (clobber (reg:HI 30))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code><mode>3.call"
[(set (reg:ALL4A 22)
@@ -684,12 +648,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (unspec:ALL124QA [(match_dup 1)
- (match_dup 2)
- (const_int 0)]
- UNSPEC_ROUND))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*round<mode>3_const"
[(set (match_operand:ALL124QA 0 "register_operand" "=d")
@@ -714,11 +674,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL1Q 24)
- (unspec:ALL1Q [(reg:ALL1Q 22)
- (reg:QI 24)] UNSPEC_ROUND))
- (clobber (reg:ALL1Q 22))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*round<mode>3.libgcc"
[(set (reg:ALL1Q 24)
@@ -740,11 +697,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL2QA 24)
- (unspec:ALL2QA [(reg:ALL2QA 22)
- (reg:QI 24)] UNSPEC_ROUND))
- (clobber (reg:ALL2QA 22))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*round<mode>3.libgcc"
[(set (reg:ALL2QA 24)
@@ -766,11 +720,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL4QA 22)
- (unspec:ALL4QA [(reg:ALL4QA 18)
- (reg:QI 24)] UNSPEC_ROUND))
- (clobber (reg:ALL4QA 18))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*round<mode>3.libgcc"
[(set (reg:ALL4QA 22)
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index f8bbdc7..67e88c1 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -574,9 +574,8 @@
&& REG_Z == REGNO (XEXP (operands[0], 0))"
"#"
"&& reload_completed"
- [(parallel [(set (reg:MOVMODE 22)
- (match_dup 0))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*load_<mode>_libgcc"
[(set (reg:MOVMODE 22)
@@ -716,14 +715,8 @@
|| avr_load_libgcc_insn_p (insn, ADDR_SPACE_FLASHX, true)"
"#"
"&& reload_completed"
- [(parallel [(set (reg:MOVMODE REG_22)
- (match_dup 0))
- (clobber (reg:QI REG_21))
- (clobber (reg:HI REG_Z))
- (clobber (reg:CC REG_CC))])]
- {
- operands[0] = SET_SRC (single_set (curr_insn));
- })
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fxload_<mode>_libgcc"
[(set (reg:MOVMODE REG_22)
@@ -853,9 +846,8 @@
|| reg_or_0_operand (operands[1], <MODE>mode)"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (match_dup 1))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
;; "movqi_insn"
;; "movqq_insn" "movuqq_insn"
@@ -964,9 +956,8 @@
|| reg_or_0_operand (operands[1], <MODE>mode)"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (match_dup 1))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mov<mode>"
[(set (match_operand:ALL2 0 "nonimmediate_operand" "=r,r ,r,m ,d,*r,q,r")
@@ -1137,9 +1128,8 @@
|| const0_rtx == operands[1]"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (match_dup 1))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*movpsi"
[(set (match_operand:PSI 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")
@@ -1197,9 +1187,8 @@
|| reg_or_0_operand (operands[1], <MODE>mode)"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (match_dup 1))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mov<mode>"
[(set (match_operand:ALL4 0 "nonimmediate_operand" "=r,r ,r ,Qm ,!d,r")
@@ -1245,9 +1234,8 @@
|| reg_or_0_operand (operands[1], SFmode)"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (match_dup 1))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*movsf"
[(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")
@@ -1326,16 +1314,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (mem:BLK (reg:HI REG_X))
- (mem:BLK (reg:HI REG_Z)))
- (unspec [(match_dup 0)]
- UNSPEC_CPYMEM)
- (use (match_dup 1))
- (clobber (reg:HI REG_X))
- (clobber (reg:HI REG_Z))
- (clobber (reg:QI LPM_REGNO))
- (clobber (match_dup 2))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*cpymem_<mode>"
[(set (mem:BLK (reg:HI REG_X))
@@ -1382,22 +1362,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (mem:BLK (reg:HI REG_X))
- (match_dup 2))
- (unspec [(match_dup 0)]
- UNSPEC_CPYMEM)
- (use (reg:QIHI 24))
- (clobber (reg:HI REG_X))
- (clobber (reg:HI REG_Z))
- (clobber (reg:QI LPM_REGNO))
- (clobber (reg:HI 24))
- (clobber (reg:QI 23))
- (clobber (mem:QI (match_dup 1)))
- (clobber (reg:CC REG_CC))])]
- {
- rtx xset = XVECEXP (PATTERN (curr_insn), 0, 0);
- operands[2] = SET_SRC (xset);
- })
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*cpymemx_<mode>"
[(set (mem:BLK (reg:HI REG_X))
@@ -1461,13 +1427,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (mem:BLK (match_dup 0))
- (const_int 0))
- (use (match_dup 1))
- (use (match_dup 2))
- (clobber (match_dup 3))
- (clobber (match_dup 4))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*clrmemqi"
[(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
@@ -1492,14 +1453,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (mem:BLK (match_dup 0))
- (const_int 0))
- (use (match_dup 1))
- (use (match_dup 2))
- (clobber (match_dup 3))
- (clobber (match_dup 4))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "adiw,*")])
@@ -1550,13 +1505,8 @@
""
"#"
"&& reload_completed"
- [(parallel
- [(set (match_dup 0)
- (unspec:HI [(mem:BLK (match_dup 1))
- (const_int 0)
- (match_dup 2)]
- UNSPEC_STRLEN))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*strlenhi"
[(set (match_operand:HI 0 "register_operand" "=e")
@@ -1581,10 +1531,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:ALL1 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*add<mode>3"
[(set (match_operand:ALL1 0 "register_operand" "=r,d ,r ,r ,r ,r")
@@ -1640,10 +1588,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HI (zero_extend:HI (match_dup 1))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*addhi3_zero_extend"
[(set (match_operand:HI 0 "register_operand" "=r,*?r")
@@ -1663,10 +1609,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HI (match_dup 1)
- (zero_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*addhi3_zero_extend1"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -1684,10 +1628,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HI (zero_extend:HI (match_dup 1))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*addhi3_zero_extend.const"
[(set (match_operand:HI 0 "register_operand" "=d")
@@ -1723,11 +1665,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HI (ashift:HI (zero_extend:HI (match_dup 1))
- (const_int 1))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*addhi3_zero_extend.ashift1"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -1752,11 +1691,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HI (zero_extend:HI (match_dup 1))
- (zero_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
-
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*usum_widenqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -1774,10 +1710,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:HI (zero_extend:HI (match_dup 1))
- (zero_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*udiff_widenqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -1797,7 +1731,7 @@
return avr_out_addto_sp (operands, NULL);
}
""
- [(const_int 0)]
+ [(scratch)]
{
// Do not attempt to split this pattern. This FAIL is necessary
// to prevent the splitter from matching *add<ALL2>3_split, splitting
@@ -1909,11 +1843,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:ALL2 (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
;; "*addhi3_clobber"
;; "*addhq3_clobber" "*adduhq3_clobber"
@@ -1943,11 +1874,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:ALL4 (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*add<mode>3"
[(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
@@ -1979,10 +1907,8 @@
&& (<HISI:SIZE> > 2 || <CODE> == SIGN_EXTEND)"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HISI (any_extend:HISI (match_dup 1))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
;; "*addhi3.sign_extend.qi"
;; "*addpsi3.zero_extend.qi" "*addpsi3.sign_extend.qi"
@@ -2019,10 +1945,8 @@
"<HISI:SIZE> > <QIPSI:SIZE>"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:HISI (match_dup 1)
- (any_extend:HISI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
;; "*subhi3.zero_extend.qi" "*subhi3.sign_extend.qi"
;; "*subpsi3.zero_extend.qi" "*subpsi3.sign_extend.qi"
@@ -2053,11 +1977,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3 ))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*addpsi3"
[(set (match_operand:PSI 0 "register_operand" "=??r,d ,d,r")
@@ -2079,10 +2000,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*subpsi3"
[(set (match_operand:PSI 0 "register_operand" "=r")
@@ -2106,10 +2025,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:ALL1 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sub<mode>3"
[(set (match_operand:ALL1 0 "register_operand" "=??r,d ,r ,r ,r ,r")
@@ -2137,11 +2054,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:ALL2 (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sub<mode>3"
[(set (match_operand:ALL2 0 "register_operand" "=??r,d ,*r")
@@ -2167,11 +2081,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:ALL4 (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sub<mode>3"
[(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
@@ -2209,10 +2120,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:QI (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulqi3_enh"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -2243,10 +2152,8 @@
"!AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:QI 24)
- (mult:QI (reg:QI 24) (reg:QI 22)))
- (clobber (reg:QI 22))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulqi3_call"
[(set (reg:QI 24)
@@ -2269,12 +2176,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (truncate:QI
- (lshiftrt:HI (mult:HI (any_extend:HI (match_dup 1))
- (any_extend:HI (match_dup 2)))
- (const_int 8))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<extend_su>mulqi3_highpart"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -2361,21 +2264,21 @@
(const_int 0))))
(clobber (reg:CC REG_CC))])])
-;; *subqi3.lt0 *subqi3.ge0
-;; *subhi3.lt0 *subhi3.ge0
-;; *subpsi3.lt0 *subpsi3.ge0
-;; *subsi3.lt0 *subsi3.ge0
-(define_insn "*sub<QISI:mode>3.<code>0"
- [(set (match_operand:QISI 0 "register_operand" "=r")
- (minus:QISI (match_operand:QISI 1 "register_operand" "0")
- (gelt:QISI (match_operand:QISI2 2 "register_operand" "r")
- (const_int 0))))
- (clobber (reg:CC REG_CC))]
- "reload_completed"
- {
- return avr_out_add_msb (insn, operands, <CODE>, nullptr);
- }
- [(set_attr "adjust_len" "add_<code>0")])
+;; *addqi3.lt0_split *addqi3.ge0_split
+;; *addhi3.lt0_split *addhi3.ge0_split
+;; *addpsi3.lt0_split *addpsi3.ge0_split
+;; *addsi3.lt0_split *addsi3.ge0_split
+(define_insn_and_split "*add<QISI:mode>3.<code>0_split"
+ [(set (match_operand:QISI 0 "register_operand" "=r")
+ (plus:QISI (gelt:QISI (match_operand:QISI2 1 "register_operand" "r")
+ (const_int 0))
+ (match_operand:QISI 2 "register_operand" "0")))]
+ ""
+ "#"
+ "&& reload_completed"
+ ; *add<QISI:mode>3.<code>0
+ [(scratch)]
+ { DONE_ADD_CCC })
;; *addqi3.lt0 *addqi3.ge0
;; *addhi3.lt0 *addhi3.ge0
@@ -2393,25 +2296,6 @@
}
[(set_attr "adjust_len" "add_<code>0")])
-;; *addqi3.lt0_split *addqi3.ge0_split
-;; *addhi3.lt0_split *addhi3.ge0_split
-;; *addpsi3.lt0_split *addpsi3.ge0_split
-;; *addsi3.lt0_split *addsi3.ge0_split
-(define_insn_and_split "*add<QISI:mode>3.<code>0_split"
- [(set (match_operand:QISI 0 "register_operand" "=r")
- (plus:QISI (gelt:QISI (match_operand:QISI2 1 "register_operand" "r")
- (const_int 0))
- (match_operand:QISI 2 "register_operand" "0")))]
- ""
- "#"
- "&& reload_completed"
- [; *add<QISI:mode>3.<code>0
- (parallel [(set (match_dup 0)
- (plus:QISI (gelt:QISI (match_dup 1)
- (const_int 0))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
-
;; *subqi3.lt0_split *subqi3.ge0_split
;; *subhi3.lt0_split *subhi3.ge0_split
;; *subpsi3.lt0_split *subpsi3.ge0_split
@@ -2424,13 +2308,25 @@
""
"#"
"&& reload_completed"
- [; *sub<QISI:mode>3.<code>0
- (parallel [(set (match_dup 0)
- (minus:QISI (match_dup 1)
- (gelt:QISI (match_dup 2)
- (const_int 0))))
- (clobber (reg:CC REG_CC))])])
+ ; *sub<QISI:mode>3.<code>0
+ [(scratch)]
+ { DONE_ADD_CCC })
+;; *subqi3.lt0 *subqi3.ge0
+;; *subhi3.lt0 *subhi3.ge0
+;; *subpsi3.lt0 *subpsi3.ge0
+;; *subsi3.lt0 *subsi3.ge0
+(define_insn "*sub<QISI:mode>3.<code>0"
+ [(set (match_operand:QISI 0 "register_operand" "=r")
+ (minus:QISI (match_operand:QISI 1 "register_operand" "0")
+ (gelt:QISI (match_operand:QISI2 2 "register_operand" "r")
+ (const_int 0))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
+ {
+ return avr_out_add_msb (insn, operands, <CODE>, nullptr);
+ }
+ [(set_attr "adjust_len" "add_<code>0")])
(define_insn_and_split "*umulqihi3.call_split"
[(set (reg:HI 24)
@@ -2441,12 +2337,8 @@
"!AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (mult:HI (zero_extend:HI (reg:QI 22))
- (zero_extend:HI (reg:QI 24))))
- (clobber (reg:QI 21))
- (clobber (reg:HI 22))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*umulqihi3.call"
[(set (reg:HI 24)
@@ -2469,10 +2361,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (any_extend:HI (match_dup 1))
- (any_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "<extend_u>mulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -2492,10 +2382,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (zero_extend:HI (match_dup 1))
- (sign_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*usmulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -2517,10 +2405,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (sign_extend:HI (match_dup 1))
- (zero_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sumulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -2542,10 +2428,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (not:HI (zero_extend:HI (not:QI (match_dup 1))))
- (sign_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*osmulqihi3"
[(set (match_operand:HI 0 "register_operand" "=&r")
@@ -2566,10 +2450,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (not:HI (zero_extend:HI (not:QI (match_dup 1))))
- (zero_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*oumulqihi3"
[(set (match_operand:HI 0 "register_operand" "=&r")
@@ -2596,11 +2478,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:QI (mult:QI (match_dup 1)
- (match_dup 2))
- (match_dup 3)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*maddqi4"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -2622,11 +2501,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:QI (match_dup 3)
- (mult:QI (match_dup 1)
- (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*msubqi4"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -2705,11 +2581,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HI (mult:HI (any_extend:HI (match_dup 1))
- (any_extend:HI (match_dup 2)))
- (match_dup 3)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<extend_u>maddqihi4"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -2734,11 +2607,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:HI (match_dup 3)
- (mult:HI (any_extend:HI (match_dup 1))
- (any_extend:HI (match_dup 2)))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<extend_u>msubqihi4"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -2765,11 +2635,8 @@
&& <any_extend:CODE> != <any_extend2:CODE>"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HI (mult:HI (any_extend:HI (match_dup 1))
- (any_extend2:HI (match_dup 2)))
- (match_dup 3)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -2800,11 +2667,8 @@
&& <any_extend:CODE> != <any_extend2:CODE>"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:HI (match_dup 3)
- (mult:HI (any_extend:HI (match_dup 1))
- (any_extend2:HI (match_dup 2)))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -3072,10 +2936,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashift:HI (sign_extend:HI (match_dup 1))
- (const_int 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ashiftqihi2.signx.1"
[(set (match_operand:HI 0 "register_operand" "=r,*r")
@@ -3153,10 +3015,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (sign_extend:HI (match_dup 1))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulsqihi3"
[(set (match_operand:HI 0 "register_operand" "=&r")
@@ -3178,10 +3038,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (zero_extend:HI (match_dup 1))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*muluqihi3"
[(set (match_operand:HI 0 "register_operand" "=&r")
@@ -3205,10 +3063,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (not:HI (zero_extend:HI (not:QI (match_dup 1))))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*muloqihi3"
[(set (match_operand:HI 0 "register_operand" "=&r")
@@ -3277,10 +3133,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulhi3_enh"
[(set (match_operand:HI 0 "register_operand" "=&r")
@@ -3319,11 +3173,8 @@
"!AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (mult:HI (reg:HI 24) (reg:HI 22)))
- (clobber (reg:HI 22))
- (clobber (reg:QI 21))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulhi3_call"
[(set (reg:HI 24)
@@ -3719,11 +3570,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 22)
- (mult:SI (reg:SI 22)
- (reg:SI 18)))
- (clobber (reg:HI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn_and_split "*mulsi3_call_pr118012_split"
[(set (reg:SI 22)
@@ -3737,13 +3585,8 @@
&& ! AVR_TINY"
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 22)
- (mult:SI (reg:SI 22)
- (reg:SI 18)))
- (clobber (reg:SI 18))
- (clobber (reg:HI 26))
- (clobber (reg:HI 30))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulsi3_call"
[(set (reg:SI 22)
@@ -3779,10 +3622,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 22)
- (mult:SI (any_extend:SI (reg:HI 18))
- (any_extend:SI (reg:HI 26))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<extend_u>mulhisi3_call"
[(set (reg:SI 22)
@@ -3804,12 +3645,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (truncate:HI (lshiftrt:SI (mult:SI (any_extend:SI (reg:HI 18))
- (any_extend:SI (reg:HI 26)))
- (const_int 16))))
- (clobber (reg:HI 22))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<extend_su>mulhi3_highpart_call"
[(set (reg:HI 24)
@@ -3829,10 +3666,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 22)
- (mult:SI (zero_extend:SI (reg:HI 18))
- (sign_extend:SI (reg:HI 26))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*usmulhisi3_call"
[(set (reg:SI 22)
@@ -3850,10 +3685,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 22)
- (mult:SI (any_extend:SI (reg:HI 26))
- (reg:SI 18)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mul<extend_su>hisi3_call"
[(set (reg:SI 22)
@@ -3871,10 +3704,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 22)
- (mult:SI (not:SI (zero_extend:SI (not:HI (reg:HI 26))))
- (reg:SI 18)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulohisi3_call"
[(set (reg:SI 22)
@@ -3925,11 +3756,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
- (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
- (clobber (reg:QI 22))
- (clobber (reg:QI 23))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*divmodqi4_call"
[(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
@@ -3969,10 +3797,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
- (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
- (clobber (reg:QI 23))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*udivmodqi4_call"
[(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
@@ -4013,11 +3839,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
- (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
- (clobber (reg:HI 26))
- (clobber (reg:QI 21))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*divmodhi4_call"
[(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
@@ -4059,11 +3882,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
- (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
- (clobber (reg:HI 26))
- (clobber (reg:QI 21))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*udivmodhi4_call"
[(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
@@ -4112,10 +3932,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:PSI (zero_extend:PSI (match_dup 1))
- (zero_extend:PSI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*umulqihipsi3"
[(set (match_operand:PSI 0 "register_operand" "=&r")
@@ -4134,31 +3952,17 @@
(define_insn_and_split "*umulhiqipsi3_split"
[(set (match_operand:PSI 0 "register_operand" "=&r")
- (mult:PSI (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))
- (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))))]
+ (mult:PSI (zero_extend:PSI (match_operand:HI 1 "register_operand" "r"))
+ (zero_extend:PSI (match_operand:QI 2 "register_operand" "r"))))]
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
+ ; "*umulqihipsi3"
[(parallel [(set (match_dup 0)
(mult:PSI (zero_extend:PSI (match_dup 2))
(zero_extend:PSI (match_dup 1))))
(clobber (reg:CC REG_CC))])])
-(define_insn "*umulhiqipsi3"
- [(set (match_operand:PSI 0 "register_operand" "=&r")
- (mult:PSI (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))
- (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))))
- (clobber (reg:CC REG_CC))]
- "AVR_HAVE_MUL && reload_completed"
- "mul %1,%A2
- movw %A0,r0
- mul %1,%B2
- add %B0,r0
- mov %C0,r1
- clr __zero_reg__
- adc %C0,__zero_reg__"
- [(set_attr "length" "7")])
-
(define_expand "mulsqipsi3"
[(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "")
(mult:PSI (sign_extend:PSI (match_operand:QI 1 "pseudo_register_operand" ""))
@@ -4229,10 +4033,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:PSI 18)
- (mult:PSI (sign_extend:PSI (reg:QI 25))
- (reg:PSI 22)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulsqipsi3.libgcc"
[(set (reg:PSI 18)
@@ -4253,13 +4055,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:PSI 22)
- (mult:PSI (reg:PSI 22)
- (reg:PSI 18)))
- (clobber (reg:QI 21))
- (clobber (reg:QI 25))
- (clobber (reg:HI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulpsi3.libgcc"
[(set (reg:PSI 22)
@@ -4311,12 +4108,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:PSI 22) (div:PSI (reg:PSI 22) (reg:PSI 18)))
- (set (reg:PSI 18) (mod:PSI (reg:PSI 22) (reg:PSI 18)))
- (clobber (reg:QI 21))
- (clobber (reg:QI 25))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*divmodpsi4_call"
[(set (reg:PSI 22) (div:PSI (reg:PSI 22) (reg:PSI 18)))
@@ -4360,12 +4153,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:PSI 22) (udiv:PSI (reg:PSI 22) (reg:PSI 18)))
- (set (reg:PSI 18) (umod:PSI (reg:PSI 22) (reg:PSI 18)))
- (clobber (reg:QI 21))
- (clobber (reg:QI 25))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*udivmodpsi4_call"
[(set (reg:PSI 22) (udiv:PSI (reg:PSI 22) (reg:PSI 18)))
@@ -4411,11 +4200,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
- (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
- (clobber (reg:HI 26))
- (clobber (reg:HI 30))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*divmodsi4_call"
[(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
@@ -4458,11 +4244,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
- (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
- (clobber (reg:HI 26))
- (clobber (reg:HI 30))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*udivmodsi4_call"
[(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
@@ -4484,10 +4267,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (and:QI (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*andqi3"
[(set (match_operand:QI 0 "register_operand" "=??r,d,*l ,r")
@@ -4511,11 +4292,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (and:HI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*andhi3"
[(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r ,r")
@@ -4545,11 +4323,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (and:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*andpsi3"
[(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r ,r")
@@ -4580,11 +4355,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (and:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*andsi3"
[(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r ,r")
@@ -4634,10 +4406,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ior:QI (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*iorqi3"
[(set (match_operand:QI 0 "register_operand" "=??r,d,*l")
@@ -4659,11 +4429,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ior:HI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*iorhi3"
[(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r")
@@ -4691,11 +4458,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ior:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*iorpsi3"
[(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r")
@@ -4723,11 +4487,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ior:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*iorsi3"
[(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r")
@@ -4758,10 +4519,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (xor:QI (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*xorqi3"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -4780,11 +4539,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (xor:HI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*xorhi3"
[(set (match_operand:HI 0 "register_operand" "=??r,r ,d ,r")
@@ -4810,11 +4566,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (xor:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*xorpsi3"
[(set (match_operand:PSI 0 "register_operand" "=??r,r ,d ,r")
@@ -4842,11 +4595,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (xor:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*xorsi3"
[(set (match_operand:SI 0 "register_operand" "=??r,r ,d ,r")
@@ -4918,7 +4668,7 @@
(clobber (reg:CC REG_CC))])]
"optimize
&& reload_completed"
- [(const_int 1)]
+ [(scratch)]
{
for (int i = 0; i < <SIZE>; i++)
{
@@ -5026,10 +4776,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (rotate:QI (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*rotlqi3"
[(set (match_operand:QI 0 "register_operand" "=r,r,r ,r ,r ,r ,r ,r")
@@ -5099,10 +4847,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (rotate:HI (match_dup 1)
- (const_int 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*rotlhi2.1"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -5120,10 +4866,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (rotate:HI (match_dup 1)
- (const_int 15)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*rotlhi2.15"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -5141,10 +4885,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (rotate:PSI (match_dup 1)
- (const_int 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*rotlpsi2.1"
[(set (match_operand:PSI 0 "register_operand" "=r")
@@ -5162,10 +4904,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (rotate:PSI (match_dup 1)
- (const_int 23)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*rotlpsi2.23"
[(set (match_operand:PSI 0 "register_operand" "=r")
@@ -5183,10 +4923,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (rotate:SI (match_dup 1)
- (const_int 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*rotlsi2.1"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -5204,10 +4942,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (rotate:SI (match_dup 1)
- (const_int 31)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*rotlsi2.31"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -5239,7 +4975,7 @@
&& 0 == INTVAL (operands[2]) % 16"
"#"
"&& reload_completed"
- [(const_int 0)]
+ [(scratch)]
{
avr_rotate_bytes (operands);
DONE;
@@ -5263,7 +4999,7 @@
&& 0 == INTVAL (operands[2]) % 16))"
"#"
"&& reload_completed"
- [(const_int 0)]
+ [(scratch)]
{
avr_rotate_bytes (operands);
DONE;
@@ -5363,10 +5099,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashift:ALL1 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ashl<mode>3"
[(set (match_operand:ALL1 0 "register_operand" "=r,r ,r ,r,r")
@@ -5390,11 +5124,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashift:ALL2 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*,*")])
;; "*ashlhi3"
@@ -5506,11 +5237,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashift:ALL4 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*,*")])
(define_insn "*ashl<mode>3"
@@ -5749,12 +5477,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashift:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*")])
(define_insn "*ashlpsi3"
@@ -5808,10 +5532,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashiftrt:ALL1 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ashr<mode>3"
[(set (match_operand:ALL1 0 "register_operand" "=r,r ,r ,r")
@@ -5835,11 +5557,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashiftrt:ALL2 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*,*")])
;; "*ashrhi3"
@@ -5866,12 +5585,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashiftrt:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*")])
(define_insn "*ashrpsi3"
@@ -5898,11 +5613,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashiftrt:ALL4 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*,*")])
(define_insn "*ashr<mode>3"
@@ -6013,10 +5725,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (lshiftrt:ALL1 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*lshr<mode>3"
[(set (match_operand:ALL1 0 "register_operand" "=r,r ,r ,r,r")
@@ -6039,11 +5749,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (lshiftrt:ALL2 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*,*")])
(define_insn "*lshr<mode>3"
@@ -6066,12 +5773,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (lshiftrt:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*")])
(define_insn "*lshrpsi3"
@@ -6098,11 +5801,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (lshiftrt:ALL4 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*,*")])
(define_insn "*lshr<mode>3"
@@ -6217,9 +5917,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (abs:QI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*absqi2"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -6237,9 +5936,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (abs:SF (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*abssf2"
[(set (match_operand:SF 0 "register_operand" "=d,r")
@@ -6260,9 +5958,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (neg:QI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*negqi2"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -6278,9 +5975,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (neg:HI (sign_extend:HI (match_dup 1))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*negqihi2"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -6296,9 +5992,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (neg:HI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*neghi2"
[(set (match_operand:HI 0 "register_operand" "=r,&r")
@@ -6316,9 +6011,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (neg:PSI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*negpsi2"
[(set (match_operand:PSI 0 "register_operand" "=!d,r,&r")
@@ -6337,10 +6031,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (neg:SI (match_dup 1)))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,mov,movw")])
(define_insn "*negsi2.libgcc"
@@ -6371,9 +6063,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (neg:SF (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*negsf2"
[(set (match_operand:SF 0 "register_operand" "=d,r")
@@ -6394,9 +6085,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (not:QI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*one_cmplqi2"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -6412,9 +6102,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (not:HI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*one_cmplhi2"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -6431,9 +6120,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (not:PSI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*one_cmplpsi2"
[(set (match_operand:PSI 0 "register_operand" "=r")
@@ -6449,9 +6137,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (not:SI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -6480,9 +6167,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (sign_extend:HI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*extendqihi2"
[(set (match_operand:HI 0 "register_operand" "=r,r")
@@ -6501,9 +6187,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (sign_extend:PSI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*extendqipsi2"
[(set (match_operand:PSI 0 "register_operand" "=r,r")
@@ -6522,9 +6207,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (sign_extend:SI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -6543,9 +6227,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (sign_extend:PSI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*extendhipsi2"
[(set (match_operand:PSI 0 "register_operand" "=r,r")
@@ -6564,9 +6247,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (sign_extend:SI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -6585,9 +6267,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (sign_extend:SI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*extendpsisi2"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -7032,10 +6713,11 @@
"#"
"reload_completed"
[(set (reg:CC REG_CC)
- (compare:CC (match_dup 1) (match_dup 2)))
+ (compare:CC (match_dup 1)
+ (match_dup 2)))
(set (pc)
- (if_then_else (match_op_dup 0
- [(reg:CC REG_CC) (const_int 0)])
+ (if_then_else (match_op_dup 0 [(reg:CC REG_CC)
+ (const_int 0)])
(label_ref (match_dup 3))
(pc)))])
@@ -7054,11 +6736,12 @@
"#"
"reload_completed"
[(parallel [(set (reg:CC REG_CC)
- (compare:CC (match_dup 1) (match_dup 2)))
+ (compare:CC (match_dup 1)
+ (match_dup 2)))
(clobber (match_dup 4))])
(set (pc)
- (if_then_else (match_op_dup 0
- [(reg:CC REG_CC) (const_int 0)])
+ (if_then_else (match_op_dup 0 [(reg:CC REG_CC)
+ (const_int 0)])
(label_ref (match_dup 3))
(pc)))]
{
@@ -7081,11 +6764,12 @@
"#"
"reload_completed"
[(parallel [(set (reg:CC REG_CC)
- (compare:CC (match_dup 1) (match_dup 2)))
+ (compare:CC (match_dup 1)
+ (match_dup 2)))
(clobber (match_dup 4))])
(set (pc)
- (if_then_else (match_op_dup 0
- [(reg:CC REG_CC) (const_int 0)])
+ (if_then_else (match_op_dup 0 [(reg:CC REG_CC)
+ (const_int 0)])
(label_ref (match_dup 3))
(pc)))]
{
@@ -7109,11 +6793,12 @@
"#"
"reload_completed"
[(parallel [(set (reg:CC REG_CC)
- (compare:CC (match_dup 1) (match_dup 2)))
+ (compare:CC (match_dup 1)
+ (match_dup 2)))
(clobber (match_dup 4))])
(set (pc)
- (if_then_else (match_op_dup 0
- [(reg:CC REG_CC) (const_int 0)])
+ (if_then_else (match_op_dup 0 [(reg:CC REG_CC)
+ (const_int 0)])
(label_ref (match_dup 3))
(pc)))]
{
@@ -7668,17 +7353,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (if_then_else
- (match_op_dup 0
- [(zero_extract:QIDI
- (match_dup 1)
- (const_int 1)
- (match_dup 2))
- (const_int 0)])
- (label_ref (match_dup 3))
- (pc)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sbrx_branch<mode>"
[(set (pc)
@@ -7721,13 +7397,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (if_then_else (match_op_dup 0 [(and:QISI (match_dup 1)
- (match_dup 2))
- (const_int 0)])
- (label_ref (match_dup 3))
- (pc)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sbrx_and_branch<mode>"
[(set (pc)
@@ -7968,14 +7639,8 @@
"!AVR_HAVE_EIJMP_EICALL"
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (unspec:HI [(match_dup 0)]
- UNSPEC_INDEX_JMP))
- (use (label_ref (match_dup 1)))
- (clobber (match_dup 2))
- (clobber (const_int 0))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "rjmp,rjmp,jmp")])
(define_insn "*tablejump"
@@ -8004,14 +7669,8 @@
"AVR_HAVE_EIJMP_EICALL"
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (unspec:HI [(reg:HI REG_Z)]
- UNSPEC_INDEX_JMP))
- (use (label_ref (match_dup 0)))
- (clobber (reg:HI REG_Z))
- (clobber (reg:QI 24))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "eijmp")])
@@ -8182,17 +7841,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (if_then_else
- (match_operator 0 "eqne_operator"
- [(zero_extract:QIHI
- (mem:QI (match_dup 1))
- (const_int 1)
- (match_dup 2))
- (const_int 0)])
- (label_ref (match_dup 3))
- (pc)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sbix_branch"
[(set (pc)
@@ -8230,14 +7880,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (if_then_else
- (match_operator 0 "gelt_operator"
- [(mem:QI (match_dup 1))
- (const_int 0)])
- (label_ref (match_dup 2))
- (pc)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sbix_branch_bit7"
[(set (pc)
@@ -8277,17 +7921,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (if_then_else
- (match_operator 0 "eqne_operator"
- [(zero_extract:QIHI
- (mem:QI (match_dup 1))
- (const_int 1)
- (match_dup 2))
- (const_int 0)])
- (label_ref (match_dup 3))
- (pc)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sbix_branch_tmp"
[(set (pc)
@@ -8324,14 +7959,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (if_then_else
- (match_operator 0 "gelt_operator"
- [(mem:QI (match_dup 1))
- (const_int 0)])
- (label_ref (match_dup 2))
- (pc)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sbix_branch_tmp_bit7"
[(set (pc)
@@ -8784,13 +8413,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(unspec_volatile [(match_dup 0)
- (const_int 1)]
- UNSPECV_DELAY_CYCLES)
- (set (match_dup 1)
- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
- (clobber (match_dup 2))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*delay_cycles_1"
[(unspec_volatile [(match_operand:QI 0 "const_int_operand" "n")
@@ -8816,14 +8440,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(unspec_volatile [(match_dup 0)
- (const_int 2)]
- UNSPECV_DELAY_CYCLES)
- (set (match_dup 1)
- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
- (clobber (match_dup 2))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "adiw,no_adiw")])
(define_insn "*delay_cycles_2"
@@ -8853,15 +8471,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(unspec_volatile [(match_dup 0)
- (const_int 3)]
- UNSPECV_DELAY_CYCLES)
- (set (match_dup 1)
- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
- (clobber (match_dup 2))
- (clobber (match_dup 3))
- (clobber (match_dup 4))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*delay_cycles_3"
[(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
@@ -8896,16 +8507,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(unspec_volatile [(match_dup 0)
- (const_int 4)]
- UNSPECV_DELAY_CYCLES)
- (set (match_dup 1)
- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
- (clobber (match_dup 2))
- (clobber (match_dup 3))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*delay_cycles_4"
[(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
@@ -8942,12 +8545,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (unspec:QI [(match_dup 1)
- (match_dup 2)
- (match_dup 3)]
- UNSPEC_INSERT_BITS))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*insert_bits"
[(set (match_operand:QI 0 "register_operand" "=r ,d ,r")
@@ -9127,12 +8726,13 @@
"#"
"reload_completed"
[(set (reg:CC REG_CC)
- (compare:CC (match_dup 0) (const_int 0)))
+ (compare:CC (match_dup 0)
+ (const_int 0)))
(set (pc)
- (if_then_else (ge (reg:CC REG_CC) (const_int 0))
+ (if_then_else (ge (reg:CC REG_CC)
+ (const_int 0))
(label_ref (match_dup 1))
- (pc)))]
- "")
+ (pc)))])
(define_expand "flash_segment"
[(parallel [(match_operand:QI 0 "register_operand" "")
@@ -9235,9 +8835,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (parity:HI (reg:HI 24)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*parityhi2.libgcc"
[(set (reg:HI 24)
@@ -9253,9 +8852,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (zero_extend:HI (parity:QI (reg:QI 24))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*parityqihi2.libgcc"
[(set (reg:HI 24)
@@ -9271,9 +8869,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (truncate:HI (parity:SI (reg:SI 22))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*paritysihi2.libgcc"
[(set (reg:HI 24)
@@ -9329,9 +8926,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (popcount:HI (reg:HI 24)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*popcounthi2.libgcc"
[(set (reg:HI 24)
@@ -9347,9 +8943,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (truncate:HI (popcount:SI (reg:SI 22))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*popcountsi2.libgcc"
[(set (reg:HI 24)
@@ -9365,9 +8960,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:QI 24)
- (popcount:QI (reg:QI 24)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*popcountqi2.libgcc"
[(set (reg:QI 24)
@@ -9421,10 +9015,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (clz:HI (reg:HI 24)))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*clzhi2.libgcc"
[(set (reg:HI 24)
@@ -9442,10 +9034,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (truncate:HI (clz:SI (reg:SI 22))))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*clzsihi2.libgcc"
[(set (reg:HI 24)
@@ -9490,10 +9080,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (ctz:HI (reg:HI 24)))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ctzhi2.libgcc"
[(set (reg:HI 24)
@@ -9512,11 +9100,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (truncate:HI (ctz:SI (reg:SI 22))))
- (clobber (reg:QI 22))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ctzsihi2.libgcc"
[(set (reg:HI 24)
@@ -9562,10 +9147,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (ffs:HI (reg:HI 24)))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ffshi2.libgcc"
[(set (reg:HI 24)
@@ -9584,11 +9167,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (truncate:HI (ffs:SI (reg:SI 22))))
- (clobber (reg:QI 22))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ffssihi2.libgcc"
[(set (reg:HI 24)
@@ -9633,9 +9213,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 22)
- (bswap:SI (reg:SI 22)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*bswapsi2.libgcc"
[(set (reg:SI 22)
@@ -9742,11 +9321,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (unspec:HI [(match_dup 1)
- (match_dup 2)]
- UNSPEC_FMUL))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fmul_insn"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -9768,11 +9344,8 @@
"!AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 22)
- (unspec:HI [(reg:QI 24)
- (reg:QI 25)] UNSPEC_FMUL))
- (clobber (reg:HI 24))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fmul.call"
[(set (reg:HI 22)
@@ -9814,11 +9387,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (unspec:HI [(match_dup 1)
- (match_dup 2)]
- UNSPEC_FMULS))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fmuls_insn"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -9840,11 +9410,8 @@
"!AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 22)
- (unspec:HI [(reg:QI 24)
- (reg:QI 25)] UNSPEC_FMULS))
- (clobber (reg:HI 24))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fmuls.call"
[(set (reg:HI 22)
@@ -9886,11 +9453,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (unspec:HI [(match_dup 1)
- (match_dup 2)]
- UNSPEC_FMULSU))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fmulsu_insn"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -9912,11 +9476,8 @@
"!AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 22)
- (unspec:HI [(reg:QI 24)
- (reg:QI 25)] UNSPEC_FMULSU))
- (clobber (reg:HI 24))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fmulsu.call"
[(set (reg:HI 22)
@@ -10037,11 +9598,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (zero_extract:QI (match_dup 0)
- (const_int 1)
- (match_dup 1))
- (match_dup 2))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*insv.reg"
[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r,d,d,l,l")
@@ -10478,11 +10036,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (zero_extract:QI (not:QI (match_dup 1))
- (const_int 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*extzv.not"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -10619,11 +10174,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (and:QISI (any_shift:QISI (match_dup 1)
- (match_dup 2))
- (match_dup 3)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*insv.any_shift.<mode>"
[(set (match_operand:QISI 0 "register_operand" "=r")
@@ -10686,11 +10238,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (sign_extract:QISI (match_dup 1)
- (const_int 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sextr.<QISI:mode>.<QISI2:mode>"
[(set (match_operand:QISI 0 "register_operand" "=r")
generated by cgit v1.1 at 2025-08-03 12:36:53 +0000