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| author | Jiawei <jiawei@iscas.ac.cn> | 2025-05-13 15:23:39 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2025-05-14 23:27:59 +0800 |
| commit | 0cbace3b142c087335e245245e97f6605a6cd1f7 (patch) | |
| tree | 95c70dcc4bba114006cd25feebfb681addf89884 /gcc/common | |
| parent | eedaf969f4d24dad368de63ea40b1e694fd57c40 (diff) | |
| download | gcc-0cbace3b142c087335e245245e97f6605a6cd1f7.zip gcc-0cbace3b142c087335e245245e97f6605a6cd1f7.tar.gz gcc-0cbace3b142c087335e245245e97f6605a6cd1f7.tar.bz2 | |
RISC-V: Add augmented hypervisor series extensions.
The augmented hypervisor series extensions 'sha'[1] is a new profile-defined
extension series that captures the full set of features that are mandated to
be supported along with the 'H' extension.
[1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23s64-profile
Version log: Update implements， fix testcase format.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension defs.
* config/riscv/riscv-ext.opt: Ditto.
* doc/riscv-ext.texi: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-55.c: New test.
Diffstat (limited to 'gcc/common')
0 files changed, 0 insertions, 0 deletions