RISC-V: Add pattern for vector-scalar single-width floating-point sub

This pattern enables the combine pass (or late-combine, depending on the case)
to merge a vec_duplicate into a minus RTL instruction. The vec_duplicate is the
subtrahend operand.

Before this patch, we have two instructions, e.g.:
  vfmv.v.f       v2,fa0
  vfsub.vv       v1,v1,v2

After, we get only one:
  vfsub.vf       v1,v1,fa0

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*vfsub_vf_<mode>): New pattern to
	combine vec_duplicate + vfsub.vv into vfsub.vf.
	* config/riscv/vector.md (@pred_<optab><mode>_scalar): Allow VLS modes.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c: Adjust scan
	dumps.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfsub.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: Add data for
	vfsub.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f64.c: New test.

0 files changed, 0 insertions, 0 deletions