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path: root/opcodes/aarch64-asm.c
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2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson1-2/+2
2019-05-09[binutils][aarch64] New sve_size_tsz_bhs iclass.Matthew Malcomson1-0/+6
2019-05-09[binutils][aarch64] New sve_shift_tsz_bhsd iclass.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-2/+4
2019-05-09[binutils][aarch64] New sve_size_013 iclass.Matthew Malcomson1-0/+8
2019-05-09[binutils][aarch64] New sve_size_bh iclass.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New sve_size_sd2 iclass.Matthew Malcomson1-0/+4
2019-05-09[binutils][aarch64] New iclass sve_size_hsd2.Matthew Malcomson1-0/+5
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte...Sudi Das1-11/+0
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-0/+11
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten...Sudakshina Das1-1/+2
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex...Sudakshina Das1-0/+2
2018-10-03AArch64: Constraint disassembler and assembler changes.Tamar Christina1-1/+33
2018-10-03AArch64: Wire through instr_sequenceTamar Christina1-1/+2
2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina1-0/+31
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina1-186/+248
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-1/+1
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-0/+30
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina1-0/+14
2017-05-18Don't compare boolean values against TRUE or FALSEAlan Modra1-3/+2
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-30/+48
2017-02-22aarch64: actually copy first operand in convert_bfc_to_bfm()Jan Beulich1-2/+2
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-08AArch64/opcodes: Correct another `index' global shadowing errorMaciej W. Rozycki1-8/+8
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-3/+47
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-0/+24
2016-10-11[AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudoJiong Wang1-1/+1
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-0/+43
2016-09-21[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford1-0/+84
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-0/+45
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-6/+91
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-0/+50
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-0/+108
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-0/+13
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-0/+27
2016-09-21[AArch64][SVE 16/32] Use specific insert/extract methods for fpimmRichard Sandiford1-0/+10
2016-09-21[AArch64][SVE 15/32] Add {insert,extract}_all_fields helpersRichard Sandiford1-7/+21
2016-09-21[AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element sizeRichard Sandiford1-2/+2
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-11[AArch64][Patch 4/5] Support HINT aliases taking operands.Matthew Wahab1-0/+13
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab1-0/+34
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-09-03[PATCH/AArch64] Implement LSE featureJiong Wang1-0/+8
2014-03-05Update copyright yearsAlan Modra1-1/+1
2013-08-23 PR binutils/15834Nick Clifton1-2/+2
2013-05-13gas/Yufeng Zhang1-1/+0
2013-01-30include/opcode/Yufeng Zhang1-1/+17
2013-01-17include/opcode/Yufeng Zhang1-1/+5
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