rocket-tools/riscv-gnu-toolchain/binutils.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-05-29	MIPS/opcodes: Properly handle ISA exclusion	Maciej W. Rozycki	1	-19/+18
2021-05-29	MIPS/opcodes: Factor out ISA matching against flags	Maciej W. Rozycki	1	-4/+21
2021-05-29	MIPS/opcodes: Do not use CP0 register names for control registers	Maciej W. Rozycki	1	-2/+9
2021-05-29	MIPS/opcodes: Free up redundant `g' operand code	Maciej W. Rozycki	1	-2/+1
2021-04-01	Remove strneq macro and use startswith.	Martin Liska	1	-1/+0
2021-03-31	Use bool in include	Alan Modra	5	-46/+45
2021-03-31	Remove bfd_stdint.h	Alan Modra	4	-5/+4
2021-03-29	TRUE/FALSE simplification	Alan Modra	1	-7/+5
2021-03-29	opcodes int vs bfd_boolean fixes	Alan Modra	1	-1/+1
2021-03-16	RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions	Kuan-Lin Chen	2	-0/+107
2021-02-19	RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.	Nelson Chu	1	-64/+71
2021-02-18	RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.	Nelson Chu	1	-69/+0
2021-02-15	IBM Z: Implement instruction set extensions	Andreas Krebbel	1	-0/+1
2021-02-08	opcodes: tic54x: namespace exported variables	Mike Frysinger	1	-4/+4
2021-02-05	RISC-V: PR27348, Remove the obsolete OP_*CUSTOM_IMM.	Nelson Chu	1	-2/+0
2021-02-05	RISC-V: PR27348, Remove obsolete Xcustom support.	Nelson Chu	1	-72/+0
2021-02-04	RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.	Nelson Chu	2	-112/+0
2021-01-15	RISC-V: Indent and GNU coding standards tidy, also aligned the code.	Nelson Chu	1	-44/+51
2021-01-15	RISC-V: Comments tidy and improvement.	Nelson Chu	2	-31/+17
2021-01-11	aarch64: Remove support for CSRE	Kyrylo Tkachov	1	-2/+0
2021-01-07	RISC-V: Add pause hint instruction.	Philipp Tomsich	2	-0/+4
2021-01-07	RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).	Claire Xenia Wolf	2	-1/+114
2021-01-01	PR27116, Spelling errors found by Debian style checker	Alan Modra	1	-1/+1
2021-01-01	Update year range in copyright notice of binutils files	Alan Modra	69	-69/+69
2020-12-18	Constify more arrays	Alan Modra	1	-1/+1
2020-12-10	RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.	Nelson Chu	1	-0/+4
2020-12-10	RISC-V: Control fence.i and csr instructions by zifencei and zicsr.	Nelson Chu	1	-2/+4
2020-12-01	RISC-V: Support to add implicit extensions for G.	Nelson Chu	1	-0/+2
2020-12-01	RISC-V: Improve the version parsing for arch string.	Nelson Chu	1	-2/+2
2020-11-16	aarch64: Extract Condition flag manipulation feature from Armv8.4-A	Przemyslaw Wirkus	1	-1/+3
2020-11-09	Add support for the LMBD (left-most bit detect) instruction to the PRU assemb...	Spencer E. Olson	1	-16/+18
2020-11-09	aarch64: Limit Rt register number for LS64 load/store instructions	Przemyslaw Wirkus	1	-0/+1
2020-11-06	aarch64: Extract Pointer Authentication feature from Armv8.3-A	Przemyslaw Wirkus	1	-0/+2
2020-11-04	aarch64: Update feature RAS system registers	Przemyslaw Wirkus	1	-2/+2
2020-11-03	[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7	Przemyslaw Wirkus	1	-1/+3
2020-10-28	aarch64: Add CSR PDEC instruction	Przemyslaw Wirkus	1	-0/+2
2020-10-28	aarch64: Add DSB instruction Armv8.7-a variant	Przemyslaw Wirkus	1	-0/+2
2020-10-28	aarch64: Add basic support for armv8.7-a architecture	Przemyslaw Wirkus	1	-0/+3
2020-10-26	CSKY: Add version flag in eflag and fix bug in disassembling register.	Cooper Qu	1	-0/+5
2020-09-12	CSKY: Change ISA flag's type to bfd_uint64_t and fix build error.	Cooper Qu	1	-31/+36
2020-09-10	Fix compile time warnings when building for the CSKY target on a 32-bit host.	Nick Clifton	1	-1/+1
2020-09-09	CSKY: Change mvtc and mulsw's ISA flag.	Cooper Qu	1	-0/+1
2020-09-09	CSKY: Add FPUV3 instructions, which supported by ck860f.	Cooper Qu	1	-0/+2
2020-09-08	aarch64: Add support for Armv8-R system registers	Alex Coplan	1	-2/+4
2020-09-08	aarch64: Add base support for Armv8-R	Alex Coplan	1	-1/+7
2020-09-02	ubsan: v850-opc.c:412 left shift cannot be represented	Alan Modra	1	-1/+1
2020-09-02	CSKY: Add CPU CK803r3.	Cooper Qu	1	-0/+1
2020-08-31	PR26493 UBSAN: elfnn-riscv.c left shift of negative value	Alan Modra	1	-4/+4
2020-08-28	CSKY: Support attribute section.	Cooper Qu	1	-27/+28
2020-08-24	CSKY: Add new arch CK860.	Cooper Qu	1	-0/+2