| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-06-18 | RISC-V: Add SiFive cease extension v1.0 | Hau Hsu | 3 | -0/+8 |
| 2024-06-18 | RISC-V: Support Zacas extension. | Gianluca Guida | 9 | -0/+137 |
| 2024-06-18 | Support APX CCMP and CTEST | Cui, Lili | 8 | -16/+720 |
| 2024-06-18 | LoongArch: add .option directive | Lulu Cai | 5 | -0/+60 |
| 2024-06-17 | GAS/testsuite: Make a copy of none.s before operating on it as output | Maciej W. Rozycki | 1 | -2/+11 |
| 2024-06-17 | GAS/testsuite: Add a helper for paths outside the source dir | Maciej W. Rozycki | 1 | -0/+13 |
| 2024-06-14 | aarch64: add SPMU system registers missed in f01ae0392ed | Matthieu Longo | 3 | -1/+539 |
| 2024-06-12 | aarch64: add Branch Record Buffer extension instructions | Claudio Bantaloukas | 9 | -0/+54 |
| 2024-06-12 | RISC-V: Support S[sm]csrind extension csrs. | Jiawei | 8 | -36/+525 |
| 2024-06-11 | MIPS/opcodes: Add MIPS Allegrex DBREAK instruction | David Guillen Fandos | 2 | -1/+3 |
| 2024-06-11 | MIPS/opcodes: Exclude trap instructions for MIPS Allegrex | David Guillen Fandos | 4 | -0/+30 |
| 2024-06-10 | aarch64: warn on unpredictable results for new rcpc3 instructions | Matthieu Longo | 5 | -25/+267 |
| 2024-06-10 | Revert "MIPS/Allegrex: Exclude trap instructions" | Maciej W. Rozycki | 3 | -27/+0 |
| 2024-06-10 | Revert "MIPS/Allegrex: Enable dbreak instruction" | Maciej W. Rozycki | 2 | -3/+1 |
| 2024-06-10 | MIPS/Allegrex: Enable dbreak instruction | David Guillen Fandos | 2 | -1/+3 |
| 2024-06-10 | MIPS/Allegrex: Exclude trap instructions | David Guillen Fandos | 3 | -0/+27 |
| 2024-06-10 | x86: disassembler macro for condition code | Jan Beulich | 6 | -276/+276 |
| 2024-06-10 | x86/APX: support extended SETcc form | Jan Beulich | 3 | -0/+9 |
| 2024-06-10 | gas: extend \+ support to .rept | Jan Beulich | 3 | -0/+26 |
| 2024-06-06 | arm: fix testsuite fallout on arm-elf and arm-nto from FPA removal | Richard Earnshaw | 5 | -3/+7 |
| 2024-06-06 | RISC-V: Add support for Zvfbfwma extension | Xiao Zeng | 3 | -0/+20 |
| 2024-06-06 | RISC-V: Add support for Zvfbfmin extension | Xiao Zeng | 3 | -0/+20 |
| 2024-06-06 | RISC-V: Add support for Zfbfmin extension | Xiao Zeng | 3 | -0/+18 |
| 2024-06-05 | arm: remove disassembly support for the FPA co-processor | Richard Earnshaw | 2 | -6/+6 |
| 2024-06-05 | arm: redirect fp constant data directives through a wrapper | Richard Earnshaw | 11 | -5/+35 |
| 2024-06-05 | arm: remove FPA related tests | Richard Earnshaw | 27 | -1858/+119 |
| 2024-06-05 | RISC-V: Tidy vendor core-v extension gas testcases | Nelson Chu | 146 | -1629/+1393 |
| 2024-06-05 | RISC-V: Add support for XCVmem extension in CV32E40P | Mary Bennett | 67 | -0/+725 |
| 2024-06-05 | RISC-V: Add support for XCVbi extension in CV32E40P | Mary Bennett | 17 | -0/+86 |
| 2024-06-05 | RISC-V: Add support for XCVelw extension in CV32E40P | Mary Bennett | 9 | -0/+186 |
| 2024-06-04 | LoongArch: Make align symbol be in same section with alignment directive | mengqinggang | 3 | -3/+38 |
| 2024-06-04 | arm: testsuite: fix msdos line endings in tests | Richard Earnshaw | 2 | -18/+18 |
| 2024-05-31 | aarch64, testsuite: avoid regexes in opcode field | Claudio Bantaloukas | 2 | -493/+493 |
| 2024-05-31 | gas, aarch64: Fixes in texi and tests following faminmax and lut changes | saurabh.jha@arm.com | 3 | -154/+154 |
| 2024-05-29 | x86/Intel: warn about undue mnemonic suffixes | Jan Beulich | 31 | -157/+101 |
| 2024-05-29 | x86/Intel: SHLD/SHRD have dual meaning | Jan Beulich | 3 | -0/+74 |
| 2024-05-28 | gas, aarch64: Add SVE2 lut extension | saurabh.jha@arm.com | 8 | -1/+461 |
| 2024-05-28 | gas, aarch64: Add AdvSIMD lut extension | saurabh.jha@arm.com | 7 | -0/+428 |
| 2024-05-24 | Re: LoongArch: gas: Adjust DWARF CIE alignment factors | Alan Modra | 1 | -22/+22 |
| 2024-05-24 | gas: extend \+ support to .irp / .irpc | Jan Beulich | 4 | -14/+10 |
| 2024-05-24 | gas: adjust handling of quotes for .irpc | Jan Beulich | 3 | -0/+26 |
| 2024-05-24 | x86: correct VCVT{,U}SI2SD | Jan Beulich | 2 | -0/+9 |
| 2024-05-22 | aarch64: fix incorrect encoding for system register pmsdsfr_el1 | Matthieu Longo | 1 | -2/+2 |
| 2024-05-22 | Support APX zero-upper | Cui, Lili | 6 | -0/+285 |
| 2024-05-22 | Add check for 8-bit old registers in EVEX format | Cui, Lili | 2 | -0/+5 |
| 2024-05-20 | aarch64: Add support for the fpmr system register | Claudio Bantaloukas | 4 | -0/+23 |
| 2024-05-17 | aarch64: correct SVE2.1 ld2q (scalar plus scalar) | Jan Beulich | 1 | -1/+1 |
| 2024-05-17 | aarch64: correct SVE2.1 ld{3,4}q / st{3,4}q (scalar plus immediate) | Jan Beulich | 3 | -13/+13 |
| 2024-05-16 | aarch64: fp8 convert and scale - add sme2 insn variants | Victor Do Nascimento | 6 | -2/+623 |
| 2024-05-16 | aarch64: fp8 convert and scale - add sve2 insn variants | Victor Do Nascimento | 7 | -0/+313 |
