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11 daysRISC-V: Add extension XTheadVdot for T-Head VECTOR vendor extension [1]Jin Ma1-0/+5
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the additional extension "XTheadVdot" based on the "V" extension, and it provides four 8-bit multiply and add with 32-bit instructions for the "v" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([2]). Co-Authored-By: Lifang Xia <lifang_xia@linux.alibaba.com> [1] https://github.com/XUANTIE-RV/thead-extension-spec/tree/master/xtheadvdot [2] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add support for "XTheadVdot" extension. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Likewise. * testsuite/gas/riscv/march-help.l: Likewise. * testsuite/gas/riscv/x-thead-vdot.d: New test. * testsuite/gas/riscv/x-thead-vdot.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VMAQA_VV): New. * opcode/riscv.h (enum riscv_insn_class): Add insn class for XTheadVdot. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2025-03-14gas: permit wider-than-byte operands for .cfi_escapeJan Beulich1-0/+12
Some DW_CFA_* and DW_OP_* take wider than byte, but non-LEB128 operands. Having to hand-encode such when needing to resort to .cfi_escape isn't very helpful.
2025-03-14gas: permit LEB128 operands for .cfi_escapeJan Beulich1-1/+12
Many DW_CFA_* and DW_OP_* take LEB128 operands. Having to hand-encode such when needing to resort to .cfi_escape isn't very helpful.
2025-02-14x86/APX: make .insn extended-EVEX capableJan Beulich1-2/+9
So far tricks had to be played to use .insn to encode extended-EVEX insns; the X4 bit couldn't be controlled at all. Extend the syntax just enough to cover all features, taking care to reject invalid feature combinations (albeit aiming at being as lax there as possible, to offer users as much flexibility as we can - we don't, after all, know what future will bring). In a pre-existing testcase replace all but one .byte; the one that needs to remain wants to have EVEX.U clear in a way that's neither controllable via AVX10/256 embedded rounding (would otherwise also set EVEX.ND), nor via the index register (EVEX.X4), as there's no memory operand. For one of the converted instances ModR/M.mod needs correcting: An 8-bit displacement requires that to be 1, not 2. Also adjust source comments to better represent what the bad insns mimic.
2025-02-14RISC-V: Add missing doc for OP_VKito Cheng1-0/+3
2025-02-14RISC-V: Add OP_VE for .insnKito Cheng1-0/+3
OP_VE is the opcode space for crypto vector instructions. Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/vector-crypto.adoc#crypto-vector-cryptographic-instructions
2025-02-11RISC-V: Add .bfloat16 directiveKito Cheng1-0/+10
RISC-V already support bfloat16 instruciton like Zfbfmin, Zvfbfmin and Zvfbfwma, so I think it's reasonable to add .bfloat16 directive to support bfloat16 data type. And the code logic mostly support by common code already.
2025-02-07x86: Support x86 Zhaoxin PadLock XMODX instructionsMayShao-oc1-1/+3
The CPUID EDX bit[28] indicates its enablement, and it includes REP XMODEXP and REP MONTMUL2. XMODX stands for modular exponentiation, it indicates the support of modular exponentiation feature, both REP XMODEXP and REP MONTMUL2 use it. gas/ChangeLog: * NEWS: Support Zhaoxin PadLock XMODX instructions. * config/tc-i386.c (add_branch_prefix_frag_p): Don't add prefix to PadLockXMODX instructions. (output_insn): Handle PadLockXMODX instructions. * doc/c-i386.texi: Document PadLockXMODX. * testsuite/gas/i386/i386.exp: Add PadLockXMODX test. * testsuite/gas/i386/padlockxmodx.d: Ditto. * testsuite/gas/i386/padlockxmodx.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add PadLockXMODX. * i386-gen.c: Ditto * i386-opc.h (CpuPadLockXMODX): New. * i386-opc.tbl: Add Zhaoxin PadLock XMODX instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2025-01-31aarch64: Support +sme+nosve permissivelyAndrew Carlotti1-2/+2
There is inconsistency regarding whether or not +sme implies +sve2 and whether +nosve2 implies +nosme. In particular, GCC 14 assumes the dependency exists, and canonicalises target strings accordingly, whereas LLVM treats the features as independent. This patch removes the positive implication while retaining the negative implication. This is the more permissive choice in each case, and allows us to support target strings written with either interpretation in mind. This reduces our ability to detect invalid instructions, but we already can't rely on this detection because gas doesn't know whether functions might be executed in streaming mode and/or non-streaming mode. The aarch64_feature_enable_set change is functionally redundant within this patch. It is included because the longer term intention is to instead remove the workaround in aarch64_parse_features, once the internal feature checks have been modified to support having both AARCH64_FEATURE_SME set and AARCH64_FEATURE_SVE unset. Similarly, the dependency from +sme to +fp16 is currently redundant, but this redundancy relies upon an incorrect dependency from +fcma to +fp16. This can be fixed in the future, but it might require modifying internal feature checks for a few FCMA instructions, so it's left unchanged for now.
2025-01-31aarch64: Fix fp8 feature dependenciesAndrew Carlotti1-8/+8
We agreed with LLVM that we shouldn't enforce the architectural dependencies between fp8 muliplication features, so remove them. Additionally, fix a typo in the gating for FEAT_SME_F8F16 instructions, which were mistakenly gated by +sme-f8f32 instead. Until now this mistake had been masked by the dependency between the features.
2025-01-31aarch64: Fix overly lax +frintts dependencyAndrew Carlotti1-1/+1
We agreed with LLVM that +frintts should only enable +fp, not +simd. This also matches the dependency used in GCC.
2025-01-31x86: support RMPREAD insnJan Beulich1-2/+4
Like for RMPUPDATE documentation is about to change as far as operands are concerned. They're merely the other way around here. While adjustind gas documentation, also add the missing RMPQUERY counterparts there.
2025-01-31RISC-V: widen LEB128 supportJan Beulich1-4/+5
Do away with at least one of the limitations - all other targets permit multiple values to be specified with a single directive. Re-arrange the logic further to also overcome an internal error in riscv_insert_uleb128_fixes(), as e.g. observed by the all/sleb128-2 testcase. This way there's also no need to parse expressions twice, thus also not raising the same diagnostics (if any) twice. Note how this addresses a pre-existing XFAIL (where the comment wasn't really applicable either for RISC-V). Also update documentation, also to mention that differences between symbols may be used with .uleb128 (albeit I'm uncertain whether there are limitations).
2025-01-27Fix some broken links in docs and commentsYury Khrustalev2-6/+7
Reviewed-By Richard Earnshaw <richard.earnshaw@arm.com>
2025-01-22x86: Add missing @tab to separate columns in c-i386.texitimhu20111-2/+2
I have missed @tab for .gmiccs and .padlockphe2, so fix this doc error. gas/ChangeLog: * doc/c-i386.texi: Add the missing @tab for .gmiccs and .padlockphe2
2025-01-21Support broken gcc test for gas string merge supportAlan Modra1-1/+1
On casual reading of older gcc configure scripts it might be supposed that the test for gas string merge support tries with %progbits after a fail on ARM with @progbits. It doesn't succeed due to a bug. So to support building of older gcc's for ARM without users having to edit gcc sources, add a hack to gas. The hack can disappear in a few years when building older gcc's likely requires other work too. I've changed the docs to reflect what we actually allow for .section syntax prior to this patch. (No way should this hack be documented as allowed!) PR 32491 * config/obj-elf.c (obj_elf_section): Allow missing entsize for ARM gcc configure bug. * doc/as.texi: Correct syntax of ELF .section directive. * testsuite/gas/elf/string.s, * testsuite/gas/elf/string.d: Test it.
2025-01-20gas: elf: Relax rules for SHF_STRING sectionsRichard Earnshaw1-10/+18
Commit af3394d97a8c5187085c0eec5fb03e8da88db5fb allowed sections declared with "S" (SHF_STRING) to specify the entity size, but then would warn if the entity size was omitted, as with the old syntax. Unfortunately, since specifying the entity size is incompatible with binutils 2.43 or earlier, this makes it impossible to specify a strings section in source code without generating an assembly warning (the new syntax isn't supported in older assemblers and the old syntax generates warnings). Nevertheless, the old code was wrong in that it did not set the entity size at all, in contravention of the ELF specification (though to date there are no known cases where this mattered outside of mergeable sections). Fix this by permitting the original syntax without a warning again, but by defaulting the entity size to 1. This is compatible with the most common case of strings being byte-based. Added some tests for the various flavours of declaration that we support.
2025-01-17x86: Add CpuGMISM2 and CpuGMICCSMayShao-oc1-3/+4
There are separate CPUID feature bits for SM2 and CCS instructions. CCS is the acronym of Chinese Cipher System, it includes SM3 and SM4 instructions. This patch adds CpuGMISM2 and CpuGMICCS to replace CpuGMI on corresponding instructions. gas/ChangeLog: * config/tc-i386.c: Add gmism2 and gmiccs to replace gmi. * doc/c-i386.texi: Ditto. opcodes/ChangeLog: * i386-gen.c: Add GMISM2 and GMICCS to replace GMI. * i386-opc.h (enum i386_cpu): Add CpuGMISM2 and CpuGMICCS to replace CpuGMI. * i386-opc.tbl: Replace GMI with GMISM2 on sm2 instruction. Replace GMI with GMICCS on sm3 and sm4 instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2025-01-16x86: Support x86 Zhaoxin PadLock PHE2 instructionsMayShao-oc1-1/+3
The CPUID EDX bit[26] indicates its enablement, and it includes REP XSHA384 and REP XSHA512. gas/ChangeLog: * NEWS: Support Zhaoxin PadLock PHE2 instructions. * config/tc-i386.c (add_branch_prefix_frag_p): Don't add prefix to PadLockPHE2 instructions. (output_insn): Handle PadLockPHE2 instructions. * doc/c-i386.texi: Document PadLockPHE2. * testsuite/gas/i386/i386.exp: Add PadLockPHE2 test. * testsuite/gas/i386/padlock_phe2.d: Ditto. * testsuite/gas/i386/padlock_phe2.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add PadLockPHE2. * i386-gen.c: Ditto * i386-opc.h (CpuPadLockPHE2): New. * i386-opc.tbl: Add Zhaoxin PadLock PHE2 instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2025-01-14Support Intel AMX-AVX512Haochen Jiang1-1/+3
This patch will support AMX-AVX512. In disassmbler, we pull out all GPR mode out of the vex length switch to make it more general. gas/ChangeLog: * NEWS: Mention the full support on DMR AMX ISAs. * config/tc-i386.c: Add amx_avx512. * doc/c-i386.texi: Document .amx_avx512. * testsuite/gas/i386/x86-64.exp: Run AMX-AVX512 tests. * testsuite/gas/i386/x86-64-amx-avx512-intel.d: New test. * testsuite/gas/i386/x86-64-amx-avx512.d: Ditto. * testsuite/gas/i386/x86-64-amx-avx512.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-len.h: Add EVEX_LEN_0F384A_X86_64_W_0, EVEX_LEN_0F386D_X86_64_W_0, EVEX_LEN_0F3A07_X86_64_W_0, EVEX_LEN_0F3A77_X86_64_W_0. * i386-dis-evex-prefix.h: Add PREFIX_EVEX_0F384A_W_0_L_2, PREFIX_EVEX_0F386D_W_0_L_2, PREFIX_EVEX_0F3A07_W_0_L_2, PREFIX_EVEX_0F3A77_W_0_L_2. * i386-dis-evex-w.h: Add EVEX_W_0F384A_X86_64, EVEX_W_0F386D_X86_64, EVEX_W_0F3A07_X86_64, EVEX_W_0F3A77_X86_64. * i386-dis-evex-x86-64.h: Add X86_64_EVEX_0F384A, X86_64_EVEX_0F386D, X86_64_EVEX_0F3A07, X86_64_EVEX_0F3A77. * i386-dis-evex.h: Ditto. * i386-dis.c (EVEX_LEN_0F384A_X86_64_W_0): New. (EVEX_LEN_0F386D_X86_64_W_0): Ditto. (EVEX_LEN_0F3A07_X86_64_W_0): Ditto. (EVEX_LEN_0F3A77_X86_64_W_0): Ditto. (MOD_EVEX_0F384A_X86_64_W_0): Ditto. (MOD_EVEX_0F386D_X86_64_W_0): Ditto. (MOD_EVEX_0F3A07_X86_64_W_0): Ditto. (MOD_EVEX_0F3A77_X86_64_W_0): Ditto. (PREFIX_EVEX_0F384A_W_0_L_2): Ditto. (PREFIX_EVEX_0F386D_W_0_L_2): Ditto. (PREFIX_EVEX_0F3A07_W_0_L_2): Ditto. (PREFIX_EVEX_0F3A77_W_0_L_2): Ditto. (EVEX_W_0F384A_X86_64): Ditto. (EVEX_W_0F386D_X86_64): Ditto. (EVEX_W_0F3A07_X86_64): Ditto. (EVEX_W_0F3A77_X86_64): Ditto. (X86_64_EVEX_0F384A): Ditto. (X86_64_EVEX_0F386D): Ditto. (X86_64_EVEX_0F3A07): Ditto. (X86_64_EVEX_0F3A77): Ditto. (OP_VEX): Pull out all GPR mode out of the vector length switch. * i386-gen.c (isa_dependencies): Add AMX-AVX512. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_AVX512): New. (i386_cpu_flags): Add cpuamx_avx512. * i386-opc.tbl: Add AMX-AVX512 instructions. * i386-tbl.h: Regenerated.
2025-01-14Support Intel AMX-MOVRSHu, Lin11-1/+2
This patch will support AMX-MOVRS feature. Unlike all the other AMX insns in vector space where we pass vex_len_table before vex_w_table, we first pass vex_w_table for tileloaddrs[,t1] to align with the order in EVEX space. The reason why we first pass vex_w_table in EVEX space is due to AMX-AVX512, where tcvtrowd2ps and tilemovrow with r32 shares the same opcode with tileloaddrs[,t1]. All of them have evex.w = 0 but with different evex.length. Re-doing that shortly is not ideal. APX_F extension is also implemented in this patch. The encoding will be: - EVEX.128.NP/66.MAP5.W0 F8/F9 !(11):rrr:100 for T2RPNTLVW[Z0,Z1]RS[,T1] with NF=0. - EVEX.128.F2/66.0F38.W0 4A !(11):rrr:100 FOR TILELOADDRS[,T1] with NF=0. For APX_F extension, we could not use APX_F(AMX_TRANSPOSE&AMX_MOVRS) since the transformation could not be done. Instead, we will use AMX_TRANSPOSE & APX_F(AMX_MOVRS). Thus, we should set AMX_TRANSPOSE for "any" for cpu_flags in assembler. Since it will only affect the cpu_flags_match, handle that there. gas/ChangeLog: * config/tc-i386.c (cpu_arch): Add amx_movrs. (cpu_flags_match): Set any bitfield for multiple cpuid enabled insns. * doc/c-i386.texi: Document .amx_movrs. * testsuite/gas/i386/x86-64.exp: Run AMX-MOVRS tests. * testsuite/gas/i386/x86-64-amx-movrs-intel.d: New test. * testsuite/gas/i386/x86-64-amx-movrs-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-movrs-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-movrs.d: Ditto. * testsuite/gas/i386/x86-64-amx-movrs.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-len.h (EVEX_LEN_0F384A_X86_64_W_0): New. * i386-dis-evex-w.h (EVEX_W_0F384A_X86_64): Ditto. * i386-dis-evex-x86-64.h (X86_64_EVEX_0F384A): Ditto. * i386-dis-evex.h: New entry for AMX-MOVRS. * i386-dis.c: (PREFIX_VEX_0F384A_X86_64_L_0_W_0): New. (PREFIX_VEX_MAP5_F8_X86_64_L_0_W_0): Ditto. (PREFIX_VEX_MAP5_F9_X86_64_L_0_W_0): Ditto. (X86_64_VEX_0F384A): Ditto. (X86_64_VEX_MAP5_F8): Ditto. (X86_64_VEX_MAP5_F9): Ditto. (X86_64_EVEX_0F384A): Ditto. (VEX_LEN_0F384A_X86_64_W_0): Ditto. (VEX_LEN_MAP5_F8_X86_64): Ditto. (VEX_LEN_MAP5_F9_X86_64): Ditto. (EVEX_LEN_0F384A_X86_64_W_0): Ditto. (VEX_W_0F384A_X86_64): Ditto. (VEX_W_MAP5_F8_X86_64): Ditto. (VEX_W_MAP5_F9_X86_64): Ditto. (EVEX_W_0F384A_X86_64): Ditto. (prefix_table): New entry for AMX-MOVRS. (x86_64_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (map5_f8_opcode): New. (map5_f9_opcode): Ditto. (get_valid_dis386): Handle VEX_MAP5 opcode for AMX-MOVRS. * i386-gen.c (isa_dependencies): Add AMX_MOVRS. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_MOVRS): New. (i386_cpu_flags): Add cpuamx_movrs. * i386-opc.tbl: Add AMX-MOVRS instructions. * i386-tbl.h: Regenerated. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2025-01-14Support Intel MOVRSHu, Lin11-0/+2
This patch focus on supporting MOVRS ISA. We could take this full ISA as four part: PREFETCHRST2, MOVRS, MOVRS APX_F extension and MOVRS AVX10.2 extension. The APX_F extension for MOVRS will be: - EVEX.LLZ.NP.MAP4.WIG 8A !(11):rrr:bbb for r8/m8 with NF=0 and ND=0 - EVEX.LLZ.NP/66.MAP4.SCALABLE 8B !(11):rrr:bbb for rv/mv with NF=0 and ND=0 We did not merge the table together for APX_F since there is an explicit x64 for movrs insn. The current APX_F() did not support the combination between CPUIDs. Also, the space is different for legacy and apx_f forms. gas/ChangeLog: * NEWS: Support Intel MOVRS. * config/tc-i386.c: Add MOVRS. * doc/c-i386.texi: Document .movrs. * testsuite/gas/i386/i386.exp: Run MOVRS tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Add MOVRS tests. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. * testsuite/gas/i386/lfence-load.d: Add prefetchrst2. * testsuite/gas/i386/lfence-load.s: Ditto. * testsuite/gas/i386/nops-8.d: Ditto. * testsuite/gas/i386/prefetch-intel.d: Ditto. * testsuite/gas/i386/prefetch.d: Ditto. * testsuite/gas/i386/x86-64-lfence-load.d: Ditto. * testsuite/gas/i386/x86-64-lfence-load.s: Ditto. * testsuite/gas/i386/x86-64-prefetch-intel.d: Ditto. * testsuite/gas/i386/x86-64-prefetch.d: Ditto. * testsuite/gas/i386/movrs-intel.d: New test. * testsuite/gas/i386/movrs-inval.l: Ditto. * testsuite/gas/i386/movrs-inval.s: Ditto. * testsuite/gas/i386/movrs.d: Ditto. * testsuite/gas/i386/movrs.s: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-256-intel.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-256.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-256.s: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-512-intel.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-512.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-512.s: Ditto. * testsuite/gas/i386/x86-64-movrs-intel.d: Ditto. * testsuite/gas/i386/x86-64-movrs.d: Ditto. * testsuite/gas/i386/x86-64-movrs.s: Ditto. * testsuite/gas/i386/x86-64-movrs-intel-suffix.d: Ditto. * testsuite/gas/i386/x86-64-movrs-suffix.d: Ditto. * testsuite/gas/i386/x86-64-movrs-suffix.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Add PREFIX_EVEX_MAP5_6F_X86_64. * i386-dis-evex-x86.h: Add X86_64_EVEX_MAP5_6F. * i386-dis-evex.h (evex_table): New entry for movrs. * i386-dis.c (MOD_0F18_REG_4): New. (PREFIX_EVEX_MAP5_6F_X86_64): Ditto. (X86_64_0F388A): Ditto. (X86_64_0F388B): Ditto. (X86_64_EVEX_MAP5_6F): Ditto. (three_byte_table): New entry for MOVRS. (reg_table): Ditto. (mod_table): Ditto. (x86_64_table): Ditto. Also include i386-dis-evex-x86.h. * i386-gen.c (cpu_flags): Add MOVRS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (i386_cpu_flags): Add cpumovrs. * i386-opc.tbl: Add MOVRS instrctions. * i386-tbl.h: Regenerated. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com> Co-authored-by: Lili Cui <lili.cui@intel.com>
2025-01-10aarch64: Add support for FEAT_SME_B16B16 feature.Srinath Parvathaneni1-0/+2
This patch adds support for SME ZA-targeting non-widening BFloat16 instructions, under tick FEAT_SME_B16B16 and command line flag "+sme-b16b16". FEAT_SME_B16B16 implements FEAT_SME2 and FEAT_SVE_B16B16, in accordance with that "+sme-b16b16" enables "+sme2" and "+sve-b16b16". Also the test files related to FEAT_SME_B16B16 are prefixed with sme-b16b16*. eg: sme-b16b16-1.s, sme-b16b16-1.d. The spec for this feature and instructions is availabe here [1]: [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
2025-01-10aarch64: Add support for FEAT_SVE_B16B16 feature.Srinath Parvathaneni1-2/+2
In the current code, SVE2 Bfloat16 instructions are implemented with tick FEAT_B16B16 and command line flag "+b16b16" and this feature was suspended due to incomplete support. In the new spec available here[1], FEAT_B16B16 is replaced with FEAT_SVE_B16B16 and command line flag "+b16b16" is replace with "sve-b16b16". Also the test files related to FEAT_SVE_B16B16 are prefixed with sve-b16b16*. eg: sve-b16b16-sve2-1.s, sve-b16b16-sve2-1.d. This patch supports the SVE Z-targeting non-widening BFloat16 instructions with command line flag "+sve-b16b16+sve2". [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SVE-Instructions?lang=en
2025-01-10aarch64: Add support for FEAT_SME_F16F16 feature.Srinath Parvathaneni1-0/+2
This patch adds support for FEAT_SME_F16F16 feature (Non-widening half-precision FP16 to FP16 arithmetic for SME2), which is enabled using command line flags +sme-f16f16 to -march (which enables both FEAT_SME2 and FEAT_SME_F16F16). There are couple of instructions (fadd and fsub variants) which should be allowed by the assembler on either passing +sme-f16f16 or +sme-f8f16. Those instructions are already supported in the current assembler, this patch adds tests for those instructions as well.
2025-01-10x86: Support x86 Zhaoxin PadLockRNG2 instructionMayShao-oc1-2/+3
This patch adds support for Zhaoxin PadLock RNG2 instruction, the CPUID EDX bit[23] indicates its enablement, it includes REP XRNG2 instruction. gas/ChangeLog: * NEWS: Support Zhaoxin PadLock RNG2 instruction. * config/tc-i386.c (add_branch_prefix_frag_p): Don't add prefix to PadLock RNG2 instruction. (output_insn): Handle PadLock RNG2 instruction. * doc/c-i386.texi: Document PadLock RNG2. * testsuite/gas/i386/i386.exp: Add PadLock RNG2 test. * testsuite/gas/i386/padlock_rng2.d: Ditto. * testsuite/gas/i386/padlock_rng2.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add PadLockRNG2. * i386-gen.c: Ditto * i386-opc.h (CpuPadLockRNG2): New. * i386-opc.tbl: Add Zhaoxin PadLock RNG2 instruction. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2025-01-08Support Intel AMX-FP8Liwei Xu1-1/+2
In this patch, we will support AMX-FP8 feature. Since in the foreseeable future, only AMX-MOVRS will also use VEX_MAP5, we currently will not add a table of 256 entries and handle just like MAP7. gas/ChangeLog: * config/tc-i386.c: Add amx_fp8. * doc/c-i386.texi: Document .amx_fp8. * testsuite/gas/i386/x86-64.exp: Run AMX-FP8 tests. * testsuite/gas/i386/x86-64-amx-fp8-bad.d: New test. * testsuite/gas/i386/x86-64-amx-fp8-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-fp8-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-fp8-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-fp8-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-fp8.d: Ditto. * testsuite/gas/i386/x86-64-amx-fp8.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0): New. (X86_64_VEX_MAP5_FD): Ditto. (VEX_LEN_MAP5_FD_X86_64): Ditto. (VEX_W_MAP5_FD_X86_64_L_0):Ditto. (prefix_table): Add PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0. (x86_64_table): Add X86_64_VEX_MAP5_FD. (vex_len_table): Add VEX_LEN_MAP5_FD_X86_64. (vex_w_table): Add VEX_W_MAP5_FD_X86_64_L_0. * i386-gen.c: Add CPU_AMX_FP8_FLAGS and CPU_ANY_AMX_FP8_FLAGS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h: Add cpuamx_fp8. * i386-opc.tbl: Add AMX_FP8 instructions. * i386-tbl.h: Regenerated. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2025-01-02gas: Revert PR 32391 related commits to fix 3 regressionsH.J. Lu1-59/+1
9f2e3c21f65 Fix the handling or arguments and macro pseudo-variables inside nested assembler macros. introduced 3 regressions of PR gas/32484, PR gas/32486 and PR gas/32487. Revert all PR 32391 related commits and add tests for PR gas/32484, PR gas/32486, PR gas/32487. PR gas/32484 PR gas/32486 PR gas/32487 * testsuite/gas/macros/macros.exp: Run nesting1, nesting2 and nesting3. * testsuite/gas/macros/nesting1.d: New file. * testsuite/gas/macros/nesting1.s: Likewise. * testsuite/gas/macros/nesting2.d: Likewise. * testsuite/gas/macros/nesting2.s: Likewise. * testsuite/gas/macros/nesting3.d: Likewise. * testsuite/gas/macros/nesting3.s: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-01-02Support Intel AMX-TF32Haochen Jiang1-1/+3
In this patch, we will support AMX-TF32. It is a simple ISA comparing to the previous ones, so there is no special handling. gas/ChangeLog: * config/tc-i386.c: Add amx_tf32. * doc/c-i386.texi: Document .amx_tf32. * testsuite/gas/i386/x86-64.exp: Run AMX-TF32 tests. * testsuite/gas/i386/x86-64-amx-tf32-bad.d: New test. * testsuite/gas/i386/x86-64-amx-tf32-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-tf32.d: Ditto. * testsuite/gas/i386/x86-64-amx-tf32.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_0F3848_X86_64_W_0_L_0): New. (X86_64_VEX_0F3848): Ditto. (VEX_LEN_0F3848_X86_64_W_0): Ditto. (VEX_W_0F3848_X86_64): Ditto. (prefix_table): Add PREFIX_VEX_0F3848_X86_64_W_0_L_0. (x86_64_table): Add X86_64_VEX_0F3848. (vex_len_table): Add VEX_LEN_0F3848_X86_64_W_0. (vex_w_table): Add VEX_W_0F3848_X86_64. * i386-gen.c (isa_dependencies): Add AMX_TF32. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_TF32): New. (i386_cpu_flags): Add cpuamx_tf32. * i386-opc.tbl: Add AMX-TF32 instructions. * i386-tbl.h: Regenerated.
2025-01-02Support Intel AMX-TRANSPOSEHaochen Jiang1-1/+2
In this patch, we will support AMX-TRANSPOSE. Since AMX-TRANSPOSE will be used with other CPUIDs very often, we put it into CPU_FLAGS_COMMON. To implement TMM pair, we reused ImplicitGroup and adjust the condition in process_operands for the instructions. APX_F extension is also handled in this patch, where it extends T2RPNTLVW[Z0,Z1][,T1] to EVEX.128.NP/66.0F38.W0 6E/6F !(11):rrr:100 with NF=0. Also, TTDPFP16PS should base on AMX_FP16, not AMX_BF16 in ISE055. It would be fixed in ISE056. gas/ChangeLog: * config/tc-i386.c (cpu_arch): Add amx_transpose. (_is_cpu): Ditto. (process_operands): Adjust the condition for AMX-TRANSPOSE. * doc/c-i386.texi: Document .amx_transpose. * testsuite/gas/i386/x86-64.exp: Run AMX-TRANSPOSE tests. * testsuite/gas/i386/x86-64-amx-transpose-bad.d: New test. * testsuite/gas/i386/x86-64-amx-transpose-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose.s: Ditto. opcodes/ChangeLog: * i386-dis.c (MOD_VEX_0F386E_X86_64_W_0): New. (MOD_VEX_0F386F_X86_64_W_0): Ditto. (PREFIX_VEX_0F385F_X86_64_W_0_L_0): Ditto. (PREFIX_VEX_0F386B_X86_64_W_0_L_0): Ditto. (PREFIX_VEX_0F386E_X86_64_W_0_M_0_L_0): Ditto. (PREFIX_VEX_0F386F_X86_64_W_0_M_0_L_0): Ditto. (X86_64_VEX_0F385F): Ditto. (X86_64_VEX_0F386B): Ditto. (X86_64_VEX_0F386E): Ditto. (X86_64_VEX_0F386F): Ditto. (VEX_LEN_0F385F_X86_64_W_0): Ditto. (VEX_LEN_0F386B_X86_64_W_0): Ditto. (VEX_LEN_0F386E_X86_64_W_0_M_0): Ditto. (VEX_LEN_0F386F_X86_64_W_0_M_0): Ditto. (VEX_W_0F385F_X86_64): Ditto. (VEX_W_0F386B_X86_64): Ditto. (VEX_W_0F386E_X86_64): Ditto. (VEX_W_0F386F_X86_64): Ditto. (mod_table): Add MOD_VEX_0F386E_X86_64_W_0, MOD_VEX_0F386F_X86_64_W_0. (prefix_table): Add PREFIX_VEX_0F386E_X86_64_W_0_M_0_L_0, PREFIX_VEX_0F386F_X86_64_W_0_M_0_L_0. Add new instructions for PREFIX_VEX_0F386C_X86_64_W_0_L_0. (x86_64_table): Add X86_64_VEX_0F385F, X86_64_VEX_0F386B, X86_64_VEX_0F386E, X86_64_VEX_0F386F. (vex_len_table): Add VEX_LEN_0F385F_X86_64_W_0, VEX_LEN_0F386B_X86_64_W_0, VEX_LEN_0F386E_X86_64_W_0_M_0, VEX_LEN_0F386F_X86_64_W_0_M_0. (vex_w_table): Add VEX_W_0F385F_X86_64, VEX_W_0F386B_X86_64, VEX_W_0F386E_X86_64, VEX_W_0F386F_X86_64. * i386-gen.c (cpu_flag_init): Add AMX_TRANSPOSE. (cpu_flags): Add CpuAMX_TRANSPOSE. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_TRANSPOSE): New. (i386_cpu): Add cpuamx_transpose. * i386-opc.tbl: Add AMX-TRANSPOSE instructions. * i386-tbl.h: Regenerated. Co-authored-by: Hu, Lin1 <lin1.hu@intel.com>
2025-01-01Update year range in copyright notice of binutils filesAlan Modra64-66/+66
2024-12-19Fix the handling or arguments and macro pseudo-variables inside nested ↵Nick Clifton1-1/+59
assembler macros. PR 32391
2024-12-17gas: add new command line options to control diagnostic informational messagesMatthieu Longo1-0/+34
gas currently emits informational messages for context information along warnings. In the context of system register tests in AArch64 backend, these messages pollute the tests when checking for error message patterns in stderr output. This patch aims at providing two new flags while preserving the existing behavior if none of the options is provided. * --info, similar to the existing --warn flag to enable diagnostic informational messages (default behavior). * --no-info, similar to the existing --no-warn flag to disable diagnostic informational messages. It also adds the flags to the existing documentation, and command manual.
2024-11-26nios2: Remove binutils support for Nios II target.Sandra Loosemore4-300/+0
The Nios II architecture has been EOL'ed by the vendor. This patch removes all binutils, bfd, gas, binutils, and opcodes support for this target with the exception of the readelf utility. (The ELF EM_* number remains valid and the relocation definitions from the Nios II ABI will never change in future, so retaining the readelf support seems consistent with its purpose as a utility that tries to parse the headers in any ELF file provided as an argument regardless of target.)
2024-11-19Support x86 Intel MSR_IMMHu, Lin11-1/+2
gas/ChangeLog: * NEWS: Support x86 Intel MSR_IMM. * config/tc-i386.c (cpu_arch): Add MSR_IMM. (cpu_flags_match): Add MSR_IMM to APX_F related processing. (i386_assemble): WRMSRNS's first operand is imm32, so add MN_wrmsrns like MN_uwrmsr. * doc/c-i386.texi: Document .msr_imm. * testsuite/gas/i386/i386.exp: Run MSR_IMM tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/msr_imm-inval.l: New test. * testsuite/gas/i386/msr_imm-inval.s: Ditto. * testsuite/gas/i386/x86-64-msr_imm-intel.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add REG_VEX_MAP7_F6_L_0_W_0, PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64, X86_64_VEX_MAP7_F6_L_0_W_0_R_0, VEX_LEN_MAP7_F6, VEX_W_MAP7_F6_L_0. (reg_table): New entry for MSR_IMM. (prefix_table): Ditto. (x86_64_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (map7_f6_opcode): New variable for MAP7. (get_valid_dis386): Support MAP7. * i386-gen.c (cpu_flags): Add MSR_IMM. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (i386_cpu_flags): Add cpumsr_imm. * i386-opc.tbl: Add MSR_IMM instructions. * i386-tbl.h: Regenerated.
2024-11-18ELF: SHF_STRINGS isn't really tied to SHF_MERGEJan Beulich1-9/+10
It's not overly useful without it, but the spec doesn't name any dependency between the two. People may want to use it for purely informational purposes, for example. Adjust, in particular, entity size processing to be engaged if either flag is set, as mandated by the spec.
2024-10-31gas/doc/riscv: Fixed misaligned instruction tableNelson Chu1-42/+42
gas/ * doc/c-riscv.texi: Fixed misaligned instruction table.
2024-10-29gas: constify md_{short,long}opts and md_longopts_sizeJan Beulich1-1/+1
First of all make the declarations globally visible, such that producer and consumer actually share them. For the latter two simply add const (as PPC already had it,), while for the former achieve the effect by converting to an array: There's no need for the extra level of indirection.
2024-10-29RISC-V: Update the doc to match ISA manualKito Cheng1-36/+36
ISA manual use funct* rather than func*[1] (e.g. funct7 rather than func7), and I realized that may something I typo at beginning when I write the patch for `.insn` support...:P [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/rv32.adoc#integer-register-register-operations
2024-10-18x86: Support x86 ZHAOXIN GMI instructionsMayShao-oc1-2/+4
gas/ChangeLog: * NEWS: Support ZHAOXIN GMI instructions. * config/tc-i386.c: Add gmi. * doc/c-i386.texi: Document gmi. * testsuite/gas/i386/i386.exp: Add gmi test. * testsuite/gas/i386/gmi.d: Ditto. * testsuite/gas/i386/gmi.s: Ditto. opcodes/ChangeLog: * i386-dis.c: New comment. * i386-gen.c: Add gmi. * i386-opc.h (CpuGMI): New. * i386-opc.tbl: Add Zhaoxin GMI instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2024-10-10s390: Add arch15 instructionsAndreas Krebbel2-4/+5
opcodes/ * s390-mkopc.c (main) Accept arch15 as CPU string. * s390-opc.txt: Add arch15 instructions. include/ * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH15. gas/ * config/tc-s390.c (s390_parse_cpu): New entry for arch15. * doc/c-s390.texi: Document arch15 march option. * doc/as.texi: Likewise. * testsuite/gas/s390/s390.exp: Run the arch15 related tests. * testsuite/gas/s390/zarch-arch15.d: Tests for arch15 instructions. * testsuite/gas/s390/zarch-arch15.s: Likewise. Signed-off-by: Andreas Krebbel <krebbel@linux.ibm.com> Reviewed-by: Jens Remus <jremus@linux.ibm.com>
2024-09-21x86: Add tls check in gasCui, Lili1-0/+10
Assembler shouldn't accept invalid TLS instructions, TLS relocations can only be used with specific instructions as specified in TLS psABI and linker issues an error when TLS relocations are used with wrong instructions or format. Since it is inconvenient for gcc to rely on linker to report errors, adding TLS check in the assembler stage so that gcc can know TLS errors earlier. gas/ChangeLog: PR gas/32022 * config.in: Regenerate. * config/tc-i386.c *(enum x86_tls_error_type): New. *(struct _i386_insn): Added has_gotrel to indicate whether TLS relocations need to be checked. (x86_check_tls_relocation): Added a new function to check TLS relocation. (x86_report_tls_error): Created a new function to report TLS error. (i386_assemble): Handle x86_check_tls_relocation. (lex_got): Set i.has_gotrel. (OPTION_MTLS_CHECK): Added a new option to contrl TLS check. (struct option): Ditto. (md_parse_option): Ditto. (md_show_usage): Ditto. * configure.ac: Added a new option to check TLS relocation by default. * configure: Regenerated. * doc/c-i386.texi: Document -mtls-check=. * testsuite/gas/i386/i386.exp: Added new tests. * testsuite/gas/i386/ilp32/ilp32.exp: Ditto. * testsuite/gas/i386/ilp32/reloc64.d: Disable TLS check for it. * testsuite/gas/i386/ilp32/x32-tls.d: Ditto. * testsuite/gas/i386/inval-tls.l: Added more test cases. * testsuite/gas/i386/inval-tls.s: Ditto. * testsuite/gas/i386/reloc32.d: Disable TLS check for it. * testsuite/gas/i386/reloc64.d: Ditto. * testsuite/gas/i386/x86-64-inval-tls.l: Added more test cases. * testsuite/gas/i386/x86-64-inval-tls.s: Ditto. * testsuite/gas/i386/x86-64.exp: Added new tests. * testsuite/gas/i386/ilp32/x32-inval-tls.l: New test. * testsuite/gas/i386/ilp32/x32-inval-tls.s: Ditto. * testsuite/gas/i386/ilp32/x86-64-tls.d: Ditto. * testsuite/gas/i386/tls.d: Ditto. * testsuite/gas/i386/tls.s: Ditto. * testsuite/gas/i386/x86-64-tls.d: Ditto. * testsuite/gas/i386/x86-64-tls.s: Ditto. ld/ChangeLog: PR gas/32022 * testsuite/ld-i386/tlsgdesc1.d: Disable TLS check for it. * testsuite/ld-i386/tlsgdesc2.d: Ditto. * testsuite/ld-i386/tlsie2.d: Ditto. * testsuite/ld-i386/tlsie3.d: Ditto. * testsuite/ld-i386/tlsie4.d: Ditto. * testsuite/ld-i386/tlsie5.d: Ditto. * testsuite/ld-i386/tlsgdesc3.d: Ditto. * testsuite/ld-x86-64/tlsdesc3.d: Ditto. * testsuite/ld-x86-64/tlsdesc4.d: Ditto. * testsuite/ld-x86-64/tlsie2.d: Ditto. * testsuite/ld-x86-64/tlsie3.d: Ditto. * testsuite/ld-x86-64/tlsie5.d: Ditto. * testsuite/ld-x86-64/tlsdesc5.d: Ditto.
2024-09-09s390: Document syntax to omit base register operandJens Remus1-2/+3
Document the s390-specific assembler syntax introduced by commit aacf780bca29 ("s390: Allow to explicitly omit base register operand in assembly") to omit the base register operand B in D(X,B) and D(L,B) by coding D(X,) and D(L,). While at it document the alternative syntax to omit the index register operand X in D(X,B) by coding D(,B) instead of D(B). gas/ * doc/c-s390.texi (s390 Operands): Document syntax to omit base register operand. Fixes: aacf780bca29 ("s390: Allow to explicitly omit base register operand in assembly") Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-03RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett1-0/+5
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvsimd` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): Add custom operands. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVsimd as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvsimd. * testsuite/gas/riscv/x-cv-simd.d: New test. * testsuite/gas/riscv/x-cv-simd.s: New test. * testsuite/gas/riscv/x-cv-simd-fail.d: New test. * testsuite/gas/riscv/x-cv-simd-fail.l: New test. * testsuite/gas/riscv/x-cv-simd-fail.s: New test. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVsimd. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVsimd. (enum riscv_insn_class): Add the XCVsimd instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands. * riscv-opc.c: Add XCVsimd instructions.
2024-09-02Support ymm rounding control for Intel AVX10.2Haochen Jiang1-1/+5
In the patch, in order to support ymm rounding for AVX10.2, we derive evex attribute for all cases instead of only for rc_none to encode U bit. Also changed some bad_opcode return due to the share of U bit with APX_F. gas/ChangeLog: * config/tc-i386.c (cpu_flags_match): Handle AVX10_2. (build_evex_prefix): Handle U bit. Derive evex attribute for all cases. (check_VecOperands): Handle AVX10.2 and ymm roundings. * doc/c-i386.texi: Document .avx10.2. * testsuite/gas/i386/i386.exp: Run AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-rounding-intel.d: New test. * testsuite/gas/i386/avx10_2-rounding-inval.l: Ditto. * testsuite/gas/i386/avx10_2-rounding-inval.s: Ditto. * testsuite/gas/i386/avx10_2-rounding.d: Ditto. * testsuite/gas/i386/avx10_2-rounding.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.s: Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add U bit. (get_valid_dis386): Handle U bit. * i386-gen.c (isa_dependencies): Add AVX10.2. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX10_2): New. (i386_cpu_flags): Add cpuavx10_2. * i386-opc.tbl: Add rounding to old entries which do not permit rounding previously. Also eliminate the redundant RegXMM for vcvtps2uqq. * i386-tbl.h: Regenerated.
2024-08-09RISC-V: PR32014, .option directives shuoldn't affect elf attribute.Nelson Chu1-1/+6
The .option arch/rvc/norvc/push/pop directives can only take effect for a small/large specific code region, so they are not file-level architecture setting. They should only affect the mapping symbols only rather than the file-level elf architecture attribute. Otherwise, the elf architecture attribute will appear to missing some extensions when -flto merges files with different .option architecture settings. gas/ PR 32014 * config/tc-riscv.c (file_arch_str): New const char *, rather than the arch_str in the riscv_rps_as.subset_list, it's file-level so only be affected by .attribute arch directive. (riscv_reset_subsets_list_arch_str): Renamed to riscv_set_arch_str, and also can handle both file_arch_str and arch_str in subset_list, just give the pointer address as the input. (riscv_set_arch): Called by -march and .attribute arch, so set both file_arch_str and arch_str in subset_list. (s_riscv_option): Updated .option arch/rvc/norvc/push/pop that only set the arch_str in subset_list. (riscv_write_out_attrs): Output elf architecture attribute according to file_arch_str. Freed file_arch_str. * doc/c-riscv.texi: Added destrbution that .option directives shouldn't affect the elf attribute settings. * testsuite/gas/riscv/option-arch.s: From option-arch-01/02/03 merged. * testsuite/gas/riscv/option-arch-dis.d: Likewise, for dis-assembler. * testsuite/gas/riscv/option-arch-attr.d: Likewise, to check readelf -A.
2024-08-06RISC-V: Add support for XCvBitmanip extension in CV32E40PMary Bennett1-6/+11
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvbitmanip` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add custom operands `Xc6` and `Xc7`. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVbitmanip as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvbitmanip. * testsuite/gas/riscv/x-cv-bitmanip-fail.d: New Test. * testsuite/gas/riscv/x-cv-bitmanip-fail.l: New Test. * testsuite/gas/riscv/x-cv-bitmanip-fail.s: New Test. * testsuite/gas/riscv/x-cv-bitmanip.d: New Test. * testsuite/gas/riscv/x-cv-bitmanip.s: New Test. include/opcode/ChangeLog: * riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbitmanip. * riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbitmanip. (enum riscv_insn_class): Add the XCVbitmanip instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands `Xc6` and `Xc7`. * riscv-opc.c: Add XCvBitmanip instructions.
2024-07-31gas/doc: adjust an @xrefJan Beulich1-1/+1
Old doc tools warn about there not being a . or , following; satisfy those tools by shortening the line and adding a full stop.
2024-07-19gas: consistently drop trailing whitespace when scrubbingJan Beulich1-3/+3
From especially the checks for the two separator forms it appears to follow that the construct being touched is about trailing whitespace. In such a case, considering that for many targets ordinary and line comment chars overlap, take into account that line comment chars override ordinary ones in lex[] (logic elsewhere in do_scrub_chars() actually depends on that ordering, and also accounts for this overriding). Plus of course IS_NEWLINE() would better also be consulted. Note also that the DOUBLESLASH_LINE_COMMENTS change should generally have no effect just yet; it's a prereq for a later change but better fits here. Leave respective comments as well, and update documentation to correct which comment form is actually replaced by a single blank (i.e. neither the ones starting with what {,tc_}comment_chars[] has nor the ones starting with what line_comment_chars[] has).
2024-07-19MIPS/GAS: Handle --trap command-line option dynamicallyMaciej W. Rozycki1-4/+6
We have an ISA check for the '--trap' command-line option that reports its incompatibility with the MIPS I architecture. It doesn't prevent trap instructions from being enabled though, so when attempt is made to emit one in an expansion of one of the division or multiplication macros an assertion failure triggers: .../gas/testsuite/gas/mips/brtr-opt.s: Assembler messages: .../gas/testsuite/gas/mips/brtr-opt.s:3: Error: trap exception not supported at ISA 1 .../gas/testsuite/gas/mips/brtr-opt.s:9: Warning: divide by zero .../gas/testsuite/gas/mips/brtr-opt.s:9: Internal error in macro_build at .../gas/config/tc-mips.c:9064. Please report this bug. The same assertion failure triggers without an earlier error message when the initial ISA is compatible with the '--trap', however at the time an attempt is made to emit a trap instruction from a division or multiplication macro the ISA has been changed by a '.set' pseudo-op to an incompatible one. With the way the situations are mishandled it seems unlikely that anyone relies on the current semantics and a sane approach is to decide on the fly according to the currently selected ISA as to whether to emit trap or breakpoint instructions in the case where '--trap' has been used. Change our code to do so then and clarify that in the manual, which is not explicit about how '--trap' is handled with a changing ISA. Mention the change in NEWS too since it's a applies to a user option.
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