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-rw-r--r--sim/riscv/sim-main.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 378e6f1..172c593 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1,6 +1,6 @@
/* RISC-V simulator.
- Copyright (C) 2005-2024 Free Software Foundation, Inc.
+ Copyright (C) 2005-2025 Free Software Foundation, Inc.
Contributed by Mike Frysinger.
This file is part of simulators.
@@ -1302,7 +1302,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
case INSN_CLASS_ZAAMO:
case INSN_CLASS_ZALRSC:
return execute_a (cpu, iw, op);
- case INSN_CLASS_C:
+ case INSN_CLASS_ZCA:
/* Check whether model with C extension is selected. */
if (riscv_cpu->csr.misa & 4)
return execute_c (cpu, iw, op);