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-rw-r--r--sim/erc32/float.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/sim/erc32/float.c b/sim/erc32/float.c
index 2b851ca..069436c 100644
--- a/sim/erc32/float.c
+++ b/sim/erc32/float.c
@@ -20,7 +20,7 @@
FPU. IEEE trap handling is done as follows:
1. In the host, all IEEE traps are masked
2. After each simulated FPU instruction, check if any exception
- occured by reading the exception bits from the host FPU status
+ occurred by reading the exception bits from the host FPU status
register (get_accex()).
3. Propagate any exceptions to the simulated FSR.
4. Clear host exception bits.