diff options
Diffstat (limited to 'opcodes/ppc-opc.c')
| -rw-r--r-- | opcodes/ppc-opc.c | 89 |
1 files changed, 88 insertions, 1 deletions
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index ba93e56..028295a 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -691,6 +691,52 @@ extract_imm32 (uint64_t insn, return (insn & 0xffff) | ((insn >> 16) & 0xffff0000); } +/* The 32bit SI field in a 64-bit D form prefix instruction when the field is split + into separate SI0 and SI1 fields. */ + +static uint64_t +insert_si32 (uint64_t insn, + int64_t value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0xffff0000ULL) << 16) | (value & 0xffff); +} + +static int64_t +extract_si32 (uint64_t insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + int64_t mask = 1ULL << 31; + int64_t value = ((insn >> 16) & 0xffff0000ULL) | (insn & 0xffff); + value = (value ^ mask) - mask; + return value; +} + +/* The NSI32 field in an 8-byte D form prefix instruction. This is the same + as the SI32 field, only negated. The extraction function always marks it + as invalid, since we never want to recognize an instruction which uses + a field of this type. */ +static uint64_t +insert_nsi32 (uint64_t insn, + int64_t value, + ppc_cpu_t dialect, + const char **errmsg) +{ + return insert_si32 (insn, -value, dialect, errmsg); +} + +static int64_t +extract_nsi32 (uint64_t insn, + ppc_cpu_t dialect, + int *invalid) +{ + int64_t value = extract_si32 (insn, dialect, invalid); + *invalid = 1; + return -value; +} + /* The R field in an 8-byte prefix instruction when there are restrictions between R's value and the RA value (ie, they cannot both be non zero). */ @@ -3073,8 +3119,18 @@ const struct powerpc_operand powerpc_operands[] = { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_nsi34, extract_nsi34, PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, + /* The 32bit SI field in an 8-byte D form prefix instruction. */ +#define SI32 NSI34 + 1 + { UINT64_C(0xffffffff), PPC_OPSHIFT_INV, insert_si32, extract_si32, PPC_OPERAND_SIGNED }, + + /* The NSI field in an 8-byte D form prefix instruction with 32bit SI field. This is + the same as the SI32 field, only negated. */ +#define NSI32 SI32 + 1 + { UINT64_C(0xffffffff), PPC_OPSHIFT_INV, insert_nsi32, extract_nsi32, + PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, + /* The IMM32 field in a vector splat immediate prefix instruction. */ -#define IMM32 NSI34 + 1 +#define IMM32 NSI32 + 1 { 0xffffffff, PPC_OPSHIFT_INV, insert_imm32, extract_imm32, 0}, /* The UIM field in a vector permute extended prefix instruction. */ @@ -3757,6 +3813,7 @@ const struct powerpc_operand powerpc_operands[] = #define R RMC + 1 #define MP R +#define UIMM1 R #define P1 R { 0x1, 16, NULL, NULL, 0 }, @@ -4031,9 +4088,15 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands); /* An 8-byte D form prefix instruction. */ #define P_D_MASK (((-1ULL << 50) & ~PCREL_MASK) | OP_MASK) +/* An 8-byte D form prefix instruction with 32bit SI field. */ +#define P_D_SI32_MASK (((-1ULL << 48) & ~PCREL_MASK) | OP_MASK) + /* The same as P_D_MASK, but with the RA and PCREL fields specified. */ #define P_DRAPCREL_MASK (P_D_MASK | PCREL_MASK | RA_MASK) +/* The same as P_D_SI32_MASK, but with the RA and PCREL fields specified. */ +#define P_DRAPCREL_SI32_MASK (P_D_SI32_MASK | PCREL_MASK | RA_MASK) + /* Mask for prefix X form instructions. */ #define P_X_MASK (PREFIX_MASK | X_MASK) #define P_XX1_MASK (PREFIX_MASK | XX1_MASK) @@ -4344,6 +4407,12 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands); /* A VX form instruction. */ #define VX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff)) +/* A VX form instruction with selector bit */ +#define VXSEL5(op, xop, sel) (VX(op, xop) | (((sel) & 0x1f) << 16)) +#define VXSEL4(op, xop, sel) (VX(op, xop) | (((sel) & 0xf) << 17)) +#define VXSEL3(op, xop, sel) (VX(op, xop) | (((sel) & 0x7) << 18)) +#define VXSEL2(op, xop, sel) (VX(op, xop) | (((sel) & 0x3) << 19)) + /* The mask for an VX form instruction. */ #define VX_MASK VX(0x3f, 0x7ff) @@ -4435,6 +4504,9 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands); /* A VX_MASK with a UIMM2 field. */ #define VXUIMM2_MASK (VX_MASK | (0x7 << 18)) +/* A VX_MASK with a UIMM1 field. */ +#define VXUIMM1_MASK (VX_MASK | (0xf << 17)) + /* A VX_MASK with a PS field. */ #define VXPS_MASK (VX_MASK & ~(0x1 << 9)) @@ -5150,6 +5222,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vucmprhn", VX (4, 3), VX_MASK, FUTURE, 0, {VD, VA, VB}}, {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vrlq", VX (4, 5), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, @@ -5243,6 +5316,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vucmprln", VX (4, 67), VX_MASK, FUTURE, 0, {VD, VA, VB}}, {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vrlqmi", VX (4, 69), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, @@ -5265,6 +5339,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vucmprhb", VX (4, 131), VX_MASK, FUTURE, 0, {VD, VA, VB}}, {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, @@ -5282,6 +5357,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"vucmprlb", VX (4, 195), VX_MASK, FUTURE, 0, {VD, VA, VB}}, {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, @@ -5297,6 +5373,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"vcmpuq", VX (4, 257), VXBF_MASK, POWER10, 0, {BF, VA, VB}}, {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vucmprhh", VX (4, 259), VX_MASK, FUTURE, 0, {VD, VA, VB}}, {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vslq", VX (4, 261), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, @@ -5315,6 +5392,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"vcmpsq", VX (4, 321), VXBF_MASK, POWER10, 0, {BF, VA, VB}}, {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vucmprlh", VX (4, 323), VX_MASK, FUTURE, 0, {VD, VA, VB}}, {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vrlqnm", VX (4, 325), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, @@ -5331,6 +5409,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vupkhsntob", VXSEL5 (4, 387,0), VXVA_MASK, FUTURE, 0, {VD, VB}}, +{"vupklsntob", VXSEL5 (4, 387,1), VXVA_MASK, FUTURE, 0, {VD, VB}}, +{"vupkint8tobf16", VXSEL4 (4, 387,1), VXUIMM1_MASK, FUTURE, 0, {VD, VB, UIMM1}}, +{"vupkint4tobf16", VXSEL3 (4, 387,2), VXUIMM2_MASK, FUTURE, 0, {VD, VB, UIMM2}}, +{"vupkint8tofp32", VXSEL3 (4, 387,3), VXUIMM2_MASK, FUTURE, 0, {VD, VB, UIMM2}}, +{"vupkint4tofp32", VXSEL2 (4, 387,2), VXUIMM3_MASK, FUTURE, 0, {VD, VB, UIMM3}}, {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, @@ -9863,6 +9947,9 @@ const struct powerpc_opcode prefix_opcodes[] = { {"pla", PMLS|OP(14), P_D_MASK, POWER10, EXT, {RT, D34, PRA0, PCREL1}}, {"paddi", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, RA0, SI34, PCREL}}, {"psubi", PMLS|OP(14), P_D_MASK, POWER10, EXT, {RT, RA0, NSI34, PCREL}}, +{"plis", PMLS|OP(15), P_DRAPCREL_SI32_MASK, FUTURE, EXT, {RT, SI32}}, +{"paddis", PMLS|OP(15), P_D_SI32_MASK, FUTURE, 0, {RT, RA0, SI32, PCREL}}, +{"psubis", PMLS|OP(15), P_D_SI32_MASK, FUTURE, EXT, {RT, RA0, NSI32, PCREL}}, {"xxsplti32dx", P8RR|VSOP(32,0), P_VSI_MASK, POWER10, 0, {XTS, IX, IMM32}}, {"xxspltidp", P8RR|VSOP(32,2), P_VS_MASK, POWER10, 0, {XTS, IMM32}}, {"xxspltiw", P8RR|VSOP(32,3), P_VS_MASK, POWER10, 0, {XTS, IMM32}}, |