diff options
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 384 |
1 files changed, 316 insertions, 68 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index d573ecc..0ae7342 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1356,6 +1356,12 @@ QLF3(X, X, S_D), \ } +/* e.g. LDTP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!. */ +#define QL_LDST_PAIR_X \ +{ \ + QLF3(X, X, S_D), \ +} + /* e.g. STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */ #define QL_LDST_PAIR_FP \ { \ @@ -1364,6 +1370,12 @@ QLF3(S_Q, S_Q, S_Q), \ } +/* e.g. LDTP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */ +#define QL_LDST_PAIR_S_Q \ +{ \ + QLF3(S_Q, S_Q, S_Q), \ +} + /* e.g. LD3 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */ #define QL_SIMD_LDST \ { \ @@ -1732,6 +1744,14 @@ { \ QLF3(S_D,P_Z,S_D), \ } +#define OP_SVE_DZH \ +{ \ + QLF3(S_D,P_Z,S_H), \ +} +#define OP_SVE_DZS \ +{ \ + QLF3(S_D,P_Z,S_S), \ +} #define OP_SVE_DZU \ { \ QLF3(S_D,P_Z,NIL), \ @@ -1792,6 +1812,18 @@ { \ QLF3(S_H,NIL,NIL), \ } +#define OP_SVE_HZD \ +{ \ + QLF3(S_H,P_Z,S_D), \ +} +#define OP_SVE_HZH \ +{ \ + QLF3(S_H,P_Z,S_H), \ +} +#define OP_SVE_HZS \ +{ \ + QLF3(S_H,P_Z,S_S), \ +} #define OP_SVE_HZU \ { \ QLF3(S_H,P_Z,NIL), \ @@ -1812,6 +1844,10 @@ { \ QLF3(S_Q,NIL,NIL), \ } +#define OP_SVE_QZQ \ +{ \ + QLF3(S_Q,P_Z,S_Q), \ +} #define OP_SVE_QZU \ { \ QLF3(S_Q,P_Z,NIL), \ @@ -1899,6 +1935,14 @@ { \ QLF3(S_S,NIL,NIL), \ } +#define OP_SVE_SZD \ +{ \ + QLF3(S_S,P_Z,S_D), \ +} +#define OP_SVE_SZH \ +{ \ + QLF3(S_S,P_Z,S_H), \ +} #define OP_SVE_SZS \ { \ QLF3(S_S,P_Z,S_S), \ @@ -2171,6 +2215,11 @@ QLF4(S_S,NIL,S_S,S_S), \ QLF4(S_D,NIL,S_D,S_D), \ } +#define OP_SVE_VUV_BH \ +{ \ + QLF3(S_B,NIL,S_B), \ + QLF3(S_H,NIL,S_H), \ +} #define OP_SVE_VUV_BHSD \ { \ QLF3(S_B,NIL,S_B), \ @@ -2263,6 +2312,10 @@ QLF3(S_S,S_S,S_S), \ QLF3(S_D,S_D,S_D), \ } +#define OP_SVE_BBQ \ +{ \ + QLF3(S_B, S_B, S_Q) \ +} #define OP_SVE_VVV_D \ { \ QLF3(S_D,S_D,S_D), \ @@ -2404,6 +2457,13 @@ QLF4(S_S,X,X,NIL), \ QLF4(S_D,X,X,NIL), \ } +#define OP_SVE_VZV_BHSD \ +{ \ + QLF3(S_B,P_Z,S_B), \ + QLF3(S_H,P_Z,S_H), \ + QLF3(S_S,P_Z,S_S), \ + QLF3(S_D,P_Z,S_D), \ +} #define OP_SVE_VZVD_BHS \ { \ QLF4(S_B,P_Z,S_B,S_D), \ @@ -2729,12 +2789,7 @@ QLF3(V_4S, V_8H, S_H), \ } -/* Opcode table. - - Any SVE or SVE2 feature must include AARCH64_FEATURE_{SVE|SVE2} in its - bitmask, even if this is implied by other selected feature bits. This - allows verify_constraints to identify SVE instructions when selecting an - error message for MOVPRFX constraint violations. */ +/* Opcode table. */ static const aarch64_feature_set aarch64_feature_v8 = AARCH64_FEATURE (V8); @@ -2750,6 +2805,10 @@ static const aarch64_feature_set aarch64_feature_lsfe = AARCH64_FEATURE (LSFE); static const aarch64_feature_set aarch64_feature_lse128 = AARCH64_FEATURES (2, LSE, LSE128); +static const aarch64_feature_set aarch64_feature_lsui = + AARCH64_FEATURE (LSUI); +static const aarch64_feature_set aarch64_feature_lsui_fp = + AARCH64_FEATURES (2, LSUI, FP); static const aarch64_feature_set aarch64_feature_lor = AARCH64_FEATURE (LOR); static const aarch64_feature_set aarch64_feature_rdma = @@ -2807,25 +2866,25 @@ static const aarch64_feature_set aarch64_feature_tme = static const aarch64_feature_set aarch64_feature_sve2 = AARCH64_FEATURE (SVE2); static const aarch64_feature_set aarch64_feature_sve2aes = - AARCH64_FEATURES (2, SVE2, SVE2_AES); + AARCH64_FEATURES (2, SVE_AES, SVE2_SSVE_AES); static const aarch64_feature_set aarch64_feature_sve2sha3 = - AARCH64_FEATURES (2, SVE2, SVE2_SHA3); + AARCH64_FEATURE (SVE2_SHA3); static const aarch64_feature_set aarch64_feature_sve2sm4 = - AARCH64_FEATURES (2, SVE2, SVE2_SM4); + AARCH64_FEATURE (SVE2_SM4); static const aarch64_feature_set aarch64_feature_sve2bitperm = - AARCH64_FEATURES (2, SVE2, SVE2_BITPERM); + AARCH64_FEATURE (SVE2_BITPERM); static const aarch64_feature_set aarch64_feature_sme = - AARCH64_FEATURES (2, SVE2, SME); + AARCH64_FEATURE (SME); static const aarch64_feature_set aarch64_feature_sme_f64f64 = - AARCH64_FEATURES (3, SVE2, SME, SME_F64F64); + AARCH64_FEATURE (SME_F64F64); static const aarch64_feature_set aarch64_feature_sme_i16i64 = - AARCH64_FEATURES (3, SVE2, SME, SME_I16I64); + AARCH64_FEATURE (SME_I16I64); static const aarch64_feature_set aarch64_feature_sme2 = - AARCH64_FEATURES (3, SVE2, SME, SME2); + AARCH64_FEATURE (SME2); static const aarch64_feature_set aarch64_feature_sme2_i16i64 = - AARCH64_FEATURES (2, SME2, SME_I16I64); + AARCH64_FEATURE (SME_I16I64); static const aarch64_feature_set aarch64_feature_sme2_f64f64 = - AARCH64_FEATURES (2, SME2, SME_F64F64); + AARCH64_FEATURE (SME_F64F64); static const aarch64_feature_set aarch64_feature_i8mm = AARCH64_FEATURE (I8MM); static const aarch64_feature_set aarch64_feature_i8mm_sve = @@ -2865,7 +2924,7 @@ static const aarch64_feature_set aarch64_feature_the = static const aarch64_feature_set aarch64_feature_d128_the = AARCH64_FEATURES (2, D128, THE); static const aarch64_feature_set aarch64_feature_sve_b16b16_sve2 = - AARCH64_FEATURES (2, SVE_B16B16, SVE2); + AARCH64_FEATURES (2, SVE_B16B16, SVE2_SME2); static const aarch64_feature_set aarch64_feature_sve_b16b16_sme2 = AARCH64_FEATURES (2, SVE_B16B16, SME2); static const aarch64_feature_set aarch64_feature_sme_b16b16 = @@ -2884,6 +2943,8 @@ static const aarch64_feature_set aarch64_feature_f8f16mm = AARCH64_FEATURE (F8F16MM); static const aarch64_feature_set aarch64_feature_f8f16mm_sve2 = AARCH64_FEATURES (2, SVE2, F8F16MM); +static const aarch64_feature_set aarch64_feature_sve_aes2 = + AARCH64_FEATURES (2, SVE_AES2, SVE2_SSVE_AES); static const aarch64_feature_set aarch64_feature_rcpc3 = AARCH64_FEATURE (RCPC3); static const aarch64_feature_set aarch64_feature_cpa = @@ -2895,7 +2956,7 @@ static const aarch64_feature_set aarch64_feature_faminmax = static const aarch64_feature_set aarch64_feature_faminmax_sve2 = AARCH64_FEATURES (2, FAMINMAX, SVE2); static const aarch64_feature_set aarch64_feature_faminmax_sme2 = - AARCH64_FEATURES (3, SVE2, FAMINMAX, SME2); + AARCH64_FEATURES (2, FAMINMAX, SME2); static const aarch64_feature_set aarch64_feature_fp8 = AARCH64_FEATURE (FP8); static const aarch64_feature_set aarch64_feature_fp8_sve2 = @@ -2923,25 +2984,31 @@ static const aarch64_feature_set aarch64_feature_fp8dot4 = static const aarch64_feature_set aarch64_feature_fp8dot2 = AARCH64_FEATURE (FP8DOT2); static const aarch64_feature_set aarch64_feature_fp8fma_sve = - AARCH64_FEATURES (2, FP8FMA_SVE, SVE); + AARCH64_FEATURE (FP8FMA_SVE); static const aarch64_feature_set aarch64_feature_fp8dot4_sve = - AARCH64_FEATURES (2, FP8DOT4_SVE, SVE); + AARCH64_FEATURE (FP8DOT4_SVE); static const aarch64_feature_set aarch64_feature_fp8dot2_sve = - AARCH64_FEATURES (2, FP8DOT2_SVE, SVE); + AARCH64_FEATURE (FP8DOT2_SVE); static const aarch64_feature_set aarch64_feature_sme_f8f32 = - AARCH64_FEATURES (2, SME_F8F32, SME2); + AARCH64_FEATURE (SME_F8F32); static const aarch64_feature_set aarch64_feature_sme_f8f16 = - AARCH64_FEATURES (2, SME_F8F16, SME2); + AARCH64_FEATURE (SME_F8F16); static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 = - AARCH64_FEATURES (2, SME_F16F16_F8F16, SME2); + AARCH64_FEATURE (SME_F16F16_F8F16); static const aarch64_feature_set aarch64_feature_sme_f16f16 = - AARCH64_FEATURES (2, SME_F16F16, SME2); + AARCH64_FEATURE (SME_F16F16); static const aarch64_feature_set aarch64_feature_sve2p1_sme = - AARCH64_FEATURES (2, SVE2p1_SME, SVE); + AARCH64_FEATURE (SVE2p1_SME); static const aarch64_feature_set aarch64_feature_sve2p1_sme2 = - AARCH64_FEATURES (2, SVE2p1_SME2, SVE); + AARCH64_FEATURE (SVE2p1_SME2); static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = - AARCH64_FEATURES (2, SVE2p1_SME2p1, SVE); + AARCH64_FEATURE (SVE2p1_SME2p1); +static const aarch64_feature_set aarch64_feature_sme2p2 = + AARCH64_FEATURE (SME2p2); +static const aarch64_feature_set aarch64_feature_sve_sme2p2 = + AARCH64_FEATURE (SVE_SME2p2); +static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = + AARCH64_FEATURE (SVE2p2_SME2p2); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2950,6 +3017,8 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = #define LSE &aarch64_feature_lse #define LSFE &aarch64_feature_lsfe #define LSE128 &aarch64_feature_lse128 +#define LSUI &aarch64_feature_lsui +#define LSUI_FP &aarch64_feature_lsui_fp #define LOR &aarch64_feature_lor #define RDMA &aarch64_feature_rdma #define FP_F16 &aarch64_feature_fp_f16 @@ -3017,6 +3086,7 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = #define F8F32MM_SVE2 &aarch64_feature_f8f32mm_sve2 #define F8F16MM &aarch64_feature_f8f16mm #define F8F16MM_SVE2 &aarch64_feature_f8f16mm_sve2 +#define SVE_AES2 &aarch64_feature_sve_aes2 #define RCPC3 &aarch64_feature_rcpc3 #define CPA &aarch64_feature_cpa #define CPA_SVE &aarch64_feature_cpa_sve @@ -3046,13 +3116,16 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = #define SVE2p1_SME &aarch64_feature_sve2p1_sme #define SVE2p1_SME2 &aarch64_feature_sve2p1_sme2 #define SVE2p1_SME2p1 &aarch64_feature_sve2p1_sme2p1 +#define SME2p2 &aarch64_feature_sme2p2 +#define SVE_SME2p2 &aarch64_feature_sve_sme2p2 +#define SVE2p2_SME2p2 &aarch64_feature_sve2p2_sme2p2 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define __FP_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define _SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,VERIFIER) \ { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, VERIFIER } #define _CRC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -3063,26 +3136,30 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = { NAME, OPCODE, MASK, CLASS, 0, LSFE, OPS, QUALS, FLAGS, 0, 0, NULL } #define _LSE128_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LSE128, OPS, QUALS, FLAGS, 0, 0, NULL } +#define _LSUI_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, LSUI, OPS, QUALS, FLAGS, 0, 0, NULL } +#define _LSUI_FP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, LSUI_FP, OPS, QUALS, FLAGS, 0, 0, NULL } #define _LOR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LOR, OPS, QUALS, FLAGS, 0, 0, NULL } #define RDMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, RDMA, OPS, QUALS, FLAGS, 0, 0, NULL } #define FF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define SF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define FPRCVT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, FPRCVT, OPS, QUALS, FLAGS, 0, 0, NULL } #define _SVE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, 0, TIED, NULL } #define _SVE_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \ - FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } + FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, CONSTRAINTS, TIED, NULL } #define PAUTH_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, PAUTH, OPS, QUALS, FLAGS, 0, 0, NULL } #define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define JSCVT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, JSCVT, OPS, QUALS, FLAGS, 0, 0, NULL } #define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -3094,7 +3171,7 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = #define AES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, AES, OPS, QUALS, FLAGS, 0, 0, NULL } #define SHA3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define SM4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, SM4, OPS, QUALS, FLAGS, 0, 0, NULL } #define FP16_V8_2A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -3110,30 +3187,30 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = #define PREDRES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL } #define CMPBR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, CMPBR, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, CMPBR, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, 0, TIED, NULL } #define SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2p1, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } #define SVE_F16F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, SVE_F16F32MM, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, SVE_F16F32MM, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } #define F8F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, F8F32MM, OPS, QUALS, FLAGS, 0, 0, NULL } #define F8F32MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, F8F32MM_SVE2, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, F8F32MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } #define F8F16MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, F8F16MM, OPS, QUALS, FLAGS, 0, 0, NULL } #define F8F16MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, F8F16MM_SVE2, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, F8F16MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } #define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ - FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } + FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, CONSTRAINTS, TIED, NULL } #define B16B16_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, B16B16_SVE2, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } @@ -3158,6 +3235,9 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = #define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } +#define SVE_AES2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE_AES2, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } #define SVE2SHA3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2_SHA3, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } @@ -3169,7 +3249,7 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + F_STRICT | F_INVALID_IMM_SYMS_2 | FLAGS, 0, TIED, NULL } #define SME_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME_F64F64, OPS, QUALS, \ F_STRICT | FLAGS, 0, TIED, NULL } @@ -3181,7 +3261,7 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } #define SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + F_STRICT | F_INVALID_IMM_SYMS_3 | FLAGS, 0, TIED, NULL } #define SME2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \ FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } @@ -3195,36 +3275,34 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } #define SVE_BFSCALE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE, OPS, QUALS, FLAGS, 0, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE, OPS, QUALS, FLAGS | F_STRICT, 0, TIED, NULL } #define SVE_BFSCALE_SME2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE_SME2, OPS, QUALS, FLAGS, 0, TIED, NULL } -#define BFLOAT16_SVE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE_SME2, OPS, QUALS, FLAGS | F_STRICT, 0, TIED, NULL } #define BFLOAT16_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS | F_STRICT, \ CONSTRAINTS, TIED, NULL } #define BFLOAT16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16, OPS, QUALS, FLAGS, 0, 0, NULL } #define INT8MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, I8MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, I8MM_SVE, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define INT8MATMUL_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, I8MM, OPS, QUALS, FLAGS, 0, 0, NULL } #define F64MATMUL_SVE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, 0, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS | F_STRICT, 0, TIED, NULL } #define F64MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define F32MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define V8R_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, ARMV8R, OPS, QUALS, FLAGS, 0, 0, NULL } #define XS_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, XS, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, XS, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define WFXT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, WFXT, OPS, QUALS, FLAGS, 0, 0, NULL } #define _LS64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LS64, OPS, QUALS, FLAGS, 0, 0, NULL } #define FLAGM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, FLAGM, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, FLAGM, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define MOPS_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS, CONSTRAINTS, VERIFIER) \ { NAME, OPCODE, MASK, CLASS, 0, MOPS, OPS, QUALS, FLAGS, CONSTRAINTS, \ 0, VERIFIER } @@ -3234,13 +3312,13 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = #define HBC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, HBC, OPS, QUALS, FLAGS, 0, 0, NULL } #define CSSC_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, cssc, 0, CSSC, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, cssc, 0, CSSC, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define CHK_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \ { NAME, OPCODE, MASK, ic_system, 0, CHK, OPS, QUALS, FLAGS, 0, 0, NULL } #define GCS_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \ { NAME, OPCODE, MASK, gcs, 0, GCS, OPS, QUALS, FLAGS, 0, 0, NULL } #define D128_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, ic_system, 0, D128, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, ic_system, 0, D128, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define THE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, the, 0, THE, OPS, QUALS, FLAGS, 0, 0, NULL } #define D128_THE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ @@ -3256,10 +3334,10 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = { NAME, OPCODE, MASK, asimdsame, 0, FAMINMAX, OPS, QUALS, FLAGS, 0, 0, NULL } #define FAMINMAX_SVE2_INSN(NAME,OPCODE,MASK,OPS,QUALS,CONSTRAINTS) \ { NAME, OPCODE, MASK, sve_size_hsd, 0, FAMINMAX_SVE2, OPS, QUALS, \ - 0 | F_STRICT, CONSTRAINTS, 2, NULL } + F_STRICT, CONSTRAINTS, 2, NULL } #define FAMINMAX_SME2_INSN(NAME,OPCODE,MASK,OPS,QUALS) \ { NAME, OPCODE, MASK, sme_size_22_hsd, 0, FAMINMAX_SME2, OPS, QUALS, \ - F_STRICT | 0, 0, 1, NULL } + F_STRICT, 0, 1, NULL } #define FP8_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, FP8, OPS, QUALS, FLAGS, 0, 0, NULL } #define FP8_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ @@ -3271,16 +3349,16 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = #define LUT_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, lut, 0, LUT, OPS, QUALS, FLAGS, 0, 0, NULL } #define LUT_SVE2_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS,CONSTRAINTS) \ - { NAME, OPCODE, MASK, lut, 0, LUT_SVE2, OPS, QUALS, \ - FLAGS, CONSTRAINTS, 0, NULL } + { NAME, OPCODE, MASK, sve_misc, 0, LUT_SVE2, OPS, QUALS, \ + FLAGS | F_STRICT, CONSTRAINTS, 0, NULL } #define BRBE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, ic_system, 0, BRBE, OPS, QUALS, FLAGS, 0, 0, NULL } #define LUTv2_SME2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LUTv2_SME2, OPS, QUALS, \ - FLAGS, 0, 0, NULL } + FLAGS | F_STRICT, 0, 0, NULL } #define LUTv2_SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LUTv2_SME2p1, OPS, QUALS, \ - FLAGS, 0, 0, NULL } + FLAGS | F_STRICT, 0, 0, NULL } #define FP8FMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, FP8FMA, OPS, QUALS, FLAGS, 0, 0, NULL } #define FP8DOT4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -3310,7 +3388,7 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } #define SVE2p1_SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + F_STRICT | F_INVALID_IMM_SYMS_2 | FLAGS, 0, TIED, NULL } #define SVE2p1_SME2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2, OPS, QUALS, \ F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } @@ -3319,7 +3397,16 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = F_STRICT | FLAGS, 0, TIED, NULL } #define SVE2p1_SME2p1_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2p1, OPS, QUALS, \ + F_STRICT | F_INVALID_IMM_SYMS_2 | FLAGS, CONSTRAINTS, TIED, NULL } +#define SVE_SME2p2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE_SME2p2, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } +#define SVE2p2_SME2p2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, SVE2p2_SME2p2, OPS, QUALS, \ F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } +#define SME2p2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, SME2p2, OPS, QUALS, \ + F_STRICT | FLAGS, 0, TIED, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -4704,6 +4791,55 @@ const struct aarch64_opcode aarch64_opcode_table[] = _LSE128_INSN ("swppa", 0x19a08000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), _LSE128_INSN ("swppal", 0x19e08000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), _LSE128_INSN ("swppl", 0x19608000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + + /* LSUI extension */ + _LSUI_INSN ("ldtxr", 0x895f7c00, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), + _LSUI_INSN ("ldatxr", 0x895ffc00, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), + _LSUI_INSN ("sttxr", 0x89007c00, 0xbfe0fc00, ldstexcl, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q), + _LSUI_INSN ("stltxr", 0x8900fc00, 0xbfe0fc00, ldstexcl, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q), + _LSUI_INSN ("cast", 0xc9807c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + _LSUI_INSN ("casat", 0xc9c07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + _LSUI_INSN ("casalt", 0xc9c0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + _LSUI_INSN ("caslt", 0xc980fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + _LSUI_INSN ("caspt", 0x49807c00, 0xffe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_X4NIL, 0), + _LSUI_INSN ("caspat", 0x49c07c00, 0xffe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_X4NIL, 0), + _LSUI_INSN ("caspalt", 0x49c0fc00, 0xffe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_X4NIL, 0), + _LSUI_INSN ("casplt", 0x4980fc00, 0xffe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_X4NIL, 0), + _LSUI_INSN ("swpt", 0x19208400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), + _LSUI_INSN ("swpta", 0x19a08400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), + _LSUI_INSN ("swptal", 0x19e08400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), + _LSUI_INSN ("swptl", 0x19608400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), + _LSUI_INSN ("ldtadd", 0x19200400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), + _LSUI_INSN ("sttadd", 0x1920041f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), + _LSUI_INSN ("ldtadda", 0x19a00400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), + _LSUI_INSN ("ldtaddal", 0x19e00400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), + _LSUI_INSN ("ldtaddl", 0x19600400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), + _LSUI_INSN ("sttaddl", 0x1960041f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), + _LSUI_INSN ("ldtclr", 0x19201400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), + _LSUI_INSN ("sttclr", 0x1920141f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), + _LSUI_INSN ("ldtclra", 0x19a01400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), + _LSUI_INSN ("ldtclral", 0x19e01400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), + _LSUI_INSN ("ldtclrl", 0x19601400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), + _LSUI_INSN ("sttclrl", 0x1960141f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), + _LSUI_INSN ("ldtset", 0x19203400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), + _LSUI_INSN ("sttset", 0x1920341f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), + _LSUI_INSN ("ldtseta", 0x19a03400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), + _LSUI_INSN ("ldtsetal", 0x19e03400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), + _LSUI_INSN ("ldtsetl", 0x19603400, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), + _LSUI_INSN ("sttsetl", 0x1960341f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), + _LSUI_INSN ("ldtnp", 0xe8400000, 0xffc00000, ldstnapair_offs, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X, F_LDST_LOAD), + _LSUI_FP_INSN ("ldtnp", 0xec400000, 0xffc00000, ldstnapair_offs, OP3 (Fd, Fa, ADDR_SIMM7), QL_LDST_PAIR_S_Q, F_LDST_LOAD), + _LSUI_INSN ("sttnp", 0xe8000000, 0xffc00000, ldstnapair_offs, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X, F_LDST_STORE), + _LSUI_FP_INSN ("sttnp", 0xec000000, 0xffc00000, ldstnapair_offs, OP3 (Fd, Fa, ADDR_SIMM7), QL_LDST_PAIR_S_Q, F_LDST_STORE), + _LSUI_INSN ("ldtp", 0xe9400000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X, F_LDST_LOAD), + _LSUI_FP_INSN ("ldtp", 0xed400000, 0xffc00000, ldstpair_off, OP3 (Fd, Fa, ADDR_SIMM7), QL_LDST_PAIR_S_Q, F_LDST_LOAD), + _LSUI_INSN ("sttp", 0xe9000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X, F_LDST_STORE), + _LSUI_FP_INSN ("sttp", 0xed000000, 0xffc00000, ldstpair_off, OP3 (Fd, Fa, ADDR_SIMM7), QL_LDST_PAIR_S_Q, F_LDST_STORE), + _LSUI_INSN ("ldtp", 0xe8c00000, 0xfec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X, F_LDST_LOAD), + _LSUI_FP_INSN ("ldtp", 0xecc00000, 0xfec00000, ldstpair_indexed, OP3 (Fd, Fa, ADDR_SIMM7), QL_LDST_PAIR_S_Q, F_LDST_LOAD), + _LSUI_INSN ("sttp", 0xe8800000, 0xfec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X, F_LDST_STORE), + _LSUI_FP_INSN ("sttp", 0xec800000, 0xfec00000, ldstpair_indexed, OP3 (Fd, Fa, ADDR_SIMM7), QL_LDST_PAIR_S_Q, F_LDST_STORE), + /* RCPC3 extension. */ RCPC3_INSN ("ldiapp", 0x19400800, 0x3fe0ec00, rcpc3, OP3 (Rt, Rs, RCPC3_ADDR_OPT_POSTIND), QL_R2NIL, F_RCPC3_SIZE), RCPC3_INSN ("stilp", 0x19000800, 0x3fe0ec00, rcpc3, OP3 (Rt, Rs, RCPC3_ADDR_OPT_PREIND_WB), QL_R2NIL, F_RCPC3_SIZE), @@ -4747,6 +4883,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME_INSN ("smstop", 0xd503407f, 0xfffff1ff, sme_stop, 0, OP1 (SME_SM_ZA), {}, F_SYS_WRITE, 0), /* System. */ CHK_INSN ("chkfeat", 0xd503251f, 0xffffffff, OP1 (X16), QL_I1X, 0), + CORE_INSN ("stshh", 0xd503261f, 0xffffffdf, ic_system, 0, OP1 (STSHH_POLICY), {}, F_ALIAS), CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, 0, OP2 (PSTATEFIELD, UIMM4), {}, F_SYS_WRITE), CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS), CORE_INSN ("nop", 0xd503201f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), @@ -4940,7 +5077,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = _SVE_INSN ("cnth", 0x0460e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), _SVE_INSN ("cntp", 0x25208000, 0xff3fc200, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_10, SVE_Pn), OP_SVE_XUV_BHSD, 0, 0), _SVE_INSN ("cntw", 0x04a0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), - _SVE_INSN ("compact", 0x05a18000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0), + SVE_SME2p2_INSN ("compact", 0x05a18000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0), _SVE_INSNC ("cpy", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0), _SVE_INSNC ("cpy", 0x0528a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, Rn_SP), OP_SVE_VMR_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0), _SVE_INSNC ("cpy", 0x05100000, 0xff308000, sve_cpy, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_ASIMM), OP_SVE_VPU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0), @@ -5928,6 +6065,17 @@ const struct aarch64_opcode aarch64_opcode_table[] = SVE2BITPERM_INSN ("bdep", 0x4500b400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), SVE2BITPERM_INSN ("bext", 0x4500b000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), SVE2BITPERM_INSN ("bgrp", 0x4500b800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), + /* SVE_AES2 instructions */ + SVE_AES2_INSN ("aesdimc", 0x4523ec00, 0xffe7fc01, sve_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1), + SVE_AES2_INSN ("aesdimc", 0x4527ec00, 0xffe7fc03, sve_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1), + SVE_AES2_INSN ("aesd", 0x4522ec00, 0xffe7fc01, sve_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1), + SVE_AES2_INSN ("aesd", 0x4526ec00, 0xffe7fc03, sve_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1), + SVE_AES2_INSN ("aesemc", 0x4523e800, 0xffe7fc01, sve_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1), + SVE_AES2_INSN ("aesemc", 0x4527e800, 0xffe7fc03, sve_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1), + SVE_AES2_INSN ("aese", 0x4522e800, 0xffe7fc01, sve_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1), + SVE_AES2_INSN ("aese", 0x4526e800, 0xffe7fc03, sve_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1), + SVE_AES2_INSN ("pmlal", 0x4520fc00, 0xffe0fc01, sve_misc, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_Q_D, 0, 0), + SVE_AES2_INSN ("pmull", 0x4520f800, 0xffe0fc01, sve_misc, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_Q_D, 0, 0), /* SME instructions. */ SME_INSN ("addha", 0xc0900000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_SMMS, 0, 0), SME_I16I64_INSN ("addha", 0xc0d00000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_DMMD, 0, 0), @@ -7233,6 +7381,102 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME_F8F32_INSNC ("fvdotb", 0xc1d00800, 0xfff09830, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2_3), OP_SVE_VVV_S_B, F_OD (4) | F_VG_REQ, 0), SME_F8F32_INSNC ("fvdott", 0xc1d00810, 0xfff09830, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2_3), OP_SVE_VVV_S_B, F_OD (4) | F_VG_REQ, 0), + /* SVE2p2 / SME2p2 instructions. */ + SVE2p2_SME2p2_INSN ("abs", 0x0406a000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("bfcvt", 0x649ac000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("bfcvtnt", 0x6482a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("cls", 0x0408a000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("clz", 0x0409a000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("cnot", 0x040ba000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("cnt", 0x040aa000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("compact", 0x05218000, 0xffbfe000, sve_size_bh, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BH, 0, 0, 0), + SVE2p2_SME2p2_INSN ("expand", 0x05318000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fabs", 0x040ca000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvt", 0x649aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZH, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvt", 0x64daa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZH, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvt", 0x649a8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvt", 0x64dae000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvt", 0x64da8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvt", 0x64dac000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtlt", 0x6481a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZH, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtlt", 0x64c3a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtnt", 0x6480a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtnt", 0x64c2a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtx", 0x641ac000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtxnt", 0x6402a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtzs", 0x645ec000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZH, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtzs", 0x645f8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZH, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtzs", 0x645fc000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZH, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtzs", 0x649f8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtzs", 0x64df8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtzs", 0x64de8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtzs", 0x64dfc000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtzu", 0x645ee000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZH, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtzu", 0x645fa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZH, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtzu", 0x645fe000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZH, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtzu", 0x649fa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtzu", 0x64dfa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtzu", 0x64dea000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fcvtzu", 0x64dfe000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("firstp", 0x25218000, 0xff3fc200, sve_size_bhsd, OP3 (Rd, SVE_Pg4_10, SVE_Pn), OP_SVE_XUV_BHSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("flogb", 0x641e8000, 0xffff8000, sve_size_hsd3, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fneg", 0x040da000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("frecpx", 0x641b8000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("frint32x", 0x6511a000, 0xfffde000, sve_size_sd3, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0), + SVE2p2_SME2p2_INSN ("frint32x", 0x641ca000, 0xffffa000, sve_size_sd4, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_SD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("frint32z", 0x6510a000, 0xfffde000, sve_size_sd3, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0), + SVE2p2_SME2p2_INSN ("frint32z", 0x641c8000, 0xffffa000, sve_size_sd4, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_SD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("frint64x", 0x6515a000, 0xfffde000, sve_size_sd3, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0), + SVE2p2_SME2p2_INSN ("frint64x", 0x641da000, 0xffffa000, sve_size_sd4, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_SD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("frint64z", 0x6514a000, 0xfffde000, sve_size_sd3, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0), + SVE2p2_SME2p2_INSN ("frint64z", 0x641d8000, 0xffffa000, sve_size_sd4, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_SD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("frintx", 0x6419c000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("frinti", 0x6419e000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("frinta", 0x64198000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("frintn", 0x64188000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("frintz", 0x6418e000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("frintm", 0x6418c000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("frintp", 0x6418a000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("fsqrt", 0x641ba000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("lastp", 0x25228000, 0xff3fc200, sve_size_bhsd, OP3 (Rd, SVE_Pg4_10, SVE_Pn), OP_SVE_XUV_BHSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("neg", 0x0407a000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("not", 0x040ea000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("rbit", 0x0527a000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("revb", 0x0524a000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("revh", 0x05a5a000, 0xffbfe000, sve_size_sd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_SD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("revw", 0x05e6a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("revd", 0x052ea000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QZQ, 0, 0, 0), + SVE2p2_SME2p2_INSN ("scvtf", 0x645cc000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZH, 0, 0, 0), + SVE2p2_SME2p2_INSN ("scvtf", 0x645d8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("scvtf", 0x649d8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("scvtf", 0x64dc8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("scvtf", 0x645dc000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("scvtf", 0x64dd8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("scvtf", 0x64ddc000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("sqabs", 0x440aa000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("sqneg", 0x440ba000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("sxtb", 0x0400a000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("sxth", 0x0482a000, 0xffbfe000, sve_size_sd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_SD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("sxtw", 0x04c4a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("ucvtf", 0x645ce000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZH, 0, 0, 0), + SVE2p2_SME2p2_INSN ("ucvtf", 0x645da000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("ucvtf", 0x649da000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("ucvtf", 0x64dca000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("ucvtf", 0x645de000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("ucvtf", 0x64dda000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("ucvtf", 0x64dde000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("urecpe", 0x4482a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("ursqrte", 0x4483a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZS, 0, 0, 0), + SVE2p2_SME2p2_INSN ("uxtb", 0x0401a000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("uxth", 0x0483a000, 0xffbfe000, sve_size_sd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_SD, 0, 0, 0), + SVE2p2_SME2p2_INSN ("uxtw", 0x04c5a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZD, 0, 0, 0), + + /* SME2p2 instructions. */ + SME2p2_INSN ("fmul", 0xc120e800, 0xff21fc21, sme_size_22_hsd, OP3 (SME_Zdnx2, SME_Znx2, SME_Zm_17), OP_SVE_VVV_HSD, 0, 0), + SME2p2_INSN ("fmul", 0xc121e800, 0xff21fc63, sme_size_22_hsd, OP3 (SME_Zdnx4, SME_Znx4, SME_Zm_17), OP_SVE_VVV_HSD, 0, 0), + SME2p2_INSN ("fmul", 0xc120e400, 0xff21fc21, sme_size_22_hsd, OP3 (SME_Zdnx2, SME_Znx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 0), + SME2p2_INSN ("fmul", 0xc121e400, 0xff21fc63, sme_size_22_hsd, OP3 (SME_Zdnx4, SME_Znx4, SME_Zmx4), OP_SVE_VVV_HSD, 0, 0), + {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -7471,6 +7715,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = "the GCSB option name DSYNC") \ Y(SYSTEM, hint, "BTI_TARGET", 0, F (), \ "BTI targets j/c/jc") \ + Y(SYSTEM, hint, "STSHH_POLICY", 0, F(), \ + "an STSHH policy (keep/strm)") \ Y(SYSTEM, imm, "BRBOP", 0, F(FLD_brbop), \ "Branch Record Buffer operation operand") \ Y(INT_REG, regno, "Rt_IN_SYS_ALIASES", 0, F(FLD_Rt), \ @@ -7903,6 +8149,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = F(FLD_SVE_Zn, FLD_imm2_15), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX2_16", 0, \ F(FLD_SVE_Zn, FLD_imm2_16), "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zn_INDEX2_19", 0, \ + F(FLD_SVE_Zn, FLD_imm2_19), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX3_14", 0, \ F(FLD_SVE_Zn, FLD_imm3_14), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX3_15", 0, \ @@ -7951,7 +8199,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a register destination address with writeback") \ Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rs", 0, F(FLD_Rs), \ "a register source address with writeback") \ - Y(INT_REG, x0_to_x30, "MOPS_WB_Rd", 0, F(FLD_Rn), \ + Y(INT_REG, x0_to_x30, "MOPS_WB_Rn", 0, F(FLD_Rn), \ "an integer register with writeback") \ Y(IMMEDIATE, imm, "CSSC_SIMM8", OPD_F_SEXT, F(FLD_CSSC_imm8), \ "an 8-bit signed immediate") \ |