diff options
Diffstat (limited to 'opcodes/aarch64-opc-2.c')
| -rw-r--r-- | opcodes/aarch64-opc-2.c | 192 |
1 files changed, 102 insertions, 90 deletions
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 99294b3..c70824a 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -1,6 +1,6 @@ /* This file is automatically generated by aarch64-gen. Do not edit! */ /* Copyright (C) 2012-2025 Free Software Foundation, Inc. - Contributed by ARM Ltd. + Contributed by Arm Ltd. This file is part of the GNU opcodes library. @@ -19,6 +19,7 @@ see <http://www.gnu.org/licenses/>. */ #include "sysdep.h" +#include "aarch64-tbl-2.h" #include "aarch64-opc.h" @@ -90,6 +91,8 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_10}, "the width of the bit-field"}, {AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_10}, "an immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_15}, "an immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMMP1_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_15}, "an immediate plus 1"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS1_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_15}, "an immediate minus 1"}, {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op1}, "a 3-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op2}, "a 3-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit unsigned immediate"}, @@ -113,6 +116,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_COND, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a condition"}, {AARCH64_OPND_CLASS_COND, "COND1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "one of the standard conditions, excluding AL and NV."}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {FLD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page"}, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL9", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9_5}, "9-bit PC-relative address"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm14}, "14-bit PC-relative address"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm19}, "19-bit PC-relative address"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immhi,FLD_immlo}, "21-bit PC-relative address"}, @@ -146,6 +150,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB/TSB option name CSYNC"}, {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_GCSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the GCSB option name DSYNC"}, {AARCH64_OPND_CLASS_SYSTEM, "BTI_TARGET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "BTI targets j/c/jc"}, + {AARCH64_OPND_CLASS_SYSTEM, "STSHH_POLICY", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an STSHH policy (keep/strm)"}, {AARCH64_OPND_CLASS_SYSTEM, "BRBOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_brbop}, "Branch Record Buffer operation operand"}, {AARCH64_OPND_CLASS_INT_REG, "Rt_IN_SYS_ALIASES", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "Rt register with defaults for SYS aliases"}, {AARCH64_OPND_CLASS_INT_REG, "LSE128_Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_LSE128_Rt}, "an integer register"}, @@ -162,12 +167,16 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 2"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 4"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 8"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_R", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with an optional scalar register offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX", (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, @@ -274,6 +283,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm}, "an SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_17", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2}, "an SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm4}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"}, @@ -324,6 +334,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm1_16}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_15}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_16}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_19", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_19}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_14}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_15}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX4_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm4_14}, "an indexed SVE vector register"}, @@ -345,7 +356,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"}, {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "a register source address with writeback"}, - {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"}, + {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"}, {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit signed immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit unsigned immediate"}, {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_opc2}, "an address with post-incrementing by ammount of loaded bytes"}, @@ -356,97 +367,98 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, }; -/* Indexed by an enum aarch64_op enumerator, the value is the offset of - the corresponding aarch64_opcode entry in the aarch64_opcode_table. */ +/* Indexed by an enum aarch64_op enumerator, the value is the + offset of the corresponding aarch64_opcode entry in the + aarch64_opcode_table. */ -static const unsigned op_enum_table [] = +static const enum aarch64_opcode_idx op_enum_table [] = { - 0, - 889, - 890, - 891, - 894, - 895, - 896, - 897, - 898, - 892, - 893, - 899, - 900, - 922, - 923, - 924, - 927, - 928, - 929, - 930, - 931, - 925, - 926, - 932, - 933, - 987, - 988, - 989, - 990, - 12, - 636, - 637, - 1216, - 1218, - 1220, - 998, - 1219, - 1217, - 318, - 624, - 635, - 634, - 996, - 631, - 628, - 620, - 619, - 626, - 627, - 630, - 632, - 633, - 1006, - 664, - 667, - 670, - 665, - 668, - 825, - 178, - 179, - 180, - 181, - 516, - 759, - 389, - 391, - 413, - 415, - 1323, - 1324, - 1329, - 1321, - 1320, - 1325, - 1332, - 1334, - 1335, - 1331, - 1337, - 1336, - 131, + A64_OPID_1a000000_adc_Rd_Rn_Rm, + A64_OPID_39000000_strb_Rt_ADDR_UIMM12, + A64_OPID_39400000_ldrb_Rt_ADDR_UIMM12, + A64_OPID_39800000_ldrsb_Rt_ADDR_UIMM12, + A64_OPID_79000000_strh_Rt_ADDR_UIMM12, + A64_OPID_79400000_ldrh_Rt_ADDR_UIMM12, + A64_OPID_79800000_ldrsh_Rt_ADDR_UIMM12, + A64_OPID_b9000000_str_Rt_ADDR_UIMM12, + A64_OPID_b9400000_ldr_Rt_ADDR_UIMM12, + A64_OPID_3d000000_str_Ft_ADDR_UIMM12, + A64_OPID_3d400000_ldr_Ft_ADDR_UIMM12, + A64_OPID_b9800000_ldrsw_Rt_ADDR_UIMM12, + A64_OPID_f9800000_prfm_PRFOP_ADDR_UIMM12, + A64_OPID_38000000_sturb_Rt_ADDR_SIMM9, + A64_OPID_38400000_ldurb_Rt_ADDR_SIMM9, + A64_OPID_38800000_ldursb_Rt_ADDR_SIMM9, + A64_OPID_78000000_sturh_Rt_ADDR_SIMM9, + A64_OPID_78400000_ldurh_Rt_ADDR_SIMM9, + A64_OPID_78800000_ldursh_Rt_ADDR_SIMM9, + A64_OPID_b8000000_stur_Rt_ADDR_SIMM9, + A64_OPID_b8400000_ldur_Rt_ADDR_SIMM9, + A64_OPID_3c000000_stur_Ft_ADDR_SIMM9, + A64_OPID_3c400000_ldur_Ft_ADDR_SIMM9, + A64_OPID_b8800000_ldursw_Rt_ADDR_SIMM9, + A64_OPID_f8800000_prfum_PRFOP_ADDR_SIMM9, + A64_OPID_18000000_ldr_Rt_ADDR_PCREL19, + A64_OPID_1c000000_ldr_Ft_ADDR_PCREL19, + A64_OPID_98000000_ldrsw_Rt_ADDR_PCREL19, + A64_OPID_d8000000_prfm_PRFOP_ADDR_PCREL19, + A64_OPID_11000000_add_Rd_SP_Rn_SP_AIMM, + A64_OPID_14000000_b_ADDR_PCREL26, + A64_OPID_94000000_bl_ADDR_PCREL26, + A64_OPID_12800000_movn_Rd_HALF, + A64_OPID_52800000_movz_Rd_HALF, + A64_OPID_72800000_movk_Rd_HALF, + A64_OPID_320003e0_mov_Rd_SP_IMM_MOV, + A64_OPID_52800000_mov_Rd_IMM_MOV, + A64_OPID_12800000_mov_Rd_IMM_MOV, + A64_OPID_0ea01c00_mov_Vd_Vn, + A64_OPID_13000000_asr_Rd_Rn_IMM, + A64_OPID_53000000_lsr_Rd_Rn_IMM, + A64_OPID_53000000_lsl_Rd_Rn_IMM, + A64_OPID_12000000_bic_Rd_SP_Rn_LIMM, + A64_OPID_53000000_ubfx_Rd_Rn_IMM_WIDTH, + A64_OPID_33000000_bfxil_Rd_Rn_IMM_WIDTH, + A64_OPID_13000000_sbfx_Rd_Rn_IMM_WIDTH, + A64_OPID_13000000_sbfiz_Rd_Rn_IMM_WIDTH, + A64_OPID_33000000_bfi_Rd_Rn_IMM_WIDTH, + A64_OPID_330003e0_bfc_Rd_IMM_WIDTH, + A64_OPID_53000000_ubfiz_Rd_Rn_IMM_WIDTH, + A64_OPID_53001c00_uxtb_Rd_Rn, + A64_OPID_53003c00_uxth_Rd_Rn, + A64_OPID_2a0003e0_uxtw_Rd_Rm, + A64_OPID_1a800400_cinc_Rd_Rn_COND1, + A64_OPID_5a800000_cinv_Rd_Rn_COND1, + A64_OPID_5a800400_cneg_Rd_Rn_COND1, + A64_OPID_1a9f07e0_cset_Rd_COND1, + A64_OPID_5a9f03e0_csetm_Rd_COND1, + A64_OPID_1e224000_fcvt_Fd_Fn, + A64_OPID_0e216800_fcvtn_Vd_Vn, + A64_OPID_4e216800_fcvtn2_Vd_Vn, + A64_OPID_0e217800_fcvtl_Vd_Vn, + A64_OPID_4e217800_fcvtl2_Vd_Vn, + A64_OPID_7e216800_fcvtxn_Sd_Sn, + A64_OPID_13800000_ror_Rd_Rm_IMMS, + A64_OPID_0f00a400_sxtl_Vd_Vn, + A64_OPID_4f00a400_sxtl2_Vd_Vn, + A64_OPID_2f00a400_uxtl_Vd_Vn, + A64_OPID_6f00a400_uxtl2_Vd_Vn, + A64_OPID_25804000_mov_SVE_Pd_SVE_Pn, + A64_OPID_25804000_mov_SVE_PNd_SVE_PNn, + A64_OPID_0520c000_mov_SVE_Zd_SVE_Pg4_10_SVE_Zn, + A64_OPID_05202000_mov_SVE_Zd_SVE_VZn, + A64_OPID_04603000_mov_SVE_Zd_SVE_Zn, + A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX, + A64_OPID_25004210_mov_SVE_Pd_SVE_Pg4_10_SVE_Pn, + A64_OPID_25c04000_movs_SVE_Pd_SVE_Pn, + A64_OPID_25404000_movs_SVE_Pd_SVE_Pg4_10_SVE_Pn, + A64_OPID_25004000_mov_SVE_Pd_SVE_Pg4_10_SVE_Pn, + A64_OPID_25404200_nots_SVE_Pd_SVE_Pg4_10_SVE_Pn, + A64_OPID_25004200_not_SVE_Pd_SVE_Pg4_10_SVE_Pn, + A64_OPID_2f001000_fcmla_Vd_Vn_Em_IMM_ROT2, }; -/* Given the opcode enumerator OP, return the pointer to the corresponding - opcode entry. */ +/* Given the opcode enumerator OP, return the pointer to the + corresponding opcode entry. */ const aarch64_opcode * aarch64_get_opcode (enum aarch64_op op) |