diff options
Diffstat (limited to 'opcodes/aarch64-opc-2.c')
| -rw-r--r-- | opcodes/aarch64-opc-2.c | 180 |
1 files changed, 91 insertions, 89 deletions
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index f36222c..c70824a 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -1,6 +1,6 @@ /* This file is automatically generated by aarch64-gen. Do not edit! */ /* Copyright (C) 2012-2025 Free Software Foundation, Inc. - Contributed by ARM Ltd. + Contributed by Arm Ltd. This file is part of the GNU opcodes library. @@ -19,6 +19,7 @@ see <http://www.gnu.org/licenses/>. */ #include "sysdep.h" +#include "aarch64-tbl-2.h" #include "aarch64-opc.h" @@ -355,7 +356,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"}, {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "a register source address with writeback"}, - {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"}, + {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"}, {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit signed immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit unsigned immediate"}, {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_opc2}, "an address with post-incrementing by ammount of loaded bytes"}, @@ -366,97 +367,98 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, }; -/* Indexed by an enum aarch64_op enumerator, the value is the offset of - the corresponding aarch64_opcode entry in the aarch64_opcode_table. */ +/* Indexed by an enum aarch64_op enumerator, the value is the + offset of the corresponding aarch64_opcode entry in the + aarch64_opcode_table. */ -static const unsigned op_enum_table [] = +static const enum aarch64_opcode_idx op_enum_table [] = { - 0, - 941, - 942, - 943, - 946, - 947, - 948, - 949, - 950, - 944, - 945, - 951, - 952, - 974, - 975, - 976, - 979, - 980, - 981, - 982, - 983, - 977, - 978, - 984, - 985, - 1039, - 1040, - 1041, - 1042, - 12, - 636, - 637, - 1314, - 1316, - 1318, - 1050, - 1317, - 1315, - 318, - 624, - 635, - 634, - 1048, - 631, - 628, - 620, - 619, - 626, - 627, - 630, - 632, - 633, - 1058, - 704, - 707, - 710, - 705, - 708, - 877, - 178, - 179, - 180, - 181, - 516, - 799, - 389, - 391, - 413, - 415, - 1422, - 1423, - 1428, - 1420, - 1419, - 1424, - 1431, - 1433, - 1434, - 1430, - 1436, - 1435, - 131, + A64_OPID_1a000000_adc_Rd_Rn_Rm, + A64_OPID_39000000_strb_Rt_ADDR_UIMM12, + A64_OPID_39400000_ldrb_Rt_ADDR_UIMM12, + A64_OPID_39800000_ldrsb_Rt_ADDR_UIMM12, + A64_OPID_79000000_strh_Rt_ADDR_UIMM12, + A64_OPID_79400000_ldrh_Rt_ADDR_UIMM12, + A64_OPID_79800000_ldrsh_Rt_ADDR_UIMM12, + A64_OPID_b9000000_str_Rt_ADDR_UIMM12, + A64_OPID_b9400000_ldr_Rt_ADDR_UIMM12, + A64_OPID_3d000000_str_Ft_ADDR_UIMM12, + A64_OPID_3d400000_ldr_Ft_ADDR_UIMM12, + A64_OPID_b9800000_ldrsw_Rt_ADDR_UIMM12, + A64_OPID_f9800000_prfm_PRFOP_ADDR_UIMM12, + A64_OPID_38000000_sturb_Rt_ADDR_SIMM9, + A64_OPID_38400000_ldurb_Rt_ADDR_SIMM9, + A64_OPID_38800000_ldursb_Rt_ADDR_SIMM9, + A64_OPID_78000000_sturh_Rt_ADDR_SIMM9, + A64_OPID_78400000_ldurh_Rt_ADDR_SIMM9, + A64_OPID_78800000_ldursh_Rt_ADDR_SIMM9, + A64_OPID_b8000000_stur_Rt_ADDR_SIMM9, + A64_OPID_b8400000_ldur_Rt_ADDR_SIMM9, + A64_OPID_3c000000_stur_Ft_ADDR_SIMM9, + A64_OPID_3c400000_ldur_Ft_ADDR_SIMM9, + A64_OPID_b8800000_ldursw_Rt_ADDR_SIMM9, + A64_OPID_f8800000_prfum_PRFOP_ADDR_SIMM9, + A64_OPID_18000000_ldr_Rt_ADDR_PCREL19, + A64_OPID_1c000000_ldr_Ft_ADDR_PCREL19, + A64_OPID_98000000_ldrsw_Rt_ADDR_PCREL19, + A64_OPID_d8000000_prfm_PRFOP_ADDR_PCREL19, + A64_OPID_11000000_add_Rd_SP_Rn_SP_AIMM, + A64_OPID_14000000_b_ADDR_PCREL26, + A64_OPID_94000000_bl_ADDR_PCREL26, + A64_OPID_12800000_movn_Rd_HALF, + A64_OPID_52800000_movz_Rd_HALF, + A64_OPID_72800000_movk_Rd_HALF, + A64_OPID_320003e0_mov_Rd_SP_IMM_MOV, + A64_OPID_52800000_mov_Rd_IMM_MOV, + A64_OPID_12800000_mov_Rd_IMM_MOV, + A64_OPID_0ea01c00_mov_Vd_Vn, + A64_OPID_13000000_asr_Rd_Rn_IMM, + A64_OPID_53000000_lsr_Rd_Rn_IMM, + A64_OPID_53000000_lsl_Rd_Rn_IMM, + A64_OPID_12000000_bic_Rd_SP_Rn_LIMM, + A64_OPID_53000000_ubfx_Rd_Rn_IMM_WIDTH, + A64_OPID_33000000_bfxil_Rd_Rn_IMM_WIDTH, + A64_OPID_13000000_sbfx_Rd_Rn_IMM_WIDTH, + A64_OPID_13000000_sbfiz_Rd_Rn_IMM_WIDTH, + A64_OPID_33000000_bfi_Rd_Rn_IMM_WIDTH, + A64_OPID_330003e0_bfc_Rd_IMM_WIDTH, + A64_OPID_53000000_ubfiz_Rd_Rn_IMM_WIDTH, + A64_OPID_53001c00_uxtb_Rd_Rn, + A64_OPID_53003c00_uxth_Rd_Rn, + A64_OPID_2a0003e0_uxtw_Rd_Rm, + A64_OPID_1a800400_cinc_Rd_Rn_COND1, + A64_OPID_5a800000_cinv_Rd_Rn_COND1, + A64_OPID_5a800400_cneg_Rd_Rn_COND1, + A64_OPID_1a9f07e0_cset_Rd_COND1, + A64_OPID_5a9f03e0_csetm_Rd_COND1, + A64_OPID_1e224000_fcvt_Fd_Fn, + A64_OPID_0e216800_fcvtn_Vd_Vn, + A64_OPID_4e216800_fcvtn2_Vd_Vn, + A64_OPID_0e217800_fcvtl_Vd_Vn, + A64_OPID_4e217800_fcvtl2_Vd_Vn, + A64_OPID_7e216800_fcvtxn_Sd_Sn, + A64_OPID_13800000_ror_Rd_Rm_IMMS, + A64_OPID_0f00a400_sxtl_Vd_Vn, + A64_OPID_4f00a400_sxtl2_Vd_Vn, + A64_OPID_2f00a400_uxtl_Vd_Vn, + A64_OPID_6f00a400_uxtl2_Vd_Vn, + A64_OPID_25804000_mov_SVE_Pd_SVE_Pn, + A64_OPID_25804000_mov_SVE_PNd_SVE_PNn, + A64_OPID_0520c000_mov_SVE_Zd_SVE_Pg4_10_SVE_Zn, + A64_OPID_05202000_mov_SVE_Zd_SVE_VZn, + A64_OPID_04603000_mov_SVE_Zd_SVE_Zn, + A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX, + A64_OPID_25004210_mov_SVE_Pd_SVE_Pg4_10_SVE_Pn, + A64_OPID_25c04000_movs_SVE_Pd_SVE_Pn, + A64_OPID_25404000_movs_SVE_Pd_SVE_Pg4_10_SVE_Pn, + A64_OPID_25004000_mov_SVE_Pd_SVE_Pg4_10_SVE_Pn, + A64_OPID_25404200_nots_SVE_Pd_SVE_Pg4_10_SVE_Pn, + A64_OPID_25004200_not_SVE_Pd_SVE_Pg4_10_SVE_Pn, + A64_OPID_2f001000_fcmla_Vd_Vn_Em_IMM_ROT2, }; -/* Given the opcode enumerator OP, return the pointer to the corresponding - opcode entry. */ +/* Given the opcode enumerator OP, return the pointer to the + corresponding opcode entry. */ const aarch64_opcode * aarch64_get_opcode (enum aarch64_op op) |