diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/elf/aarch64.h | 2 | ||||
| -rw-r--r-- | include/elf/common.h | 1 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 43 | ||||
| -rw-r--r-- | include/sframe-api.h | 20 | ||||
| -rw-r--r-- | include/sframe.h | 59 |
5 files changed, 111 insertions, 14 deletions
diff --git a/include/elf/aarch64.h b/include/elf/aarch64.h index e218e07..74bd7b4 100644 --- a/include/elf/aarch64.h +++ b/include/elf/aarch64.h @@ -52,6 +52,8 @@ #define DT_AARCH64_BTI_PLT (DT_LOPROC + 1) #define DT_AARCH64_PAC_PLT (DT_LOPROC + 3) #define DT_AARCH64_VARIANT_PCS (DT_LOPROC + 5) +#define DT_AARCH64_MEMTAG_MODE (DT_LOPROC + 9) +#define DT_AARCH64_MEMTAG_STACK (DT_LOPROC + 12) /* AArch64-specific values for st_other. */ #define STO_AARCH64_VARIANT_PCS 0x80 /* Symbol may follow different call diff --git a/include/elf/common.h b/include/elf/common.h index f395278..0d9a7b7 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -568,6 +568,7 @@ #define SHT_ANDROID_RELR 0x6fffff00 +#define SHT_GNU_SFRAME 0x6ffffff4 /* SFrame stack trace information. */ #define SHT_GNU_ATTRIBUTES 0x6ffffff5 /* Object attributes */ #define SHT_GNU_HASH 0x6ffffff6 /* GNU style symbol hash table */ #define SHT_GNU_LIBLIST 0x6ffffff7 /* List of prelink dependencies */ diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index dab6eac..4425dd4 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -187,6 +187,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_THE, /* LSE128. */ AARCH64_FEATURE_LSE128, + /* LSUI - Unprivileged Load Store. */ + AARCH64_FEATURE_LSUI, /* ARMv8.9-A RAS Extensions. */ AARCH64_FEATURE_RASv2, /* Delegated SError exceptions for EL3. */ @@ -242,6 +244,12 @@ enum aarch64_feature_bit { AARCH64_FEATURE_F8F32MM, /* F8F16MM instructions. */ AARCH64_FEATURE_F8F16MM, + /* SVE_PMULL128 extension. */ + AARCH64_FEATURE_SVE_AES, + /* SVE AES2 instructions. */ + AARCH64_FEATURE_SVE_AES2, + /* SSVE_AES extension. */ + AARCH64_FEATURE_SSVE_AES, /* RCPC3 instructions. */ AARCH64_FEATURE_RCPC3, /* Enhanced Software Step Extension. */ @@ -296,6 +304,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_V9_4A, /* Armv9.5-A processors. */ AARCH64_FEATURE_V9_5A, + /* Armv9.6-A processors. */ + AARCH64_FEATURE_V9_6A, /* FPRCVT instructions. */ AARCH64_FEATURE_FPRCVT, /* Point of Physical Storage. */ @@ -303,6 +313,8 @@ enum aarch64_feature_bit { /* Virtual features. These are used to gate instructions that are enabled by either of two (or more) sets of command line flags. */ + /* +sve2 or +ssve-aes */ + AARCH64_FEATURE_SVE2_SSVE_AES, /* +fp8fma+sve or +ssve-fp8fma */ AARCH64_FEATURE_FP8FMA_SVE, /* +fp8dot4+sve or +ssve-fp8dot4 */ @@ -463,6 +475,12 @@ static_assert ((AA64_REPLICATE (REP_PLUS, AA64_REPVAL, | AARCH64_FEATBIT (X, SPMU2) \ | AARCH64_FEATBIT (X, STEP2) \ ) +#define AARCH64_ARCH_V9_6A_FEATURES(X) (AARCH64_FEATBIT (X, V9_6A) \ + | AARCH64_FEATBIT (X, CMPBR) \ + | AARCH64_FEATBIT (X, FPRCVT) \ + | AARCH64_FEATBIT (X, LSUI) \ + | AARCH64_FEATBIT (X, OCCMO) \ + | AARCH64_FEATBIT (X, SVE2p2)) /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8A(X) (AARCH64_FEATBIT (X, V8) \ @@ -502,6 +520,8 @@ static_assert ((AA64_REPLICATE (REP_PLUS, AA64_REPVAL, | AARCH64_ARCH_V9_4A_FEATURES (X)) #define AARCH64_ARCH_V9_5A(X) (AARCH64_ARCH_V9_4A (X) \ | AARCH64_ARCH_V9_5A_FEATURES (X)) +#define AARCH64_ARCH_V9_6A(X) (AARCH64_ARCH_V9_5A (X) \ + | AARCH64_ARCH_V9_6A_FEATURES (X)) #define AARCH64_ARCH_NONE(X) 0 @@ -783,6 +803,7 @@ enum aarch64_opnd AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ AARCH64_OPND_BARRIER_GCSB, /* Barrier operand for GCSB. */ AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */ + AARCH64_OPND_STSHH_POLICY, /* STSHH {<policy>}. */ AARCH64_OPND_BRBOP, /* BRB operation IALL or INJ in bit 5. */ AARCH64_OPND_Rt_IN_SYS_ALIASES, /* Defaulted and omitted Rt used in SYS aliases such as brb. */ AARCH64_OPND_LSE128_Rt, /* LSE128 <Xt1>. */ @@ -974,6 +995,7 @@ enum aarch64_opnd AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */ AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */ AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */ + AARCH64_OPND_SME_Zn_INDEX2_19, /* Zn[index], bits [9:5] and [20:19]. */ AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */ AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */ AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */ @@ -1529,7 +1551,24 @@ extern const aarch64_opcode aarch64_opcode_table[]; /* For LSFE instructions with size[30:31] field. */ #define F_LSFE_SZ (1ULL << 41) -/* Next bit is 42. */ + +/* When parsing immediate values, register names should not be misinterpreted + as symbols. However, for backwards compatibility we need to permit some + newer register names within older instructions. These flags specify which + register names are invalid immediate value, and are required for all + instructions with immediate operands (and are otherwise ignored). */ +#define F_INVALID_IMM_SYMS (3ULL << 42) + +/* Any GP or SIMD register except WSP/SP. */ +#define F_INVALID_IMM_SYMS_1 (1ULL << 42) + +/* As above, plus WSP/SP, and Z and P registers. */ +#define F_INVALID_IMM_SYMS_2 (2ULL << 42) + +/* As above, plus PN registers. */ +#define F_INVALID_IMM_SYMS_3 (3ULL << 42) + +/* Next bit is 44. */ /* Instruction constraints. */ /* This instruction has a predication constraint on the instruction at PC+4. */ @@ -1878,6 +1917,8 @@ struct aarch64_inst #define HINT_OPD_C 0x22 #define HINT_OPD_J 0x24 #define HINT_OPD_JC 0x26 +#define HINT_OPD_KEEP 0x30 +#define HINT_OPD_STRM 0x31 #define HINT_OPD_NULL 0x00 diff --git a/include/sframe-api.h b/include/sframe-api.h index 3dc18b6..8c26257 100644 --- a/include/sframe-api.h +++ b/include/sframe-api.h @@ -153,14 +153,6 @@ sframe_decoder_get_fixed_fp_offset (sframe_decoder_ctx *dctx); extern int8_t sframe_decoder_get_fixed_ra_offset (sframe_decoder_ctx *dctx); -/* Find the function descriptor entry which contains the specified address. - - Note: This function is deprecated and will be removed from future release - X+2 of the library. */ -extern void * -sframe_get_funcdesc_with_addr (sframe_decoder_ctx *dctx, int32_t addr, - int *errp); - /* Find the SFrame Frame Row Entry which contains the PC. Returns SFRAME_ERR if failure. */ @@ -214,12 +206,20 @@ extern int32_t sframe_fre_get_cfa_offset (sframe_decoder_ctx *dtcx, sframe_frame_row_entry *fre, int *errp); -/* Get the FP offset from the FRE. If the offset is invalid, sets errp. */ +/* Get the FP offset from the FRE. If the offset is invalid, sets errp. + + For s390x the offset may be an encoded register number, indicated by + LSB set to one, which is only valid in the topmost frame. */ extern int32_t sframe_fre_get_fp_offset (sframe_decoder_ctx *dctx, sframe_frame_row_entry *fre, int *errp); -/* Get the RA offset from the FRE. If the offset is invalid, sets errp. */ +/* Get the RA offset from the FRE. If the offset is invalid, sets errp. + + For s390x an RA offset value of SFRAME_FRE_RA_OFFSET_INVALID indicates + that the RA is not saved, which is only valid in the topmost frame. + For s390x the offset may be an encoded register number, indicated by + LSB set to one, which is only valid in the topmost frame. */ extern int32_t sframe_fre_get_ra_offset (sframe_decoder_ctx *dctx, sframe_frame_row_entry *fre, int *errp); diff --git a/include/sframe.h b/include/sframe.h index c0375ba..7523adb 100644 --- a/include/sframe.h +++ b/include/sframe.h @@ -104,6 +104,7 @@ extern "C" #define SFRAME_ABI_AARCH64_ENDIAN_BIG 1 /* AARCH64 big endian. */ #define SFRAME_ABI_AARCH64_ENDIAN_LITTLE 2 /* AARCH64 little endian. */ #define SFRAME_ABI_AMD64_ENDIAN_LITTLE 3 /* AMD64 little endian. */ +#define SFRAME_ABI_S390X_ENDIAN_BIG 4 /* s390x big endian. */ /* SFrame FRE types. */ #define SFRAME_FRE_TYPE_ADDR1 0 @@ -201,7 +202,7 @@ typedef struct sframe_func_desc_entry - 2-bits: Unused. ------------------------------------------------------------------------ | Unused | PAC auth A/B key (aarch64) | FDE type | FRE type | - | | Unused (amd64) | | | + | | Unused (amd64, s390x) | | | ------------------------------------------------------------------------ 8 6 5 4 0 */ uint8_t sfde_func_info; @@ -247,6 +248,10 @@ typedef struct sframe_func_desc_entry may or may not be tracked. */ #define SFRAME_FRE_FP_OFFSET_IDX 2 +/* Invalid RA offset. Currently used for s390x as padding to represent FP + without RA saved. */ +#define SFRAME_FRE_RA_OFFSET_INVALID 0 + typedef struct sframe_fre_info { /* Information about @@ -259,7 +264,7 @@ typedef struct sframe_fre_info - 1 bit: Mangled RA state bit (aarch64 only). ---------------------------------------------------------------------------------- | Mangled-RA (aarch64) | Size of offsets | Number of offsets | base_reg | - | Unused (amd64) | | | | + | Unused (amd64, s390x)| | | | ---------------------------------------------------------------------------------- 8 7 5 1 0 @@ -285,7 +290,7 @@ typedef struct sframe_fre_info /* SFrame Frame Row Entry definitions. - Used for both AMD64 and AARCH64. + Used for AMD64, AARCH64, and s390x. An SFrame Frame Row Entry is a self-sufficient record which contains information on how to generate the stack trace for the specified range of @@ -309,6 +314,24 @@ typedef struct sframe_fre_info fi Note that in AAPCS64, a frame record, if created, will save both FP and LR on stack. + + s390x: + offset1 (interpreted as CFA = BASE_REG + offset1) + if RA is being tracked + offset2 (interpreted as RA = CFA + offset2; an offset value of + SFRAME_FRE_RA_OFFSET_INVALID indicates a dummy padding RA offset + to represent FP without RA saved on stack) + if FP is being tracked + offset3 (intrepreted as FP = CFA + offset3) + fi + else + if FP is being tracked + offset2 (intrepreted as FP = CFA + offset2) + fi + fi + Note that in s390x, if a FP/RA offset2/offset3 value has the least- + significant bit set it represents a DWARF register number shifted to the + left by 1 to restore the FP/RA value from. */ /* Used when SFRAME_FRE_TYPE_ADDR1 is specified as FRE type. */ @@ -353,6 +376,36 @@ typedef struct sframe_frame_row_entry_addr4 #define SFRAME_FRE_TYPE_ADDR4_LIMIT \ (1ULL << ((SFRAME_FRE_TYPE_ADDR4 * 2) * 8)) +/* On s390x, the CFA offset from CFA base register is by definition a minimum + of 160. Store it adjusted by -160 to enable use of 8-bit SFrame offsets. + Additionally scale by an alignment factor of 8, as the SP and thus CFA + offset on s390x is always 8-byte aligned. */ +#define SFRAME_S390X_CFA_OFFSET_ADJUSTMENT SFRAME_S390X_SP_VAL_OFFSET +#define SFRAME_S390X_CFA_OFFSET_ALIGNMENT_FACTOR 8 +#define SFRAME_V2_S390X_CFA_OFFSET_ENCODE(offset) \ + (((offset) + SFRAME_S390X_CFA_OFFSET_ADJUSTMENT) \ + / SFRAME_S390X_CFA_OFFSET_ALIGNMENT_FACTOR) +#define SFRAME_V2_S390X_CFA_OFFSET_DECODE(offset) \ + (((offset) * SFRAME_S390X_CFA_OFFSET_ALIGNMENT_FACTOR) \ + - SFRAME_S390X_CFA_OFFSET_ADJUSTMENT) + +/* On s390x, the CFA is defined as SP at call site + 160. Therefore the + SP value offset from CFA is -160. */ +#define SFRAME_S390X_SP_VAL_OFFSET (-160) + +/* On s390x, the FP and RA registers can be saved either on the stack or, + in case of leaf functions, in registers. Store DWARF register numbers + encoded as offset by using the least-significant bit (LSB) as indicator: + - LSB=0: Stack offset. The s390x ELF ABI mandates that stack register + slots must be 8-byte aligned. + - LSB=1: DWARF register number shifted to the left by one. */ +#define SFRAME_V2_S390X_OFFSET_IS_REGNUM(offset) \ + ((offset) & 1) +#define SFRAME_V2_S390X_OFFSET_ENCODE_REGNUM(regnum) \ + (((regnum) << 1) | 1) +#define SFRAME_V2_S390X_OFFSET_DECODE_REGNUM(offset) \ + ((offset) >> 1) + #ifdef __cplusplus } #endif |