diff options
Diffstat (limited to 'include/opcode')
-rw-r--r-- | include/opcode/aarch64.h | 13 | ||||
-rw-r--r-- | include/opcode/d30v.h | 4 | ||||
-rw-r--r-- | include/opcode/riscv.h | 8 |
3 files changed, 18 insertions, 7 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 7c1163d..dab6eac 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -282,6 +282,10 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SVE_B16B16, /* SME non-widening BFloat16 instructions. */ AARCH64_FEATURE_SME_B16B16, + /* SVE2.2. */ + AARCH64_FEATURE_SVE2p2, + /* SME2.2. */ + AARCH64_FEATURE_SME2p2, /* Armv9.1-A processors. */ AARCH64_FEATURE_V9_1A, /* Armv9.2-A processors. */ @@ -307,6 +311,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_FP8DOT2_SVE, /* +sme-f16f16 or +sme-f8f16 */ AARCH64_FEATURE_SME_F16F16_F8F16, + /* +sve or +sme2p2 */ + AARCH64_FEATURE_SVE_SME2p2, /* +sve2 or +sme2 */ AARCH64_FEATURE_SVE2_SME2, /* +sve2p1 or +sme */ @@ -315,6 +321,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SVE2p1_SME2, /* +sve2p1 or +sme2p1 */ AARCH64_FEATURE_SVE2p1_SME2p1, + /* +sve2p2 or +sme2p2 */ + AARCH64_FEATURE_SVE2p2_SME2p2, AARCH64_NUM_FEATURES }; @@ -1192,13 +1200,16 @@ enum aarch64_insn_class sve_pred_zm, sve_shift_pred, sve_shift_unpred, + sve_size_bh, sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_hsd2, + sve_size_hsd3, sve_size_sd, - sve_size_bh, sve_size_sd2, + sve_size_sd3, + sve_size_sd4, sve_size_13, sve_shift_tsz_hsd, sve_shift_tsz_bhsd, diff --git a/include/opcode/d30v.h b/include/opcode/d30v.h index 82b7612..a8db13e 100644 --- a/include/opcode/d30v.h +++ b/include/opcode/d30v.h @@ -279,8 +279,8 @@ extern const struct d30v_format d30v_format_table[]; /* formats, 2 SHORT_A forms and a LONG form. */ struct d30v_insn { - struct d30v_opcode *op; /* pointer to an entry in the opcode table */ - struct d30v_format *form; /* pointer to an entry in the format table */ + const struct d30v_opcode *op; /* pointer to an entry in the opcode table */ + const struct d30v_format *form; /* pointer to an entry in the format table */ int ecc; /* execution condition code */ }; diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 2b146af..858fcce 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -493,18 +493,18 @@ enum riscv_insn_class INSN_CLASS_NONE, INSN_CLASS_I, - INSN_CLASS_C, + INSN_CLASS_ZCA, INSN_CLASS_M, INSN_CLASS_F, INSN_CLASS_D, INSN_CLASS_Q, - INSN_CLASS_F_AND_C, - INSN_CLASS_D_AND_C, + INSN_CLASS_ZCF, + INSN_CLASS_ZCD, INSN_CLASS_ZICOND, INSN_CLASS_ZICSR, INSN_CLASS_ZIFENCEI, INSN_CLASS_ZIHINTNTL, - INSN_CLASS_ZIHINTNTL_AND_C, + INSN_CLASS_ZIHINTNTL_AND_ZCA, INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_ZIMOP, INSN_CLASS_ZMMUL, |