diff options
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/aarch64.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index dab6eac..826bd7d 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -187,6 +187,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_THE, /* LSE128. */ AARCH64_FEATURE_LSE128, + /* LSUI - Unprivileged Load Store. */ + AARCH64_FEATURE_LSUI, /* ARMv8.9-A RAS Extensions. */ AARCH64_FEATURE_RASv2, /* Delegated SError exceptions for EL3. */ @@ -242,6 +244,12 @@ enum aarch64_feature_bit { AARCH64_FEATURE_F8F32MM, /* F8F16MM instructions. */ AARCH64_FEATURE_F8F16MM, + /* SVE_PMULL128 extension. */ + AARCH64_FEATURE_SVE_AES, + /* SVE AES2 instructions. */ + AARCH64_FEATURE_SVE_AES2, + /* SSVE_AES extension. */ + AARCH64_FEATURE_SSVE_AES, /* RCPC3 instructions. */ AARCH64_FEATURE_RCPC3, /* Enhanced Software Step Extension. */ @@ -303,6 +311,8 @@ enum aarch64_feature_bit { /* Virtual features. These are used to gate instructions that are enabled by either of two (or more) sets of command line flags. */ + /* +sve2 or +ssve-aes */ + AARCH64_FEATURE_SVE2_SSVE_AES, /* +fp8fma+sve or +ssve-fp8fma */ AARCH64_FEATURE_FP8FMA_SVE, /* +fp8dot4+sve or +ssve-fp8dot4 */ @@ -783,6 +793,7 @@ enum aarch64_opnd AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ AARCH64_OPND_BARRIER_GCSB, /* Barrier operand for GCSB. */ AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */ + AARCH64_OPND_STSHH_POLICY, /* STSHH {<policy>}. */ AARCH64_OPND_BRBOP, /* BRB operation IALL or INJ in bit 5. */ AARCH64_OPND_Rt_IN_SYS_ALIASES, /* Defaulted and omitted Rt used in SYS aliases such as brb. */ AARCH64_OPND_LSE128_Rt, /* LSE128 <Xt1>. */ @@ -974,6 +985,7 @@ enum aarch64_opnd AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */ AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */ AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */ + AARCH64_OPND_SME_Zn_INDEX2_19, /* Zn[index], bits [9:5] and [20:19]. */ AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */ AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */ AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */ @@ -1878,6 +1890,8 @@ struct aarch64_inst #define HINT_OPD_C 0x22 #define HINT_OPD_J 0x24 #define HINT_OPD_JC 0x26 +#define HINT_OPD_KEEP 0x30 +#define HINT_OPD_STRM 0x31 #define HINT_OPD_NULL 0x00 |