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-rw-r--r--gas/ChangeLog8
-rw-r--r--gas/config/tc-arm.c30
-rw-r--r--gas/testsuite/ChangeLog6
-rw-r--r--gas/testsuite/gas/arm/vfp1xD.d11
-rw-r--r--gas/testsuite/gas/arm/vfp1xD.s10
5 files changed, 57 insertions, 8 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9209d4d..b6fe7e3 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2012-03-20 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-arm.c (do_vmrs): Accept priviledged mode VFP system
+ registers.
+ (do_vmsr): Likewise.
+ (arm_opcode_insns): Do not default to using the FPSCR register in
+ the VMRS and VMSR registers.
+
2012-03-16 Roland McGrath <mcgrathr@google.com>
* config/tc-i386.h [TE_NACL] (ELF_TARGET_FORMAT32, ELF_TARGET_FORMAT64):
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 8b0f6da..9222aff 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -8102,8 +8102,18 @@ do_vmrs (void)
return;
}
- if (inst.operands[1].reg != 1)
- first_error (_("operand 1 must be FPSCR"));
+ switch (inst.operands[1].reg)
+ {
+ case 0: /* FPSID */
+ case 1: /* FPSCR */
+ case 6: /* MVFR1 */
+ case 7: /* MVFR0 */
+ case 8: /* FPEXC */
+ inst.instruction |= (inst.operands[1].reg << 16);
+ break;
+ default:
+ first_error (_("operand 1 must be a VFP extension System Register"));
+ }
inst.instruction |= (Rt << 12);
}
@@ -8121,8 +8131,16 @@ do_vmsr (void)
return;
}
- if (inst.operands[0].reg != 1)
- first_error (_("operand 0 must be FPSCR"));
+ switch (inst.operands[0].reg)
+ {
+ case 0: /* FPSID */
+ case 1: /* FPSCR */
+ case 8: /* FPEXC */
+ inst.instruction |= (inst.operands[0].reg << 16);
+ break;
+ default:
+ first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC"));
+ }
inst.instruction |= (Rt << 12);
}
@@ -18147,8 +18165,8 @@ static const struct asm_opcode insns[] =
cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
cCE("fmstat", ef1fa10, 0, (), noargs),
- cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs),
- cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr),
+ cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
+ cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 7ac59cd..5fc3567 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2012-03-20 Nick Clifton <nickc@redhat.com>
+
+ * gas/arm/vfp1xD.s: Add tests of the VMSR ad VMRS instructions in
+ priviledged modes.
+ * gas/arm/vfp1xD.d: Update expected output.
+
2012-03-16 Matthew Gretton-Dann <matther.gretton-dann@arm.com>
* gas/testsuite/gas/arm/any-idiv.d: New testcase.
diff --git a/gas/testsuite/gas/arm/vfp1xD.d b/gas/testsuite/gas/arm/vfp1xD.d
index eebc72b..62b1957 100644
--- a/gas/testsuite/gas/arm/vfp1xD.d
+++ b/gas/testsuite/gas/arm/vfp1xD.d
@@ -278,5 +278,12 @@ Disassembly of section .text:
0+430 <[^>]*> eee1ba10 vmsr fpscr, fp
0+434 <[^>]*> eee1ca10 vmsr fpscr, ip
0+438 <[^>]*> eee1ea10 vmsr fpscr, lr
-0+43c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
-
+0+43c <[^>]*> eee01a10 vmsr fpsid, r1
+0+440 <[^>]*> eee82a10 vmsr fpexc, r2
+0+444 <[^>]*> eef03a10 vmrs r3, fpsid
+0+448 <[^>]*> eef64a10 vmrs r4, mvfr1
+0+44c <[^>]*> eef75a10 vmrs r5, mvfr0
+0+450 <[^>]*> eef86a10 vmrs r6, fpexc
+0+454 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
+0+458 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
+0+45c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/vfp1xD.s b/gas/testsuite/gas/arm/vfp1xD.s
index 274a0b1..0bf58b2 100644
--- a/gas/testsuite/gas/arm/vfp1xD.s
+++ b/gas/testsuite/gas/arm/vfp1xD.s
@@ -381,4 +381,14 @@ F:
vmsr FPSCR, r12
vmsr FPSCR, r14
+ @ Priviledged externsions to VMSR/VMRS instructions
+ vmsr FPSID, r1
+ vmsr FPEXC, r2
+ vmrs r3, FPSID
+ vmrs r4, MVFR1
+ vmrs r5, MVFR0
+ vmrs r6, FPEXC
+
+ nop
+ nop
nop