diff options
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-aarch64.c | 41 | ||||
| -rw-r--r-- | gas/config/tc-i386.c | 23 |
2 files changed, 12 insertions, 52 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 840cf8c..e071ad1 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -8465,6 +8465,7 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str) case ldst_imm10: case ldst_unscaled: case ldst_unpriv: + ldst_single: /* Loading/storing the base register is unpredictable if writeback. */ if ((aarch64_get_operand_class (opnds[0].type) == AARCH64_OPND_CLASS_INT_REG) @@ -8477,43 +8478,9 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str) break; case rcpc3: - { - const int nb_operands = aarch64_num_of_operands (opcode); - if (aarch64_get_operand_class (opnds[0].type) - == AARCH64_OPND_CLASS_INT_REG) - { - /* Load Pair transfer with register overlap. */ - if (nb_operands == 3 && opnds[0].reg.regno == opnds[1].reg.regno) - { // ldiapp, stilp - as_warn (_("unpredictable load pair transfer with register " - "overlap -- `%s'"), - str); - } - /* Loading/storing the base register is unpredictable if writeback. */ - else if ((nb_operands == 2 - && opnds[0].reg.regno == opnds[1].addr.base_regno - && opnds[1].addr.base_regno != REG_SP - && opnds[1].addr.writeback) - || (nb_operands == 3 - && (opnds[0].reg.regno == opnds[2].addr.base_regno - || opnds[1].reg.regno == opnds[2].addr.base_regno) - && opnds[2].addr.base_regno != REG_SP - && opnds[2].addr.writeback)) - { - if (strcmp (opcode->name, "ldapr") == 0 - || strcmp (opcode->name, "ldiapp") == 0) - as_warn ( - _("unpredictable transfer with writeback (load) -- `%s'"), - str); - else // stlr, stilp - as_warn ( - _("unpredictable transfer with writeback (store) -- `%s'"), - str); - } - } - } - break; - + if (aarch64_num_of_operands (opcode) == 2) + goto ldst_single; + /* Fall through. */ case ldstpair_off: case ldstnapair_offs: case ldstpair_indexed: diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 3879001..2319840 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -4422,7 +4422,7 @@ static void build_evex_prefix (void) { unsigned int register_specifier; - bool w, u; + bool w; rex_byte vrex_used = 0; /* Check register specifier. */ @@ -4545,12 +4545,10 @@ build_evex_prefix (void) abort (); } - u = i.rounding.type == rc_none || i.tm.opcode_modifier.evex != EVEX256; - /* The third byte of the EVEX prefix. */ i.vex.bytes[2] = ((w << 7) | (register_specifier << 3) - | (u << 2) + | 4 /* Encode the U bit. */ | i.tm.opcode_modifier.opcodeprefix); /* The fourth byte of the EVEX prefix. */ @@ -8824,19 +8822,14 @@ check_VecOperands (const insn_template *t) return 1; } - /* Non-EVEX.{LIG,512,256} forms need to have a ZMM or YMM register as at - least one operand. For YMM register or EVEX256, we will need AVX10.2 - enabled. There's no need to check all operands, though: Either of the - last two operands will be of the right size in all relevant templates. */ + /* Non-EVEX.{LIG,512} forms need to have a ZMM or YMM register as at + least one operand. There's no need to check all operands, though: + Either of the last two operands will be of the right size in all + relevant templates. */ if (t->opcode_modifier.evex != EVEXLIG && t->opcode_modifier.evex != EVEX512 - && (t->opcode_modifier.evex != EVEX256 - || !cpu_arch_flags.bitfield.cpuavx10_2) && !i.types[t->operands - 1].bitfield.zmmword - && !i.types[t->operands - 2].bitfield.zmmword - && ((!i.types[t->operands - 1].bitfield.ymmword - && !i.types[t->operands - 2].bitfield.ymmword) - || !cpu_arch_flags.bitfield.cpuavx10_2)) + && !i.types[t->operands - 2].bitfield.zmmword) { i.error = operand_size_mismatch; return 1; @@ -14032,7 +14025,7 @@ s_insn (int dummy ATTRIBUTE_UNUSED) { if (!i.tm.opcode_modifier.evex) { - /* Do _not_ consider AVX512VL / AVX10.2 here. */ + /* Do _not_ consider AVX512VL here. */ if (combined.bitfield.zmmword) i.tm.opcode_modifier.evex = EVEX512; else if (combined.bitfield.ymmword) |