diff options
Diffstat (limited to 'gas/NEWS')
| -rw-r--r-- | gas/NEWS | 35 |
1 files changed, 33 insertions, 2 deletions
@@ -1,10 +1,19 @@ -*- text -*- +* NaCl target support is removed. + +Changes in 2.45: + +* Add support to generate SFrame stack trace information (.sframe) + from CFI directives on s390 64-bit (s390x). + * All SFrame sections generated by gas have the header flag SFRAME_F_FDE_FUNC_START_PCREL set. gas was already emitting SFrame sections with the applicable encoding. Setting the flag ensures compliance with the updated SFrame V2 specification. + ELF SFrame sections now have section type set to SHT_GNU_SFRAME. + * Add .errif and .warnif directives, permitting user-controlled diagnostics with conditionals that are evaluated only at the end of assembly. @@ -14,10 +23,15 @@ * Support for x86 AVX10.2 256 bit rounding has been dropped, as all the hardware would directly support 512 bit vecotr width. +* For RISC-V, the ".option arch, -ext" format is deprecated due to its + controversial use. + * For RISC-V, stop generating mapping symbols $x and replace with $x<isa>. The $x was defined to have the same ISA as previous $x<isa>, but now is defined - to have the same ISA as elf architecture attribute. Once used .option arch - directives, the file need to be rebuilt since 2.45. + to have the same ISA as elf architecture attribute. Once both used .option + arch/rvc/norvc/push/pop directives (some code have different architectures + with file attribute) and data directives in text, then the file need to be + rebuilt since 2.45. * Add support for RISC-V privileged version 1.13, profiles 20/22/23, and .bfloat16 directive. @@ -33,6 +47,23 @@ * Add support for the x86 Zhaoxin PadLock XMODX instructions. +* Add support for several instruction aliases defined for the LoongArch 32-bit + reduced subset (LA32R): rdcntvl.w, rdcntvh.w, rdcntid.w. + +* For LoongArch, warn about out-of-range 3rd arguments (maximum number of + bytes to skip) of .align directives. + +* For LoongArch, warn about negative right-shift amounts and + division/modulus-by-zero when evaluating expressions. + +* Add support for most Armv9.6 extensions, enabled by the option + `-march=armv9.6-a' and extensions '+cmpbr', '+f8f16mm', '+f8f32mm', + '+fprcvt', '+lsfe', '+lsui', '+occmo', '+pops', '+sme2p2', '+ssve-aes', + '+sve-aes', '+sve-aes2', '+sve-bfscale', '+sve-f16f32mm' and '+sve2p2'. + +* AArch64 system registers can now be assembled without restriction. The + previous behavior can be enabled with '-menable-sysreg-checking'. + Changes in 2.44: * Add support for the x86 Intel Diamond Rapids AMX instructions, including |