diff options
| -rw-r--r-- | gas/config/tc-aarch64.c | 14 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/diagnostic.l | 17 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/diagnostic.s | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-ldapr.l | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-ldraa.l | 8 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-lse.l | 456 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-memtag.l | 18 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-sve2.l | 68 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sve-reg-diagnostic.l | 10 |
9 files changed, 308 insertions, 293 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 3237530..ee88c8f 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -3819,10 +3819,18 @@ parse_address_main (char **str, aarch64_opnd_info *operand, /* [ */ + bool alpha_base_p = ISALPHA (*p); reg = aarch64_addr_reg_parse (&p, base_type, base_qualifier); if (!reg || !aarch64_check_reg_type (reg, base_type)) { - set_syntax_error (_(get_reg_expected_msg (base_type))); + if (reg + && aarch64_check_reg_type (reg, REG_TYPE_R_SP) + && *base_qualifier == AARCH64_OPND_QLF_W) + set_syntax_error (_("expected a 64-bit base register")); + else if (alpha_base_p) + set_syntax_error (_("invalid base register")); + else + set_syntax_error (_("expected a base register")); return false; } operand->addr.base_regno = reg->number; @@ -3838,7 +3846,7 @@ parse_address_main (char **str, aarch64_opnd_info *operand, { if (!aarch64_check_reg_type (reg, offset_type)) { - set_syntax_error (_(get_reg_expected_msg (offset_type))); + set_syntax_error (_("invalid offset register")); return false; } @@ -3974,7 +3982,7 @@ parse_address_main (char **str, aarch64_opnd_info *operand, /* [Xn],Xm */ if (!aarch64_check_reg_type (reg, REG_TYPE_R_64)) { - set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64))); + set_syntax_error (_("invalid offset register")); return false; } diff --git a/gas/testsuite/gas/aarch64/diagnostic.l b/gas/testsuite/gas/aarch64/diagnostic.l index 87cc4fe..9935989 100644 --- a/gas/testsuite/gas/aarch64/diagnostic.l +++ b/gas/testsuite/gas/aarch64/diagnostic.l @@ -54,7 +54,7 @@ [^:]*:56: Error: operand 2 must be a floating-point register -- `fcmp d0,x0' [^:]*:57: Error: immediate zero expected at operand 3 -- `cmgt v0.4s,v2.4s,#1' [^:]*:58: Error: unexpected characters following instruction at operand 2 -- `fmov d3,1.00,lsl#3' -[^:]*:59: Error: integer 64-bit register expected at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],sp' +[^:]*:59: Error: invalid offset register at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],sp' [^:]*:60: Error: writeback value must be an immediate constant at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],zr' [^:]*:61: Error: invalid shift for the register offset addressing mode at operand 2 -- `ldr q0,\[x0,w0,lsr#4\]' [^:]*:62: Error: only 'LSL' shift is permitted at operand 3 -- `adds x1,sp,2134,uxtw#12' @@ -116,10 +116,10 @@ [^:]*:126: Warning: unpredictable transfer with writeback -- `ldp x0,x1,\[x1\],#16' [^:]*:127: Error: this relocation modifier is not allowed on this instruction at operand 2 -- `adr x2,:got:s1' [^:]*:128: Error: this relocation modifier is not allowed on this instruction at operand 2 -- `ldr x0,\[x0,:got:s1\]' -[^:]*:131: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[wsp,#8\]!' -[^:]*:132: Error: 64-bit integer or SP register expected at operand 3 -- `ldp x6,x29,\[w7,#8\]!' -[^:]*:133: Error: 64-bit integer or SP register expected at operand 2 -- `str x30,\[w11,#8\]!' -[^:]*:134: Error: 64-bit integer or SP register expected at operand 3 -- `stp x8,x27,\[wsp,#8\]!' +[^:]*:131: Error: expected a 64-bit base register at operand 2 -- `ldr x1,\[wsp,#8\]!' +[^:]*:132: Error: expected a 64-bit base register at operand 3 -- `ldp x6,x29,\[w7,#8\]!' +[^:]*:133: Error: expected a 64-bit base register at operand 2 -- `str x30,\[w11,#8\]!' +[^:]*:134: Error: expected a 64-bit base register at operand 3 -- `stp x8,x27,\[wsp,#8\]!' [^:]*:214: Error: register element index out of range 0 to 1 at operand 2 -- `dup v0\.2d,v1\.2d\[-1\]' [^:]*:217: Error: register element index out of range 0 to 1 at operand 2 -- `dup v0\.2d,v1\.2d\[2\]' [^:]*:218: Error: register element index out of range 0 to 1 at operand 2 -- `dup v0\.2d,v1\.2d\[64\]' @@ -144,8 +144,8 @@ [^:]*:256: Error: register element index out of range 0 to 15 at operand 1 -- `ld2 {v0\.b,v1\.b}\[-1\],\[x0\]' [^:]*:259: Error: register element index out of range 0 to 15 at operand 1 -- `ld2 {v0\.b,v1\.b}\[16\],\[x0\]' [^:]*:260: Error: register element index out of range 0 to 15 at operand 1 -- `ld2 {v0\.b,v1\.b}\[67\],\[x0\]' -[^:]*:267: Error: integer 64-bit register expected at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],xzr' -[^:]*:268: Error: integer or zero register expected at operand 2 -- `str x1,\[x2,sp\]' +[^:]*:267: Error: invalid offset register at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],xzr' +[^:]*:268: Error: invalid offset register at operand 2 -- `str x1,\[x2,sp\]' [^:]*:271: Error: relocation not allowed at operand 3 -- `ldnp x1,x2,\[x3,#:lo12:foo\]' [^:]*:272: Error: invalid addressing mode at operand 2 -- `ld1 {v0\.4s},\[x3,#:lo12:foo\]' [^:]*:273: Error: the optional immediate offset can only be 0 at operand 2 -- `stuminl x0,\[x3,#:lo12:foo\]' @@ -183,3 +183,6 @@ [^:]*:312: Warning: unpredictable load of register pair -- `ldxp x26,x26,\[x5\]' [^:]*:314: Error: expected element type rather than vector type at operand 1 -- `st4 {v0\.16b-v3\.16b}\[4\],\[x0\]' [^:]*:315: Warning: unpredictable: identical base and status registers --`stlxp w3,w26,w26,\[x3\]' +[^:]*:317: Error: expected a base register at operand 2 -- `ldr x0,\[1\]' +[^:]*:318: Error: expected a base register at operand 2 -- `ldr x0,\[\]' +[^:]*:319: Error: expected a base register at operand 2 -- `ldr x0,\[,xzr\]' diff --git a/gas/testsuite/gas/aarch64/diagnostic.s b/gas/testsuite/gas/aarch64/diagnostic.s index 0ebe85a..014e0ab 100644 --- a/gas/testsuite/gas/aarch64/diagnostic.s +++ b/gas/testsuite/gas/aarch64/diagnostic.s @@ -313,3 +313,7 @@ ldxp x26, x1, [x26] st4 {v0.16b-v3.16b}[4], [x0] stlxp w3, w26, w26, [x3] + + ldr x0, [1] + ldr x0, [] + ldr x0, [,xzr] diff --git a/gas/testsuite/gas/aarch64/illegal-ldapr.l b/gas/testsuite/gas/aarch64/illegal-ldapr.l index 8a91e79..5e3ca6d 100644 --- a/gas/testsuite/gas/aarch64/illegal-ldapr.l +++ b/gas/testsuite/gas/aarch64/illegal-ldapr.l @@ -2,7 +2,7 @@ [^:]+:18: Error: operand mismatch -- `ldaprb x0,\[x1\]' [^:]+:19: Error: operand mismatch -- `ldaprh x0,\[x1\]' [^:]+:20: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr x0,\[x1,#8\]' -[^:]+:5: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprb w1,\[xz\]' +[^:]+:5: Error: invalid base register at operand 2 -- `ldaprb w1,\[xz\]' [^:]+:23: Info: macro .* [^:]+:6: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprb w1,\[x7,#8\]' [^:]+:23: Info: macro .* @@ -10,7 +10,7 @@ [^:]+:23: Info: macro .* [^:]+:8: Error: invalid addressing mode at operand 2 -- `ldaprb w1,\[x7\],#8' [^:]+:23: Info: macro .* -[^:]+:5: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprh w1,\[xz\]' +[^:]+:5: Error: invalid base register at operand 2 -- `ldaprh w1,\[xz\]' [^:]+:23: Info: macro .* [^:]+:6: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprh w1,\[x7,#8\]' [^:]+:23: Info: macro .* @@ -18,7 +18,7 @@ [^:]+:23: Info: macro .* [^:]+:8: Error: invalid addressing mode at operand 2 -- `ldaprh w1,\[x7\],#8' [^:]+:23: Info: macro .* -[^:]+:5: Error: 64-bit integer or SP register expected at operand 2 -- `ldapr w1,\[xz\]' +[^:]+:5: Error: invalid base register at operand 2 -- `ldapr w1,\[xz\]' [^:]+:23: Info: macro .* [^:]+:6: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr w1,\[x7,#8\]' [^:]+:23: Info: macro .* diff --git a/gas/testsuite/gas/aarch64/illegal-ldraa.l b/gas/testsuite/gas/aarch64/illegal-ldraa.l index 33fae2f..b9a7922 100644 --- a/gas/testsuite/gas/aarch64/illegal-ldraa.l +++ b/gas/testsuite/gas/aarch64/illegal-ldraa.l @@ -5,7 +5,7 @@ [^:]+:12: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#4096\]' [^:]+:13: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#5555\]' [^:]+:14: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#-4104\]' -[^:]+:15: Error: 64-bit integer or SP register expected at operand 2 -- `ldraa x0,\[xz\]' +[^:]+:15: Error: invalid base register at operand 2 -- `ldraa x0,\[xz\]' [^:]+:16: Error: invalid expression in the address at operand 2 -- `ldraa x0,\[sp\],' [^:]+:17: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#1\]!' [^:]+:18: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#4\]!' @@ -13,7 +13,7 @@ [^:]+:20: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#4096\]!' [^:]+:21: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#5555\]!' [^:]+:22: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#-4104\]!' -[^:]+:23: Error: 64-bit integer or SP register expected at operand 2 -- `ldraa x0,\[xz\]' +[^:]+:23: Error: invalid base register at operand 2 -- `ldraa x0,\[xz\]' [^:]+:24: Error: invalid addressing mode at operand 2 -- `ldraa x0,\[x1\],#8' [^:]+:27: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#1\]' [^:]+:28: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#4\]' @@ -21,7 +21,7 @@ [^:]+:30: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#4096\]' [^:]+:31: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#5555\]' [^:]+:32: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#-4104\]' -[^:]+:33: Error: 64-bit integer or SP register expected at operand 2 -- `ldrab x0,\[xz\]' +[^:]+:33: Error: invalid base register at operand 2 -- `ldrab x0,\[xz\]' [^:]+:34: Error: invalid expression in the address at operand 2 -- `ldrab x0,\[sp\],' [^:]+:35: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#1\]!' [^:]+:36: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#4\]!' @@ -29,5 +29,5 @@ [^:]+:38: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#4096\]!' [^:]+:39: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#5555\]!' [^:]+:40: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#-4104\]!' -[^:]+:41: Error: 64-bit integer or SP register expected at operand 2 -- `ldrab x0,\[xz\]' +[^:]+:41: Error: invalid base register at operand 2 -- `ldrab x0,\[xz\]' [^:]+:42: Error: invalid addressing mode at operand 2 -- `ldrab x0,\[x1\],#8' diff --git a/gas/testsuite/gas/aarch64/illegal-lse.l b/gas/testsuite/gas/aarch64/illegal-lse.l index b47108d..7c87a84 100644 --- a/gas/testsuite/gas/aarch64/illegal-lse.l +++ b/gas/testsuite/gas/aarch64/illegal-lse.l @@ -1,131 +1,131 @@ [^:]*: Assembler messages: [^:]*:26: Error: operand mismatch -- `cas w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `cas w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `cas w2,w3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:26: Error: operand mismatch -- `casa w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casa w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casa w2,w3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:26: Error: operand mismatch -- `casl w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casl w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casl w2,w3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:26: Error: operand mismatch -- `casal w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casal w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casal w2,w3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:26: Error: operand mismatch -- `casb w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casb w2,w3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:26: Error: operand mismatch -- `cash w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `cash w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `cash w2,w3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:26: Error: operand mismatch -- `casab w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casab w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casab w2,w3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:26: Error: operand mismatch -- `caslb w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `caslb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `caslb w2,w3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:26: Error: operand mismatch -- `casalb w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casalb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casalb w2,w3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:26: Error: operand mismatch -- `casah w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casah w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casah w2,w3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:26: Error: operand mismatch -- `caslh w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `caslh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `caslh w2,w3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:26: Error: operand mismatch -- `casalh w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casalh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `casalh w2,w3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:30: Error: operand mismatch -- `cas w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `cas x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `cas x2,x3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:30: Error: operand mismatch -- `casa w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `casa x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `casa x2,x3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:30: Error: operand mismatch -- `casl w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `casl x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `casl x2,x3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:30: Error: operand mismatch -- `casal w0,x1,\[x2\]' [^:]*:68: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `casal x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `casal x2,x3,\[w4\]' [^:]*:68: *Info: macro .* [^:]*:26: Error: operand mismatch -- `swp w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swp w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swp w2,w3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:26: Error: operand mismatch -- `swpa w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpa w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpa w2,w3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:26: Error: operand mismatch -- `swpl w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpl w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpl w2,w3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:26: Error: operand mismatch -- `swpal w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpal w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpal w2,w3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:26: Error: operand mismatch -- `swpb w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpb w2,w3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:26: Error: operand mismatch -- `swph w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swph w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swph w2,w3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:26: Error: operand mismatch -- `swpab w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpab w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpab w2,w3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:26: Error: operand mismatch -- `swplb w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swplb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swplb w2,w3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:26: Error: operand mismatch -- `swpalb w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpalb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpalb w2,w3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:26: Error: operand mismatch -- `swpah w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpah w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpah w2,w3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:26: Error: operand mismatch -- `swplh w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swplh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swplh w2,w3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:26: Error: operand mismatch -- `swpalh w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpalh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `swpalh w2,w3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:30: Error: operand mismatch -- `swp w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `swp x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `swp x2,x3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:30: Error: operand mismatch -- `swpa w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `swpa x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `swpa x2,x3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:30: Error: operand mismatch -- `swpl w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `swpl x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `swpl x2,x3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:30: Error: operand mismatch -- `swpal w0,x1,\[x2\]' [^:]*:69: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `swpal x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `swpal x2,x3,\[w4\]' [^:]*:69: *Info: macro .* [^:]*:47: Error: reg pair must start from even reg at operand 1 -- `casp w1,w1,w2,w3,\[x5\]' [^:]*:70: *Info: macro .* @@ -133,7 +133,7 @@ [^:]*:70: *Info: macro .* [^:]*:49: Error: operand mismatch -- `casp w0,x1,x2,x3,\[x2\]' [^:]*:70: *Info: macro .* -[^:]*:50: Error: 64-bit integer or SP register expected at operand 5 -- `casp x4,x5,x6,x7,\[w8\]' +[^:]*:50: Error: expected a 64-bit base register at operand 5 -- `casp x4,x5,x6,x7,\[w8\]' [^:]*:70: *Info: macro .* [^:]*:47: Error: reg pair must start from even reg at operand 1 -- `caspa w1,w1,w2,w3,\[x5\]' [^:]*:70: *Info: macro .* @@ -141,7 +141,7 @@ [^:]*:70: *Info: macro .* [^:]*:49: Error: operand mismatch -- `caspa w0,x1,x2,x3,\[x2\]' [^:]*:70: *Info: macro .* -[^:]*:50: Error: 64-bit integer or SP register expected at operand 5 -- `caspa x4,x5,x6,x7,\[w8\]' +[^:]*:50: Error: expected a 64-bit base register at operand 5 -- `caspa x4,x5,x6,x7,\[w8\]' [^:]*:70: *Info: macro .* [^:]*:47: Error: reg pair must start from even reg at operand 1 -- `caspl w1,w1,w2,w3,\[x5\]' [^:]*:70: *Info: macro .* @@ -149,7 +149,7 @@ [^:]*:70: *Info: macro .* [^:]*:49: Error: operand mismatch -- `caspl w0,x1,x2,x3,\[x2\]' [^:]*:70: *Info: macro .* -[^:]*:50: Error: 64-bit integer or SP register expected at operand 5 -- `caspl x4,x5,x6,x7,\[w8\]' +[^:]*:50: Error: expected a 64-bit base register at operand 5 -- `caspl x4,x5,x6,x7,\[w8\]' [^:]*:70: *Info: macro .* [^:]*:47: Error: reg pair must start from even reg at operand 1 -- `caspal w1,w1,w2,w3,\[x5\]' [^:]*:70: *Info: macro .* @@ -157,1061 +157,1061 @@ [^:]*:70: *Info: macro .* [^:]*:49: Error: operand mismatch -- `caspal w0,x1,x2,x3,\[x2\]' [^:]*:70: *Info: macro .* -[^:]*:50: Error: 64-bit integer or SP register expected at operand 5 -- `caspal x4,x5,x6,x7,\[w8\]' +[^:]*:50: Error: expected a 64-bit base register at operand 5 -- `caspal x4,x5,x6,x7,\[w8\]' [^:]*:70: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldadd w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldadd w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldadd w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldadda w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldadda w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldadda w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldaddl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddl w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddl w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldaddal w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddal w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddal w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldaddb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldaddh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldaddab w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddab w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddab w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldaddlb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddlb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddlb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldaddalb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddalb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddalb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldaddah w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddah w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddah w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldaddlh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddlh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddlh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldaddalh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddalh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldaddalh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldadd w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldadd x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldadd x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldadda w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldadda x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldadda x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldaddl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddl x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldaddl x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldaddal w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddal x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldaddal x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldclr w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclr w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclr w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldclra w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclra w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclra w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldclrl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrl w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclrl w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldclral w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclral w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclral w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldclrb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclrb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldclrh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclrh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldclrab w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrab w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclrab w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldclrlb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrlb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclrlb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldclralb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclralb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclralb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldclrah w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrah w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclrah w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldclrlh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrlh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclrlh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldclralh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclralh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldclralh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldclr w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldclr x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldclr x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldclra w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldclra x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldclra x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldclrl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrl x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldclrl x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldclral w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldclral x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldclral x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldeor w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeor w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeor w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldeora w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeora w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeora w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldeorl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorl w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeorl w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldeoral w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoral w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeoral w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldeorb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeorb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldeorh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeorh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldeorab w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorab w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeorab w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldeorlb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorlb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeorlb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldeoralb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoralb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeoralb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldeorah w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorah w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeorah w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldeorlh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorlh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeorlh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldeoralh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoralh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldeoralh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldeor w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldeor x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldeor x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldeora w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldeora x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldeora x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldeorl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorl x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldeorl x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldeoral w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoral x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldeoral x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldset w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldset w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldset w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldseta w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldseta w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldseta w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsetl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetl w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetl w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsetal w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetal w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetal w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsetb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldseth w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldseth w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldseth w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsetab w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetab w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetab w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsetlb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetlb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetlb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsetalb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetalb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetalb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsetah w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetah w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetah w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsetlh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetlh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetlh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsetalh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetalh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsetalh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldset w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldset x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldset x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldseta w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldseta x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldseta x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldsetl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetl x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsetl x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldsetal w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetal x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsetal x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsmax w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmax w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmax w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsmaxa w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxa w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxa w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsmaxl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxl w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxl w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsmaxal w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxal w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxal w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsmaxb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsmaxh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsmaxab w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxab w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxab w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsmaxlb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxlb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxlb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsmaxalb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxalb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxalb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsmaxah w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxah w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxah w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsmaxlh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxlh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxlh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsmaxalh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxalh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmaxalh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldsmax w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmax x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsmax x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldsmaxa w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxa x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsmaxa x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldsmaxl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxl x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsmaxl x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldsmaxal w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxal x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsmaxal x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsmin w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmin w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmin w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsmina w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmina w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsmina w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsminl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminl w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminl w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsminal w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminal w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminal w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsminb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsminh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsminab w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminab w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminab w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsminlb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminlb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminlb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsminalb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminalb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminalb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsminah w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminah w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminah w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsminlh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminlh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminlh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldsminalh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminalh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldsminalh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldsmin w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmin x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsmin x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldsmina w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmina x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsmina x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldsminl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminl x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsminl x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldsminal w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminal x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldsminal x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldumax w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumax w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumax w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldumaxa w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxa w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxa w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldumaxl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxl w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxl w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldumaxal w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxal w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxal w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldumaxb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldumaxh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldumaxab w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxab w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxab w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldumaxlb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxlb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxlb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldumaxalb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxalb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxalb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldumaxah w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxah w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxah w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldumaxlh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxlh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxlh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldumaxalh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxalh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumaxalh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldumax w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumax x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldumax x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldumaxa w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxa x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldumaxa x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldumaxl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxl x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldumaxl x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldumaxal w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxal x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldumaxal x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldumin w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumin w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumin w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `ldumina w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumina w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `ldumina w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `lduminl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminl w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminl w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `lduminal w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminal w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminal w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `lduminb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `lduminh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `lduminab w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminab w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminab w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `lduminlb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminlb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminlb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `lduminalb w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminalb w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminalb w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `lduminah w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminah w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminah w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `lduminlh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminlh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminlh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:26: Error: operand mismatch -- `lduminalh w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminalh w2,w3,\[w4\]' +[^:]*:27: Error: expected a 64-bit base register at operand 3 -- `lduminalh w2,w3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldumin w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumin x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldumin x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `ldumina w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumina x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `ldumina x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `lduminl w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `lduminl x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `lduminl x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* [^:]*:30: Error: operand mismatch -- `lduminal w0,x1,\[x2\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `lduminal x2,x3,\[w4\]' +[^:]*:31: Error: expected a 64-bit base register at operand 3 -- `lduminal x2,x3,\[w4\]' [^:]*:56: *Info: macro .* [^:]*:71: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stadd w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stadd w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `staddl w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `staddl w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `staddb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `staddb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `staddb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `staddh x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `staddh w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `staddh w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `staddlb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `staddlb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `staddlb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `staddlh x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `staddlh w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `staddlh w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stadd x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stadd x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `staddl x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `staddl x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclr w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stclr w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclrl w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stclrl w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stclrb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclrb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stclrb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stclrh x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclrh w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stclrh w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stclrlb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclrlb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stclrlb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stclrlh x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclrlh w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stclrlh w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stclr x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stclr x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stclrl x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stclrl x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steor w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `steor w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steorl w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `steorl w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `steorb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steorb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `steorb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `steorh x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steorh w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `steorh w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `steorlb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steorlb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `steorlb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `steorlh x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steorlh w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `steorlh w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `steor x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `steor x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `steorl x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `steorl x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stset w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stset w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsetl w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsetl w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stsetb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsetb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsetb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stseth x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stseth w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stseth w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stsetlb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsetlb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsetlb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stsetlh x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsetlh w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsetlh w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stset x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stset x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stsetl x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stsetl x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmax w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsmax w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxl w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsmaxl w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stsmaxb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsmaxb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stsmaxh x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxh w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsmaxh w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stsmaxlb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxlb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsmaxlb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stsmaxlh x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxlh w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsmaxlh w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stsmax x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stsmax x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxl x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stsmaxl x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmin w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsmin w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsminl w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsminl w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stsminb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsminb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsminb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stsminh x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsminh w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsminh w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stsminlb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsminlb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsminlb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stsminlh x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsminlh w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stsminlh w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stsmin x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stsmin x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stsminl x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stsminl x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumax w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stumax w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxl w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stumaxl w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stumaxb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stumaxb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stumaxh x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxh w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stumaxh w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stumaxlb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxlb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stumaxlb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stumaxlh x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxlh w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stumaxlh w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stumax x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stumax x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxl x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stumaxl x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumin w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stumin w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stuminl w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stuminl w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stuminb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stuminb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stuminb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stuminh x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stuminh w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stuminh w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stuminlb x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stuminlb w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stuminlb w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* [^:]*:37: Error: operand mismatch -- `stuminlh x0,\[x2\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stuminlh w2,\[w3\]' +[^:]*:38: Error: expected a 64-bit base register at operand 2 -- `stuminlh w2,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stumin x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stumin x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* -[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stuminl x0,\[w3\]' +[^:]*:41: Error: expected a 64-bit base register at operand 2 -- `stuminl x0,\[w3\]' [^:]*:62: *Info: macro .* [^:]*:72: *Info: macro .* diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l index 67ec283..7e48f0a 100644 --- a/gas/testsuite/gas/aarch64/illegal-memtag.l +++ b/gas/testsuite/gas/aarch64/illegal-memtag.l @@ -34,22 +34,22 @@ [^:]*:[0-9]+: Error: operand 3 must be an integer or stack pointer register -- `subps x1,x2,xzr' [^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `cmpp xzr,x2' [^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `cmpp x2,xzr' -[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stg x2,\[xzr,#0\]' -[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `st2g x2,\[xzr,#0\]!' -[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stzg x2,\[xzr\],#0' -[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stz2g x2,\[xzr,#0\]' +[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stg x2,\[xzr,#0\]' +[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `st2g x2,\[xzr,#0\]!' +[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stzg x2,\[xzr\],#0' +[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stz2g x2,\[xzr,#0\]' [^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stg xzr,\[x2,#0\]' [^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `st2g xzr,\[x2,#0\]!' [^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stzg xzr,\[x2\],#0' [^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stz2g xzr,\[x2,#0\]' [^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]' [^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]' -[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]' +[^:]*:[0-9]+: Error: invalid base register at operand 3 -- `stgp x0,x0,\[xzr\]' [^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]' -[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldg x0,\[xzr,#16\]' -[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stzgm x0,\[xzr\]' +[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `ldg x0,\[xzr,#16\]' +[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stzgm x0,\[xzr\]' [^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stzgm sp,\[x3\]' -[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldgm x0,\[xzr\]' +[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `ldgm x0,\[xzr\]' [^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldgm sp,\[x3\]' -[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stgm x0,\[xzr\]' +[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stgm x0,\[xzr\]' [^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgm sp,\[x3\]' diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l index c3ef21a..6241de1 100644 --- a/gas/testsuite/gas/aarch64/illegal-sve2.l +++ b/gas/testsuite/gas/aarch64/illegal-sve2.l @@ -493,8 +493,8 @@ [^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\] [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1b {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.d},p8/z,\[z0\.d\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z32\.d\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z32\.d\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,x32\]' [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,w16\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,z0\.d\]' @@ -510,8 +510,8 @@ [^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\] [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1b {z32\.s},p0/z,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.s},p8/z,\[z0\.s\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z32\.s\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z32\.s\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,x32\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,z0\.s\]' [^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1d {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' @@ -520,8 +520,8 @@ [^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\] [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1d {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1d {z0\.d},p8/z,\[z0\.d\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z32\.d\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z32\.d\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,x32\]' [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,w16\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,z0\.d\]' @@ -540,8 +540,8 @@ [^ :]+:[0-9]+: Info: ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\] [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1h {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.d},p8/z,\[z0\.d\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z32\.d\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z32\.d\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,x32\]' [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,w16\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,z0\.d\]' @@ -551,8 +551,8 @@ [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1h {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1h {z32\.s},p0/z,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.s},p8/z,\[z0\.s\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z32\.s\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z32\.s\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,x32\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,z0\.s\]' [^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1sb {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' @@ -563,8 +563,8 @@ [^ :]+:[0-9]+: Info: ldnt1sb {z0\.s}, p0/z, \[z0\.s, xzr\] [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sb {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sb {z0\.d},p8/z,\[z0\.d\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z32\.d\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z32\.d\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,x32\]' [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,w16\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,z0\.d\]' @@ -576,8 +576,8 @@ [^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\] [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]' [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]' @@ -589,8 +589,8 @@ [^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\] [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]' [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]' @@ -600,8 +600,8 @@ [^ :]+:[0-9]+: Info: ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\] [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1w {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.d},p8/z,\[z0\.d\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z32\.d\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z32\.d\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,x32\]' [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,w16\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,z0\.d\]' @@ -611,8 +611,8 @@ [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1w {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1w {z32\.s},p0/z,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.s},p8/z,\[z0\.s\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z32\.s\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z32\.s\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,x32\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,z0\.s\]' [^ :]+:[0-9]+: Error: operand mismatch -- `match p0\.h,p0/z,z0\.b,z0\.b' @@ -2217,8 +2217,8 @@ [^ :]+:[0-9]+: Info: stnt1b {z0\.s}, p0, \[z0\.s, xzr\] [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1b {z32\.d},p0,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.d},p8,\[z0\.d\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1b {z0\.d},p0,\[z32\.d\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1b {z0\.d},p0,\[z32\.d\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,x32\]' [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,w16\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,z0\.d\]' @@ -2228,8 +2228,8 @@ [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1b {z0\.s,z1\.d},p0,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1b {z32\.s},p0,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.s},p8,\[z0\.s\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1b {z0\.s},p0,\[z32\.s\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1b {z0\.s},p0,\[z32\.s\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,x32\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,z0\.s\]' [^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1d {z0\.d,z1\.d},p0,\[z0\.d,x0\]' @@ -2238,8 +2238,8 @@ [^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d, xzr\] [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1d {z32\.d},p0,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1d {z0\.d},p8,\[z0\.d\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1d {z0\.d},p0,\[z32\.d\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1d {z0\.d},p0,\[z32\.d\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,x32\]' [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,w16\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,z0\.d\]' @@ -2252,8 +2252,8 @@ [^ :]+:[0-9]+: Info: stnt1h {z0\.s}, p0, \[z0\.s, xzr\] [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.d},p0,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.d},p8,\[z0\.d\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1h {z0\.d},p0,\[z32\.d\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1h {z0\.d},p0,\[z32\.d\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,x32\]' [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,w16\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,z0\.d\]' @@ -2263,8 +2263,8 @@ [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1h {z0\.s,z1\.d},p0,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.s},p0,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.s},p8,\[z0\.s\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1h {z0\.s},p0,\[z32\.s\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1h {z0\.s},p0,\[z32\.s\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,x32\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,z0\.s\]' [^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1w {z0\.d,z1\.d},p0,\[z0\.d,x0\]' @@ -2273,8 +2273,8 @@ [^ :]+:[0-9]+: Info: stnt1w {z0\.s}, p0, \[z0\.s, xzr\] [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1w {z32\.d},p0,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.d},p8,\[z0\.d\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1w {z0\.d},p0,\[z32\.d\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1w {z0\.d},p0,\[z32\.d\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,x32\]' [^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,w16\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,z0\.d\]' @@ -2284,8 +2284,8 @@ [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1w {z0\.s,z1\.d},p0,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1w {z32\.s},p0,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.s},p8,\[z0\.s\]' -[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1w {z0\.s},p0,\[z32\.s\]' -[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,sp\]' +[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1w {z0\.s},p0,\[z32\.s\]' +[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,sp\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,x32\]' [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,z0\.s\]' [^ :]+:[0-9]+: Error: operand mismatch -- `subhnb z0\.h,z0\.h,z0\.h' diff --git a/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l b/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l index b0ade28..34d6634 100644 --- a/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l +++ b/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l @@ -3,11 +3,11 @@ .*: Error: operand 3 must be a SIMD vector register -- `cmeq v0\.4s,v1\.4s,s0' .*: Error: immediate zero expected at operand 3 -- `cmeq v0\.4s,v1\.4s,p0\.b' .*: Error: immediate zero expected at operand 3 -- `cmeq v0\.4s,v1\.4s,#p0\.b' -.*: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[s0\]' -.*: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[z0\]' -.*: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[z0\.s\]' -.*: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[p0\]' -.*: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[p0\.b\]' +.*: Error: invalid base register at operand 2 -- `ldr x1,\[s0\]' +.*: Error: invalid base register at operand 2 -- `ldr x1,\[z0\]' +.*: Error: invalid base register at operand 2 -- `ldr x1,\[z0\.s\]' +.*: Error: invalid base register at operand 2 -- `ldr x1,\[p0\]' +.*: Error: invalid base register at operand 2 -- `ldr x1,\[p0\.b\]' .*: Error: invalid shift amount at operand 2 -- `ldr x0,\[x1,x2,lsl p0\.b\]' .*: Error: invalid shift amount at operand 2 -- `ldr x0,\[x1,x2,lsl#p0\.b\]' .*: Error: immediate out of range at operand 3 -- `and x0,x0,#x0' |