diff options
37 files changed, 1153 insertions, 23 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 92dbe68..aae16db 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,15 @@ +2003-09-30 Chris Demetriou <cgd@broadcom.com> + + * archures.c (bfd_mach_mipsisa64r2): New define. + * bfd-in2.h: Regenerate. + * aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2. + * cpu-mips.c (I_mipsisa64r2): New enum value. + (arch_info_struct): Add entry for I_mipsisa64r2. + * elfxx-mips.c (_bfd_elf_mips_mach) + (_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2. + (mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case. + (mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2. + 2003-09-29 H.J. Lu <hongjiu.lu@intel.com> * elfxx-ia64.c (elfNN_hpux_backend_symbol_processing): New. diff --git a/bfd/aoutx.h b/bfd/aoutx.h index 674fc76..3c49538 100644 --- a/bfd/aoutx.h +++ b/bfd/aoutx.h @@ -801,6 +801,7 @@ NAME(aout,machine_type) (arch, machine, unknown) case bfd_mach_mipsisa32r2: case bfd_mach_mips5: case bfd_mach_mipsisa64: + case bfd_mach_mipsisa64r2: case bfd_mach_mips_sb1: /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */ arch_flags = M_MIPS2; diff --git a/bfd/archures.c b/bfd/archures.c index 9033f28..c79e925 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -148,6 +148,7 @@ DESCRIPTION .#define bfd_mach_mipsisa32 32 .#define bfd_mach_mipsisa32r2 33 .#define bfd_mach_mipsisa64 64 +.#define bfd_mach_mipsisa64r2 65 . bfd_arch_i386, {* Intel 386 *} .#define bfd_mach_i386_i386 1 .#define bfd_mach_i386_i8086 2 diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index a7cca3e..d74fc1c 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1577,6 +1577,7 @@ enum bfd_architecture #define bfd_mach_mipsisa32 32 #define bfd_mach_mipsisa32r2 33 #define bfd_mach_mipsisa64 64 +#define bfd_mach_mipsisa64r2 65 bfd_arch_i386, /* Intel 386 */ #define bfd_mach_i386_i386 1 #define bfd_mach_i386_i8086 2 diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c index e64ee06..10d4e47 100644 --- a/bfd/cpu-mips.c +++ b/bfd/cpu-mips.c @@ -85,6 +85,7 @@ enum I_mipsisa32, I_mipsisa32r2, I_mipsisa64, + I_mipsisa64r2, I_sb1, }; @@ -116,6 +117,7 @@ static const bfd_arch_info_type arch_info_struct[] = N (32, 32, bfd_mach_mipsisa32, "mips:isa32", FALSE, NN(I_mipsisa32)), N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)), N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)), + N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)), N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0), }; diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c index 0063100..fa57295 100644 --- a/bfd/elfxx-mips.c +++ b/bfd/elfxx-mips.c @@ -4056,6 +4056,10 @@ _bfd_elf_mips_mach (flags) case E_MIPS_ARCH_32R2: return bfd_mach_mipsisa32r2; break; + + case E_MIPS_ARCH_64R2: + return bfd_mach_mipsisa64r2; + break; } } @@ -7192,6 +7196,10 @@ mips_set_isa_flags (abfd) case bfd_mach_mipsisa32r2: val = E_MIPS_ARCH_32R2; break; + + case bfd_mach_mipsisa64r2: + val = E_MIPS_ARCH_64R2; + break; } elf_elfheader (abfd)->e_flags &= ~(EF_MIPS_ARCH | EF_MIPS_MACH); elf_elfheader (abfd)->e_flags |= val; @@ -8929,6 +8937,7 @@ struct mips_mach_extension { static const struct mips_mach_extension mips_mach_extensions[] = { /* MIPS64 extensions. */ + { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 }, { bfd_mach_mips_sb1, bfd_mach_mipsisa64 }, /* MIPS V extensions. */ @@ -9275,6 +9284,8 @@ _bfd_mips_elf_print_private_bfd_data (abfd, ptr) fprintf (file, _(" [mips64]")); else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R2) fprintf (file, _(" [mips32r2]")); + else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64R2) + fprintf (file, _(" [mips64r2]")); else fprintf (file, _(" [unknown ISA]")); diff --git a/binutils/ChangeLog b/binutils/ChangeLog index ad5937a..72c1fd0 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,7 @@ +2003-09-30 Chris Demetriou <cgd@broadcom.com> + + * readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2. + 2003-09-29 H.J. Lu <hongjiu.lu@intel.com> * readelf.c (dump_relocations): Support SHN_IA_64_ANSI_COMMON. diff --git a/binutils/readelf.c b/binutils/readelf.c index 520b736..9a88106 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -1916,6 +1916,7 @@ get_machine_flags (unsigned e_flags, unsigned e_machine) case E_MIPS_ARCH_32: strcat (buf, ", mips32"); break; case E_MIPS_ARCH_32R2: strcat (buf, ", mips32r2"); break; case E_MIPS_ARCH_64: strcat (buf, ", mips64"); break; + case E_MIPS_ARCH_64R2: strcat (buf, ", mips64r2"); break; default: strcat (buf, ", unknown ISA"); break; } diff --git a/gas/ChangeLog b/gas/ChangeLog index e8666ad..def878b 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,24 @@ +2003-09-30 Chris Demetriou <cgd@broadcom.com> + + * configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs. + * configure: Regenerate. + * config/tc-mips.c (imm2_expr): New variable. + (md_assemble, mips16_ip): Initialize imm2_expr. + (ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2. + (macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands. + (macro): Handle M_DEXT and M_DINS. + (validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands. + (mips_ip): Likewise. + (OPTION_MIPS64R2): New define. + (md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2). + OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2. + (md_parse_option): Handle OPTION_MIPS64R2. + (s_mipsset): Handle setting "mips64r2" ISA. + (mips_cpu_info_table): Add mips64r2. + (md_show_usage): Document -mips64r2 option. + * doc/as.texinfo: Docuemnt -mips64r2 option. + * doc/c-mips.texi: Likewise. + 2003-09-27 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> * config/tc-hppa.c (pa_ip): Check for invalid 64-bit conditions. diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index e638883..25e5a3d 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -266,18 +266,20 @@ static int mips_32bitmode = 0; || (ISA) == ISA_MIPS4 \ || (ISA) == ISA_MIPS5 \ || (ISA) == ISA_MIPS64 \ + || (ISA) == ISA_MIPS64R2 \ ) /* Return true if ISA supports 64-bit right rotate (dror et al.) instructions. */ #define ISA_HAS_DROR(ISA) ( \ - 0 \ + (ISA) == ISA_MIPS64R2 \ ) /* Return true if ISA supports 32-bit right rotate (ror et al.) instructions. */ #define ISA_HAS_ROR(ISA) ( \ (ISA) == ISA_MIPS32R2 \ + || (ISA) == ISA_MIPS64R2 \ ) #define HAVE_32BIT_GPRS \ @@ -1025,6 +1027,7 @@ static char *expr_end; mips_ip. */ static expressionS imm_expr; +static expressionS imm2_expr; static expressionS offset_expr; /* Relocs associated with imm_expr and offset_expr. */ @@ -1323,6 +1326,7 @@ md_assemble (char *str) = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; imm_expr.X_op = O_absent; + imm2_expr.X_op = O_absent; offset_expr.X_op = O_absent; imm_reloc[0] = BFD_RELOC_UNUSED; imm_reloc[1] = BFD_RELOC_UNUSED; @@ -2872,6 +2876,41 @@ macro_build (char *place, int *counter, expressionS *ep, const char *name, case ')': continue; + case '+': + switch (*fmt++) + { + case 'A': + case 'E': + insn.insn_opcode |= (va_arg (args, int) + & OP_MASK_SHAMT) << OP_SH_SHAMT; + continue; + + case 'B': + case 'F': + /* Note that in the macro case, these arguments are already + in MSB form. (When handling the instruction in the + non-macro case, these arguments are sizes from which + MSB values must be calculated.) */ + insn.insn_opcode |= (va_arg (args, int) + & OP_MASK_INSMSB) << OP_SH_INSMSB; + continue; + + case 'C': + case 'G': + case 'H': + /* Note that in the macro case, these arguments are already + in MSBD form. (When handling the instruction in the + non-macro case, these arguments are sizes from which + MSBD values must be calculated.) */ + insn.insn_opcode |= (va_arg (args, int) + & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; + continue; + + default: + internalError (); + } + continue; + case 't': case 'w': case 'E': @@ -4437,6 +4476,104 @@ macro (struct mips_cl_insn *ip) "s,t,p", AT, 0); break; + case M_DEXT: + { + unsigned long pos; + unsigned long size; + + if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) + { + as_bad (_("Unsupported large constant")); + pos = size = 1; + } + else + { + pos = (unsigned long) imm_expr.X_add_number; + size = (unsigned long) imm2_expr.X_add_number; + } + + if (pos > 63) + { + as_bad (_("Improper position (%lu)"), pos); + pos = 1; + } + if (size == 0 || size > 64 + || (pos + size - 1) > 63) + { + as_bad (_("Improper extract size (%lu, position %lu)"), + size, pos); + size = 1; + } + + if (size <= 32 && pos < 32) + { + s = "dext"; + fmt = "t,r,+A,+C"; + } + else if (size <= 32) + { + s = "dextu"; + fmt = "t,r,+E,+H"; + } + else + { + s = "dextm"; + fmt = "t,r,+A,+G"; + } + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, + fmt, treg, sreg, pos, size - 1); + } + return; + + case M_DINS: + { + unsigned long pos; + unsigned long size; + + if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) + { + as_bad (_("Unsupported large constant")); + pos = size = 1; + } + else + { + pos = (unsigned long) imm_expr.X_add_number; + size = (unsigned long) imm2_expr.X_add_number; + } + + if (pos > 63) + { + as_bad (_("Improper position (%lu)"), pos); + pos = 1; + } + if (size == 0 || size > 64 + || (pos + size - 1) > 63) + { + as_bad (_("Improper insert size (%lu, position %lu)"), + size, pos); + size = 1; + } + + if (pos < 32 && (pos + size - 1) < 32) + { + s = "dins"; + fmt = "t,r,+A,+B"; + } + else if (pos >= 32) + { + s = "dinsu"; + fmt = "t,r,+E,+F"; + } + else + { + s = "dinsm"; + fmt = "t,r,+A,+F"; + } + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, + fmt, treg, sreg, pos, pos + size - 1); + } + return; + case M_DDIV_3: dbl = 1; case M_DIV_3: @@ -8060,6 +8197,11 @@ validate_mips_insn (const struct mips_opcode *opc) case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; + case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; + case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; + case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; + case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; + case 'I': break; default: as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), c, opc->name, opc->args); @@ -8319,6 +8461,12 @@ mips_ip (char *str, struct mips_cl_insn *ip) case 'A': /* ins/ext position, becomes LSB. */ limlo = 0; limhi = 31; + goto do_lsb; + case 'E': + limlo = 32; + limhi = 63; + goto do_lsb; +do_lsb: my_getExpression (&imm_expr, s); check_absolute_expr (ip, &imm_expr); if ((unsigned long) imm_expr.X_add_number < limlo @@ -8338,6 +8486,12 @@ mips_ip (char *str, struct mips_cl_insn *ip) case 'B': /* ins size, becomes MSB. */ limlo = 1; limhi = 32; + goto do_msb; + case 'F': + limlo = 33; + limhi = 64; + goto do_msb; +do_msb: my_getExpression (&imm_expr, s); check_absolute_expr (ip, &imm_expr); /* Check for negative input so that small negative numbers @@ -8364,6 +8518,16 @@ mips_ip (char *str, struct mips_cl_insn *ip) case 'C': /* ext size, becomes MSBD. */ limlo = 1; limhi = 32; + goto do_msbd; + case 'G': + limlo = 33; + limhi = 64; + goto do_msbd; + case 'H': + limlo = 33; + limhi = 64; + goto do_msbd; +do_msbd: my_getExpression (&imm_expr, s); check_absolute_expr (ip, &imm_expr); /* Check for negative input so that small negative numbers @@ -8391,6 +8555,15 @@ mips_ip (char *str, struct mips_cl_insn *ip) /* +D is for disassembly only; never match. */ break; + case 'I': + /* "+I" is like "I", except that imm2_expr is used. */ + my_getExpression (&imm2_expr, s); + if (imm2_expr.X_op != O_big + && imm2_expr.X_op != O_constant) + insn_error = _("absolute expression required"); + s = expr_end; + continue; + default: as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), *args, insn->name, insn->args); @@ -9358,6 +9531,7 @@ mips16_ip (char *str, struct mips_cl_insn *ip) imm_reloc[0] = BFD_RELOC_UNUSED; imm_reloc[1] = BFD_RELOC_UNUSED; imm_reloc[2] = BFD_RELOC_UNUSED; + imm2_expr.X_op = O_absent; offset_expr.X_op = O_absent; offset_reloc[0] = BFD_RELOC_UNUSED; offset_reloc[1] = BFD_RELOC_UNUSED; @@ -10256,9 +10430,11 @@ struct option md_longopts[] = {"mips64", no_argument, NULL, OPTION_MIPS64}, #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, +#define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) + {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, /* Options which specify Application Specific Extensions (ASEs). */ -#define OPTION_ASE_BASE (OPTION_ARCH_BASE + 10) +#define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) {"mips16", no_argument, NULL, OPTION_MIPS16}, #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) @@ -10463,6 +10639,10 @@ md_parse_option (int c, char *arg) file_mips_isa = ISA_MIPS32R2; break; + case OPTION_MIPS64R2: + file_mips_isa = ISA_MIPS64R2; + break; + case OPTION_MIPS64: file_mips_isa = ISA_MIPS64; break; @@ -12020,6 +12200,8 @@ s_mipsset (int x ATTRIBUTE_UNUSED) mips_opts.isa = ISA_MIPS32R2; else if (strcmp (name, "mips64") == 0) mips_opts.isa = ISA_MIPS64; + else if (strcmp (name, "mips64r2") == 0) + mips_opts.isa = ISA_MIPS64R2; else if (strcmp (name, "arch=default") == 0) { reset = 1; @@ -12057,6 +12239,7 @@ s_mipsset (int x ATTRIBUTE_UNUSED) case ISA_MIPS4: case ISA_MIPS5: case ISA_MIPS64: + case ISA_MIPS64R2: mips_opts.gp32 = 0; mips_opts.fp32 = 0; break; @@ -14302,6 +14485,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, + { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, /* MIPS I */ { "r3000", 0, ISA_MIPS1, CPU_R3000 }, @@ -14533,6 +14717,7 @@ MIPS options:\n\ -mips32 generate MIPS32 ISA instructions\n\ -mips32r2 generate MIPS32 release 2 ISA instructions\n\ -mips64 generate MIPS64 ISA instructions\n\ +-mips64r2 generate MIPS64 release 2 ISA instructions\n\ -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); first = 1; diff --git a/gas/configure b/gas/configure index b389a1c..62e6c9b 100755 --- a/gas/configure +++ b/gas/configure @@ -4411,13 +4411,16 @@ _ACEOF mipsisa64 | mipsisa64el) mips_cpu=mips64 ;; + mipsisa64r2 | mipsisa64r2el) + mips_cpu=mips64r2 + ;; mipstx39 | mipstx39el) mips_cpu=r3900 ;; mips64vr | mips64vrel) mips_cpu=vr4100 ;; - mipsisa32r2*) + mipsisa32r2* | mipsisa64r2*) mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'` ;; mips64* | mipsisa64* | mipsisa32*) diff --git a/gas/configure.in b/gas/configure.in index 9946a67..ec34939 100644 --- a/gas/configure.in +++ b/gas/configure.in @@ -556,13 +556,16 @@ changequote([,])dnl mipsisa64 | mipsisa64el) mips_cpu=mips64 ;; + mipsisa64r2 | mipsisa64r2el) + mips_cpu=mips64r2 + ;; mipstx39 | mipstx39el) mips_cpu=r3900 ;; mips64vr | mips64vrel) mips_cpu=vr4100 ;; - mipsisa32r2*) + mipsisa32r2* | mipsisa64r2*) changequote(,)dnl mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'` changequote([,])dnl diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index 9f7a21f..f7b4085 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -391,7 +391,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{-mabi}=@var{ABI}] [@b{-32}] [@b{-n32}] [@b{-64}] [@b{-mfp32}] [@b{-mgp32}] [@b{-march}=@var{CPU}] [@b{-mtune}=@var{CPU}] [@b{-mips1}] [@b{-mips2}] [@b{-mips3}] [@b{-mips4}] [@b{-mips5}] [@b{-mips32}] [@b{-mips32r2}] - [@b{-mips64}] + [@b{-mips64}] [@b{-mips64r2}] [@b{-construct-floats}] [@b{-no-construct-floats}] [@b{-trap}] [@b{-no-break}] [@b{-break}] [@b{-no-trap}] [@b{-mfix7000}] [@b{-mno-fix7000}] @@ -927,15 +927,17 @@ Generate ``little endian'' format output. @itemx -mips32 @itemx -mips32r2 @itemx -mips64 +@itemx -mips64r2 Generate code for a particular @sc{mips} Instruction Set Architecture level. @samp{-mips1} is an alias for @samp{-march=r3000}, @samp{-mips2} is an alias for @samp{-march=r6000}, @samp{-mips3} is an alias for @samp{-march=r4000} and @samp{-mips4} is an alias for @samp{-march=r8000}. -@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, and @samp{-mips64} +@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and +@samp{-mips64r2} correspond to generic -@samp{MIPS V}, @samp{MIPS32}, @samp{MIPS32 Release 2}, and -@samp{MIPS64} ISA processors, -respectively. +@samp{MIPS V}, @samp{MIPS32}, @samp{MIPS32 Release 2}, @samp{MIPS64}, +and @samp{MIPS64 Release 2} +ISA processors, respectively. @item -march=@var{CPU} Generate code for a particular @sc{mips} cpu. diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index 4da7b25..6f8b737 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -67,14 +67,17 @@ to select big-endian output, and @samp{-EL} for little-endian. @itemx -mips32 @itemx -mips32r2 @itemx -mips64 +@itemx -mips64r2 Generate code for a particular MIPS Instruction Set Architecture level. @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and -@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, and -@samp{-mips64} correspond to generic @sc{MIPS V}, @sc{MIPS32}, -@sc{MIPS32 Release 2}, and -@sc{MIPS64} ISA processors, respectively. You can also switch +@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, +@samp{-mips64}, and @samp{-mips64r2} +correspond to generic +@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64}, +and @sc{MIPS64 Release 2} +ISA processors, respectively. You can also switch instruction sets during the assembly; see @ref{MIPS ISA, Directives to override the ISA level}. @@ -294,7 +297,8 @@ assembly language programmers! @kindex @code{.set mips@var{n}} @sc{gnu} @code{@value{AS}} supports an additional directive to change the @sc{mips} Instruction Set Architecture level on the fly: @code{.set -mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, or 64. +mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 +or 64r2. The values other than 0 make the assembler accept instructions for the corresponding @sc{isa} level, from that point on in the assembly. @code{.set mips@var{n}} affects not only which instructions diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 22e8ec3..0b9887d 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,17 @@ +2003-09-30 Chris Demetriou <cgd@broadcom.com> + + * gas/mips/cp0-names-mips64r2.d: New file. + * gas/mips/cp0sel-names-mips64r2.d: New file. + * gas/mips/elf_arch_mips64r2.d: New file. + * gas/mips/hwr-names-mips64r2.d: New file. + * gas/mips/mips32r2-ill-fp64.l: New file. + * gas/mips/mips32r2-ill-fp64.s: New file. + * gas/mips/mips64r2-ill.l: New file. + * gas/mips/mips64r2-ill.s: New file. + * gas/mips/mips64r2.d: New file. + * gas/mips/mips64r2.s: New file. + * gas/mips/mips.exp: Define "mips64r2" arch, and run new tests. + 2003-09-29 Dave Brolley <brolley@redhat.com> * gas/frv/allinsn.s (nldqi): Removed. Replaced with nop. diff --git a/gas/testsuite/gas/mips/cp0-names-mips64r2.d b/gas/testsuite/gas/mips/cp0-names-mips64r2.d new file mode 100644 index 0000000..764156e --- /dev/null +++ b/gas/testsuite/gas/mips/cp0-names-mips64r2.d @@ -0,0 +1,42 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp0-names=mips64r2 +#name: MIPS CP0 register disassembly (mips64r2) +#source: cp0-names.s + +# Check objdump's handling of -M cp0-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 40800000 mtc0 \$0,c0_index +0+0004 <[^>]*> 40800800 mtc0 \$0,c0_random +0+0008 <[^>]*> 40801000 mtc0 \$0,c0_entrylo0 +0+000c <[^>]*> 40801800 mtc0 \$0,c0_entrylo1 +0+0010 <[^>]*> 40802000 mtc0 \$0,c0_context +0+0014 <[^>]*> 40802800 mtc0 \$0,c0_pagemask +0+0018 <[^>]*> 40803000 mtc0 \$0,c0_wired +0+001c <[^>]*> 40803800 mtc0 \$0,c0_hwrena +0+0020 <[^>]*> 40804000 mtc0 \$0,c0_badvaddr +0+0024 <[^>]*> 40804800 mtc0 \$0,c0_count +0+0028 <[^>]*> 40805000 mtc0 \$0,c0_entryhi +0+002c <[^>]*> 40805800 mtc0 \$0,c0_compare +0+0030 <[^>]*> 40806000 mtc0 \$0,c0_status +0+0034 <[^>]*> 40806800 mtc0 \$0,c0_cause +0+0038 <[^>]*> 40807000 mtc0 \$0,c0_epc +0+003c <[^>]*> 40807800 mtc0 \$0,c0_prid +0+0040 <[^>]*> 40808000 mtc0 \$0,c0_config +0+0044 <[^>]*> 40808800 mtc0 \$0,c0_lladdr +0+0048 <[^>]*> 40809000 mtc0 \$0,c0_watchlo +0+004c <[^>]*> 40809800 mtc0 \$0,c0_watchhi +0+0050 <[^>]*> 4080a000 mtc0 \$0,c0_xcontext +0+0054 <[^>]*> 4080a800 mtc0 \$0,\$21 +0+0058 <[^>]*> 4080b000 mtc0 \$0,\$22 +0+005c <[^>]*> 4080b800 mtc0 \$0,c0_debug +0+0060 <[^>]*> 4080c000 mtc0 \$0,c0_depc +0+0064 <[^>]*> 4080c800 mtc0 \$0,c0_perfcnt +0+0068 <[^>]*> 4080d000 mtc0 \$0,c0_errctl +0+006c <[^>]*> 4080d800 mtc0 \$0,c0_cacheerr +0+0070 <[^>]*> 4080e000 mtc0 \$0,c0_taglo +0+0074 <[^>]*> 4080e800 mtc0 \$0,c0_taghi +0+0078 <[^>]*> 4080f000 mtc0 \$0,c0_errorepc +0+007c <[^>]*> 4080f800 mtc0 \$0,c0_desave + \.\.\. diff --git a/gas/testsuite/gas/mips/cp0sel-names-mips64r2.d b/gas/testsuite/gas/mips/cp0sel-names-mips64r2.d new file mode 100644 index 0000000..9222800 --- /dev/null +++ b/gas/testsuite/gas/mips/cp0sel-names-mips64r2.d @@ -0,0 +1,235 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa32 -M gpr-names=numeric,cp0-names=mips64r2 +#name: MIPS CP0 with sel register disassembly (mips64r2) +#as: -32 -march=mips32 +#source: cp0sel-names.s + +# Check objdump's handling of -M cp0-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 40800001 mtc0 \$0,\$0,1 +0+0004 <[^>]*> 40800002 mtc0 \$0,\$0,2 +0+0008 <[^>]*> 40800003 mtc0 \$0,\$0,3 +0+000c <[^>]*> 40800004 mtc0 \$0,\$0,4 +0+0010 <[^>]*> 40800005 mtc0 \$0,\$0,5 +0+0014 <[^>]*> 40800006 mtc0 \$0,\$0,6 +0+0018 <[^>]*> 40800007 mtc0 \$0,\$0,7 +0+001c <[^>]*> 40800801 mtc0 \$0,\$1,1 +0+0020 <[^>]*> 40800802 mtc0 \$0,\$1,2 +0+0024 <[^>]*> 40800803 mtc0 \$0,\$1,3 +0+0028 <[^>]*> 40800804 mtc0 \$0,\$1,4 +0+002c <[^>]*> 40800805 mtc0 \$0,\$1,5 +0+0030 <[^>]*> 40800806 mtc0 \$0,\$1,6 +0+0034 <[^>]*> 40800807 mtc0 \$0,\$1,7 +0+0038 <[^>]*> 40801001 mtc0 \$0,\$2,1 +0+003c <[^>]*> 40801002 mtc0 \$0,\$2,2 +0+0040 <[^>]*> 40801003 mtc0 \$0,\$2,3 +0+0044 <[^>]*> 40801004 mtc0 \$0,\$2,4 +0+0048 <[^>]*> 40801005 mtc0 \$0,\$2,5 +0+004c <[^>]*> 40801006 mtc0 \$0,\$2,6 +0+0050 <[^>]*> 40801007 mtc0 \$0,\$2,7 +0+0054 <[^>]*> 40801801 mtc0 \$0,\$3,1 +0+0058 <[^>]*> 40801802 mtc0 \$0,\$3,2 +0+005c <[^>]*> 40801803 mtc0 \$0,\$3,3 +0+0060 <[^>]*> 40801804 mtc0 \$0,\$3,4 +0+0064 <[^>]*> 40801805 mtc0 \$0,\$3,5 +0+0068 <[^>]*> 40801806 mtc0 \$0,\$3,6 +0+006c <[^>]*> 40801807 mtc0 \$0,\$3,7 +0+0070 <[^>]*> 40802001 mtc0 \$0,c0_contextconfig +0+0074 <[^>]*> 40802002 mtc0 \$0,\$4,2 +0+0078 <[^>]*> 40802003 mtc0 \$0,\$4,3 +0+007c <[^>]*> 40802004 mtc0 \$0,\$4,4 +0+0080 <[^>]*> 40802005 mtc0 \$0,\$4,5 +0+0084 <[^>]*> 40802006 mtc0 \$0,\$4,6 +0+0088 <[^>]*> 40802007 mtc0 \$0,\$4,7 +0+008c <[^>]*> 40802801 mtc0 \$0,c0_pagegrain +0+0090 <[^>]*> 40802802 mtc0 \$0,\$5,2 +0+0094 <[^>]*> 40802803 mtc0 \$0,\$5,3 +0+0098 <[^>]*> 40802804 mtc0 \$0,\$5,4 +0+009c <[^>]*> 40802805 mtc0 \$0,\$5,5 +0+00a0 <[^>]*> 40802806 mtc0 \$0,\$5,6 +0+00a4 <[^>]*> 40802807 mtc0 \$0,\$5,7 +0+00a8 <[^>]*> 40803001 mtc0 \$0,\$6,1 +0+00ac <[^>]*> 40803002 mtc0 \$0,\$6,2 +0+00b0 <[^>]*> 40803003 mtc0 \$0,\$6,3 +0+00b4 <[^>]*> 40803004 mtc0 \$0,\$6,4 +0+00b8 <[^>]*> 40803005 mtc0 \$0,\$6,5 +0+00bc <[^>]*> 40803006 mtc0 \$0,\$6,6 +0+00c0 <[^>]*> 40803007 mtc0 \$0,\$6,7 +0+00c4 <[^>]*> 40803801 mtc0 \$0,\$7,1 +0+00c8 <[^>]*> 40803802 mtc0 \$0,\$7,2 +0+00cc <[^>]*> 40803803 mtc0 \$0,\$7,3 +0+00d0 <[^>]*> 40803804 mtc0 \$0,\$7,4 +0+00d4 <[^>]*> 40803805 mtc0 \$0,\$7,5 +0+00d8 <[^>]*> 40803806 mtc0 \$0,\$7,6 +0+00dc <[^>]*> 40803807 mtc0 \$0,\$7,7 +0+00e0 <[^>]*> 40804001 mtc0 \$0,\$8,1 +0+00e4 <[^>]*> 40804002 mtc0 \$0,\$8,2 +0+00e8 <[^>]*> 40804003 mtc0 \$0,\$8,3 +0+00ec <[^>]*> 40804004 mtc0 \$0,\$8,4 +0+00f0 <[^>]*> 40804005 mtc0 \$0,\$8,5 +0+00f4 <[^>]*> 40804006 mtc0 \$0,\$8,6 +0+00f8 <[^>]*> 40804007 mtc0 \$0,\$8,7 +0+00fc <[^>]*> 40804801 mtc0 \$0,\$9,1 +0+0100 <[^>]*> 40804802 mtc0 \$0,\$9,2 +0+0104 <[^>]*> 40804803 mtc0 \$0,\$9,3 +0+0108 <[^>]*> 40804804 mtc0 \$0,\$9,4 +0+010c <[^>]*> 40804805 mtc0 \$0,\$9,5 +0+0110 <[^>]*> 40804806 mtc0 \$0,\$9,6 +0+0114 <[^>]*> 40804807 mtc0 \$0,\$9,7 +0+0118 <[^>]*> 40805001 mtc0 \$0,\$10,1 +0+011c <[^>]*> 40805002 mtc0 \$0,\$10,2 +0+0120 <[^>]*> 40805003 mtc0 \$0,\$10,3 +0+0124 <[^>]*> 40805004 mtc0 \$0,\$10,4 +0+0128 <[^>]*> 40805005 mtc0 \$0,\$10,5 +0+012c <[^>]*> 40805006 mtc0 \$0,\$10,6 +0+0130 <[^>]*> 40805007 mtc0 \$0,\$10,7 +0+0134 <[^>]*> 40805801 mtc0 \$0,\$11,1 +0+0138 <[^>]*> 40805802 mtc0 \$0,\$11,2 +0+013c <[^>]*> 40805803 mtc0 \$0,\$11,3 +0+0140 <[^>]*> 40805804 mtc0 \$0,\$11,4 +0+0144 <[^>]*> 40805805 mtc0 \$0,\$11,5 +0+0148 <[^>]*> 40805806 mtc0 \$0,\$11,6 +0+014c <[^>]*> 40805807 mtc0 \$0,\$11,7 +0+0150 <[^>]*> 40806001 mtc0 \$0,c0_intctl +0+0154 <[^>]*> 40806002 mtc0 \$0,c0_srsctl +0+0158 <[^>]*> 40806003 mtc0 \$0,c0_srsmap +0+015c <[^>]*> 40806004 mtc0 \$0,\$12,4 +0+0160 <[^>]*> 40806005 mtc0 \$0,\$12,5 +0+0164 <[^>]*> 40806006 mtc0 \$0,\$12,6 +0+0168 <[^>]*> 40806007 mtc0 \$0,\$12,7 +0+016c <[^>]*> 40806801 mtc0 \$0,\$13,1 +0+0170 <[^>]*> 40806802 mtc0 \$0,\$13,2 +0+0174 <[^>]*> 40806803 mtc0 \$0,\$13,3 +0+0178 <[^>]*> 40806804 mtc0 \$0,\$13,4 +0+017c <[^>]*> 40806805 mtc0 \$0,\$13,5 +0+0180 <[^>]*> 40806806 mtc0 \$0,\$13,6 +0+0184 <[^>]*> 40806807 mtc0 \$0,\$13,7 +0+0188 <[^>]*> 40807001 mtc0 \$0,\$14,1 +0+018c <[^>]*> 40807002 mtc0 \$0,\$14,2 +0+0190 <[^>]*> 40807003 mtc0 \$0,\$14,3 +0+0194 <[^>]*> 40807004 mtc0 \$0,\$14,4 +0+0198 <[^>]*> 40807005 mtc0 \$0,\$14,5 +0+019c <[^>]*> 40807006 mtc0 \$0,\$14,6 +0+01a0 <[^>]*> 40807007 mtc0 \$0,\$14,7 +0+01a4 <[^>]*> 40807801 mtc0 \$0,c0_ebase +0+01a8 <[^>]*> 40807802 mtc0 \$0,\$15,2 +0+01ac <[^>]*> 40807803 mtc0 \$0,\$15,3 +0+01b0 <[^>]*> 40807804 mtc0 \$0,\$15,4 +0+01b4 <[^>]*> 40807805 mtc0 \$0,\$15,5 +0+01b8 <[^>]*> 40807806 mtc0 \$0,\$15,6 +0+01bc <[^>]*> 40807807 mtc0 \$0,\$15,7 +0+01c0 <[^>]*> 40808001 mtc0 \$0,c0_config1 +0+01c4 <[^>]*> 40808002 mtc0 \$0,c0_config2 +0+01c8 <[^>]*> 40808003 mtc0 \$0,c0_config3 +0+01cc <[^>]*> 40808004 mtc0 \$0,\$16,4 +0+01d0 <[^>]*> 40808005 mtc0 \$0,\$16,5 +0+01d4 <[^>]*> 40808006 mtc0 \$0,\$16,6 +0+01d8 <[^>]*> 40808007 mtc0 \$0,\$16,7 +0+01dc <[^>]*> 40808801 mtc0 \$0,\$17,1 +0+01e0 <[^>]*> 40808802 mtc0 \$0,\$17,2 +0+01e4 <[^>]*> 40808803 mtc0 \$0,\$17,3 +0+01e8 <[^>]*> 40808804 mtc0 \$0,\$17,4 +0+01ec <[^>]*> 40808805 mtc0 \$0,\$17,5 +0+01f0 <[^>]*> 40808806 mtc0 \$0,\$17,6 +0+01f4 <[^>]*> 40808807 mtc0 \$0,\$17,7 +0+01f8 <[^>]*> 40809001 mtc0 \$0,c0_watchlo,1 +0+01fc <[^>]*> 40809002 mtc0 \$0,c0_watchlo,2 +0+0200 <[^>]*> 40809003 mtc0 \$0,c0_watchlo,3 +0+0204 <[^>]*> 40809004 mtc0 \$0,c0_watchlo,4 +0+0208 <[^>]*> 40809005 mtc0 \$0,c0_watchlo,5 +0+020c <[^>]*> 40809006 mtc0 \$0,c0_watchlo,6 +0+0210 <[^>]*> 40809007 mtc0 \$0,c0_watchlo,7 +0+0214 <[^>]*> 40809801 mtc0 \$0,c0_watchhi,1 +0+0218 <[^>]*> 40809802 mtc0 \$0,c0_watchhi,2 +0+021c <[^>]*> 40809803 mtc0 \$0,c0_watchhi,3 +0+0220 <[^>]*> 40809804 mtc0 \$0,c0_watchhi,4 +0+0224 <[^>]*> 40809805 mtc0 \$0,c0_watchhi,5 +0+0228 <[^>]*> 40809806 mtc0 \$0,c0_watchhi,6 +0+022c <[^>]*> 40809807 mtc0 \$0,c0_watchhi,7 +0+0230 <[^>]*> 4080a001 mtc0 \$0,\$20,1 +0+0234 <[^>]*> 4080a002 mtc0 \$0,\$20,2 +0+0238 <[^>]*> 4080a003 mtc0 \$0,\$20,3 +0+023c <[^>]*> 4080a004 mtc0 \$0,\$20,4 +0+0240 <[^>]*> 4080a005 mtc0 \$0,\$20,5 +0+0244 <[^>]*> 4080a006 mtc0 \$0,\$20,6 +0+0248 <[^>]*> 4080a007 mtc0 \$0,\$20,7 +0+024c <[^>]*> 4080a801 mtc0 \$0,\$21,1 +0+0250 <[^>]*> 4080a802 mtc0 \$0,\$21,2 +0+0254 <[^>]*> 4080a803 mtc0 \$0,\$21,3 +0+0258 <[^>]*> 4080a804 mtc0 \$0,\$21,4 +0+025c <[^>]*> 4080a805 mtc0 \$0,\$21,5 +0+0260 <[^>]*> 4080a806 mtc0 \$0,\$21,6 +0+0264 <[^>]*> 4080a807 mtc0 \$0,\$21,7 +0+0268 <[^>]*> 4080b001 mtc0 \$0,\$22,1 +0+026c <[^>]*> 4080b002 mtc0 \$0,\$22,2 +0+0270 <[^>]*> 4080b003 mtc0 \$0,\$22,3 +0+0274 <[^>]*> 4080b004 mtc0 \$0,\$22,4 +0+0278 <[^>]*> 4080b005 mtc0 \$0,\$22,5 +0+027c <[^>]*> 4080b006 mtc0 \$0,\$22,6 +0+0280 <[^>]*> 4080b007 mtc0 \$0,\$22,7 +0+0284 <[^>]*> 4080b801 mtc0 \$0,c0_tracecontrol +0+0288 <[^>]*> 4080b802 mtc0 \$0,c0_tracecontrol2 +0+028c <[^>]*> 4080b803 mtc0 \$0,c0_usertracedata +0+0290 <[^>]*> 4080b804 mtc0 \$0,c0_tracebpc +0+0294 <[^>]*> 4080b805 mtc0 \$0,\$23,5 +0+0298 <[^>]*> 4080b806 mtc0 \$0,\$23,6 +0+029c <[^>]*> 4080b807 mtc0 \$0,\$23,7 +0+02a0 <[^>]*> 4080c001 mtc0 \$0,\$24,1 +0+02a4 <[^>]*> 4080c002 mtc0 \$0,\$24,2 +0+02a8 <[^>]*> 4080c003 mtc0 \$0,\$24,3 +0+02ac <[^>]*> 4080c004 mtc0 \$0,\$24,4 +0+02b0 <[^>]*> 4080c005 mtc0 \$0,\$24,5 +0+02b4 <[^>]*> 4080c006 mtc0 \$0,\$24,6 +0+02b8 <[^>]*> 4080c007 mtc0 \$0,\$24,7 +0+02bc <[^>]*> 4080c801 mtc0 \$0,c0_perfcnt,1 +0+02c0 <[^>]*> 4080c802 mtc0 \$0,c0_perfcnt,2 +0+02c4 <[^>]*> 4080c803 mtc0 \$0,c0_perfcnt,3 +0+02c8 <[^>]*> 4080c804 mtc0 \$0,c0_perfcnt,4 +0+02cc <[^>]*> 4080c805 mtc0 \$0,c0_perfcnt,5 +0+02d0 <[^>]*> 4080c806 mtc0 \$0,c0_perfcnt,6 +0+02d4 <[^>]*> 4080c807 mtc0 \$0,c0_perfcnt,7 +0+02d8 <[^>]*> 4080d001 mtc0 \$0,\$26,1 +0+02dc <[^>]*> 4080d002 mtc0 \$0,\$26,2 +0+02e0 <[^>]*> 4080d003 mtc0 \$0,\$26,3 +0+02e4 <[^>]*> 4080d004 mtc0 \$0,\$26,4 +0+02e8 <[^>]*> 4080d005 mtc0 \$0,\$26,5 +0+02ec <[^>]*> 4080d006 mtc0 \$0,\$26,6 +0+02f0 <[^>]*> 4080d007 mtc0 \$0,\$26,7 +0+02f4 <[^>]*> 4080d801 mtc0 \$0,c0_cacheerr,1 +0+02f8 <[^>]*> 4080d802 mtc0 \$0,c0_cacheerr,2 +0+02fc <[^>]*> 4080d803 mtc0 \$0,c0_cacheerr,3 +0+0300 <[^>]*> 4080d804 mtc0 \$0,\$27,4 +0+0304 <[^>]*> 4080d805 mtc0 \$0,\$27,5 +0+0308 <[^>]*> 4080d806 mtc0 \$0,\$27,6 +0+030c <[^>]*> 4080d807 mtc0 \$0,\$27,7 +0+0310 <[^>]*> 4080e001 mtc0 \$0,c0_datalo +0+0314 <[^>]*> 4080e002 mtc0 \$0,c0_taglo1 +0+0318 <[^>]*> 4080e003 mtc0 \$0,c0_datalo1 +0+031c <[^>]*> 4080e004 mtc0 \$0,c0_taglo2 +0+0320 <[^>]*> 4080e005 mtc0 \$0,c0_datalo2 +0+0324 <[^>]*> 4080e006 mtc0 \$0,c0_taglo3 +0+0328 <[^>]*> 4080e007 mtc0 \$0,c0_datalo3 +0+032c <[^>]*> 4080e801 mtc0 \$0,c0_datahi +0+0330 <[^>]*> 4080e802 mtc0 \$0,c0_taghi1 +0+0334 <[^>]*> 4080e803 mtc0 \$0,c0_datahi1 +0+0338 <[^>]*> 4080e804 mtc0 \$0,c0_taghi2 +0+033c <[^>]*> 4080e805 mtc0 \$0,c0_datahi2 +0+0340 <[^>]*> 4080e806 mtc0 \$0,c0_taghi3 +0+0344 <[^>]*> 4080e807 mtc0 \$0,c0_datahi3 +0+0348 <[^>]*> 4080f001 mtc0 \$0,\$30,1 +0+034c <[^>]*> 4080f002 mtc0 \$0,\$30,2 +0+0350 <[^>]*> 4080f003 mtc0 \$0,\$30,3 +0+0354 <[^>]*> 4080f004 mtc0 \$0,\$30,4 +0+0358 <[^>]*> 4080f005 mtc0 \$0,\$30,5 +0+035c <[^>]*> 4080f006 mtc0 \$0,\$30,6 +0+0360 <[^>]*> 4080f007 mtc0 \$0,\$30,7 +0+0364 <[^>]*> 4080f801 mtc0 \$0,\$31,1 +0+0368 <[^>]*> 4080f802 mtc0 \$0,\$31,2 +0+036c <[^>]*> 4080f803 mtc0 \$0,\$31,3 +0+0370 <[^>]*> 4080f804 mtc0 \$0,\$31,4 +0+0374 <[^>]*> 4080f805 mtc0 \$0,\$31,5 +0+0378 <[^>]*> 4080f806 mtc0 \$0,\$31,6 +0+037c <[^>]*> 4080f807 mtc0 \$0,\$31,7 + \.\.\. diff --git a/gas/testsuite/gas/mips/elf_arch_mips64r2.d b/gas/testsuite/gas/mips/elf_arch_mips64r2.d new file mode 100644 index 0000000..aa318ce --- /dev/null +++ b/gas/testsuite/gas/mips/elf_arch_mips64r2.d @@ -0,0 +1,8 @@ +# name: ELF MIPS64r2 markings +# source: empty.s +# objdump: -p +# as: -march=mips64r2 + +.*:.*file format.*elf.*mips.* +private flags = 8.......: .*\[mips64r2\].* + diff --git a/gas/testsuite/gas/mips/hwr-names-mips64r2.d b/gas/testsuite/gas/mips/hwr-names-mips64r2.d new file mode 100644 index 0000000..a26559c --- /dev/null +++ b/gas/testsuite/gas/mips/hwr-names-mips64r2.d @@ -0,0 +1,43 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa32r2 -M gpr-names=numeric,hwr-names=mips64r2 +#name: MIPS HWR disassembly (mips64r2) +#as: -32 -mips32r2 +#source: hwr-names.s + +# Check objdump's handling of -M hwr-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 7c00003b rdhwr \$0,hwr_cpunum +0+0004 <[^>]*> 7c00083b rdhwr \$0,hwr_synci_step +0+0008 <[^>]*> 7c00103b rdhwr \$0,hwr_cc +0+000c <[^>]*> 7c00183b rdhwr \$0,hwr_ccres +0+0010 <[^>]*> 7c00203b rdhwr \$0,\$4 +0+0014 <[^>]*> 7c00283b rdhwr \$0,\$5 +0+0018 <[^>]*> 7c00303b rdhwr \$0,\$6 +0+001c <[^>]*> 7c00383b rdhwr \$0,\$7 +0+0020 <[^>]*> 7c00403b rdhwr \$0,\$8 +0+0024 <[^>]*> 7c00483b rdhwr \$0,\$9 +0+0028 <[^>]*> 7c00503b rdhwr \$0,\$10 +0+002c <[^>]*> 7c00583b rdhwr \$0,\$11 +0+0030 <[^>]*> 7c00603b rdhwr \$0,\$12 +0+0034 <[^>]*> 7c00683b rdhwr \$0,\$13 +0+0038 <[^>]*> 7c00703b rdhwr \$0,\$14 +0+003c <[^>]*> 7c00783b rdhwr \$0,\$15 +0+0040 <[^>]*> 7c00803b rdhwr \$0,\$16 +0+0044 <[^>]*> 7c00883b rdhwr \$0,\$17 +0+0048 <[^>]*> 7c00903b rdhwr \$0,\$18 +0+004c <[^>]*> 7c00983b rdhwr \$0,\$19 +0+0050 <[^>]*> 7c00a03b rdhwr \$0,\$20 +0+0054 <[^>]*> 7c00a83b rdhwr \$0,\$21 +0+0058 <[^>]*> 7c00b03b rdhwr \$0,\$22 +0+005c <[^>]*> 7c00b83b rdhwr \$0,\$23 +0+0060 <[^>]*> 7c00c03b rdhwr \$0,\$24 +0+0064 <[^>]*> 7c00c83b rdhwr \$0,\$25 +0+0068 <[^>]*> 7c00d03b rdhwr \$0,\$26 +0+006c <[^>]*> 7c00d83b rdhwr \$0,\$27 +0+0070 <[^>]*> 7c00e03b rdhwr \$0,\$28 +0+0074 <[^>]*> 7c00e83b rdhwr \$0,\$29 +0+0078 <[^>]*> 7c00f03b rdhwr \$0,\$30 +0+007c <[^>]*> 7c00f83b rdhwr \$0,\$31 + \.\.\. diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index 89af998..12aeaeb 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -366,6 +366,10 @@ mips_arch_create mips32r2 32 mips32 { ror } \ mips_arch_create mips64 64 mips5 { mips32 } \ { -march=mips64 -mtune=mips64 } { -mmips:isa64 } \ { mipsisa64-*-* mipsisa64el-*-* } +mips_arch_create mips64r2 64 mips64 { mips32r2 ror } \ + { -march=mips64r2 -mtune=mips64r2 } \ + { -mmips:isa64r2 } \ + { mipsisa64r2-*-* mipsisa64r2el-*-* } mips_arch_create r3000 32 mips1 {} \ { -march=r3000 -mtune=r3000 } { -mmips:3000 } mips_arch_create r3900 32 mips1 { gpr_ilocks } \ @@ -560,10 +564,16 @@ if { [istarget mips*-*-*] } then { run_dump_test_arches "mips32" [mips_arch_list_matching mips32] run_dump_test_arches "mips32r2" [mips_arch_list_matching mips32r2] - run_list_test_arches "mips32r2-ill" "-32" [mips_arch_list_matching mips32r2] + run_list_test_arches "mips32r2-ill" "-32" \ + [mips_arch_list_matching mips32r2 gpr32] + run_list_test_arches "mips32r2-ill-fp64" "-mabi=o64" \ + [mips_arch_list_matching mips32r2 gpr64] run_dump_test_arches "mips64" [mips_arch_list_matching mips64] + run_dump_test_arches "mips64r2" [mips_arch_list_matching mips64r2] + run_list_test_arches "mips64r2-ill" "" [mips_arch_list_matching mips64r2] + run_dump_test "set-arch" if { !$addr32 } { @@ -609,6 +619,7 @@ if { [istarget mips*-*-*] } then { run_dump_test "elf_arch_mips32" run_dump_test "elf_arch_mips32r2" run_dump_test "elf_arch_mips64" + run_dump_test "elf_arch_mips64r2" # Verify that ASE markings are handled properly. if { !$no_mips16 } { run_dump_test "elf_ase_mips16" } @@ -690,14 +701,17 @@ if { [istarget mips*-*-*] } then { run_dump_test "cp0-names-mips32" run_dump_test "cp0-names-mips32r2" run_dump_test "cp0-names-mips64" + run_dump_test "cp0-names-mips64r2" run_dump_test "cp0-names-sb1" run_dump_test "cp0sel-names-numeric" run_dump_test "cp0sel-names-mips32" run_dump_test "cp0sel-names-mips32r2" run_dump_test "cp0sel-names-mips64" + run_dump_test "cp0sel-names-mips64r2" run_dump_test "cp0sel-names-sb1" run_dump_test "hwr-names-numeric" run_dump_test "hwr-names-mips32r2" + run_dump_test "hwr-names-mips64r2" } diff --git a/gas/testsuite/gas/mips/mips32r2-ill-fp64.l b/gas/testsuite/gas/mips/mips32r2-ill-fp64.l new file mode 100644 index 0000000..2b3c727 --- /dev/null +++ b/gas/testsuite/gas/mips/mips32r2-ill-fp64.l @@ -0,0 +1,13 @@ +.*: Assembler messages: +.*:12: Error: Improper position \([0-9]*\) +.*:15: Error: Improper position \(32\) +.*:18: Error: Improper extract size \(0, position 0\) +.*:21: Error: Improper extract size \(33, position 0\) +.*:24: Error: Improper extract size \(0, position 0\) +.*:27: Error: Improper extract size \(2, position 31\) +.*:30: Error: Improper position \([0-9]*\) +.*:33: Error: Improper position \(32\) +.*:36: Error: Improper insert size \(0, position 0\) +.*:39: Error: Improper insert size \(33, position 0\) +.*:42: Error: Improper insert size \(0, position 0\) +.*:45: Error: Improper insert size \(2, position 31\) diff --git a/gas/testsuite/gas/mips/mips32r2-ill-fp64.s b/gas/testsuite/gas/mips/mips32r2-ill-fp64.s new file mode 100644 index 0000000..4341607 --- /dev/null +++ b/gas/testsuite/gas/mips/mips32r2-ill-fp64.s @@ -0,0 +1,60 @@ +# source file to test illegal mips32r2 instructions + + .set noreorder + .set noat + + .text +text_label: + + # insert and extract position/size checks: + + # ext constraint: 0 <= pos < 32 + ext $4, $5, -1, 1 # error + ext $4, $5, 0, 1 + ext $4, $5, 31, 1 + ext $4, $5, 32, 1 # error + + # ext constraint: 0 < size <= 32 + ext $4, $5, 0, 0 # error + ext $4, $5, 0, 1 + ext $4, $5, 0, 32 + ext $4, $5, 0, 33 # error + + # ext constraint: 0 < (pos+size) <= 32 + ext $4, $5, 0, 0 # error + ext $4, $5, 0, 1 + ext $4, $5, 31, 1 + ext $4, $5, 31, 2 # error + + # ins constraint: 0 <= pos < 32 + ins $4, $5, -1, 1 # error + ins $4, $5, 0, 1 + ins $4, $5, 31, 1 + ins $4, $5, 32, 1 # error + + # ins constraint: 0 < size <= 32 + ins $4, $5, 0, 0 # error + ins $4, $5, 0, 1 + ins $4, $5, 0, 32 + ins $4, $5, 0, 33 # error + + # ins constraint: 0 < (pos+size) <= 32 + ins $4, $5, 0, 0 # error + ins $4, $5, 0, 1 + ins $4, $5, 31, 1 + ins $4, $5, 31, 2 # error + + # FP register checks. + # + # Even registers are supported w/ 32-bit FPU, odd + # registers supported only for 64-bit FPU. + # This file tests 64-bit FPU. + + mfhc1 $17, $f0 + mfhc1 $17, $f1 + + mthc1 $17, $f0 + mthc1 $17, $f1 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 diff --git a/gas/testsuite/gas/mips/mips64r2-ill.l b/gas/testsuite/gas/mips/mips64r2-ill.l new file mode 100644 index 0000000..c95e546 --- /dev/null +++ b/gas/testsuite/gas/mips/mips64r2-ill.l @@ -0,0 +1,57 @@ +.*: Assembler messages: +.*:12: Error: Improper position \([0-9]*\) +.*:15: Error: Improper position \(64\) +.*:18: Error: Improper extract size \(0, position 0\) +.*:21: Error: Improper extract size \(65, position 0\) +.*:31: Error: Improper extract size \(64, position 1\) +.*:33: Error: Improper extract size \(2, position 63\) +.*:34: Error: Improper extract size \(63, position 63\) +.*:35: Error: Improper extract size \(64, position 63\) +.*:40: Error: Improper position \([0-9]*\) +.*:43: Error: Improper position \(32\) +.*:46: Error: Improper extract size \(32, position 0\) +.*:49: Error: Improper extract size \(65, position 0\) +.*:59: Error: Improper extract size \(64, position 1\) +.*:61: Error: Improper extract size \(34, position 31\) +.*:62: Error: Improper extract size \(63, position 31\) +.*:63: Error: Improper extract size \(64, position 31\) +.*:68: Error: Improper position \(31\) +.*:71: Error: Improper position \(64\) +.*:74: Error: Improper extract size \(0, position 32\) +.*:77: Error: Improper extract size \(33, position 32\) +.*:87: Error: Improper extract size \(32, position 33\) +.*:89: Error: Improper extract size \(2, position 63\) +.*:90: Error: Improper extract size \(31, position 63\) +.*:91: Error: Improper extract size \(32, position 63\) +.*:96: Error: Improper position \([0-9]*\) +.*:99: Error: Improper position \(64\) +.*:102: Error: Improper insert size \(0, position 0\) +.*:105: Error: Improper insert size \(65, position 0\) +.*:115: Error: Improper insert size \(64, position 1\) +.*:117: Error: Improper insert size \(2, position 63\) +.*:118: Error: Improper insert size \(63, position 63\) +.*:119: Error: Improper insert size \(64, position 63\) +.*:124: Error: Improper position \([0-9]*\) +.*:127: Error: Improper position \(32\) +.*:130: Error: Improper insert size \(1, position 31\) +.*:133: Error: Improper insert size \(65, position 0\) +.*:136: Error: Improper insert size \(2, position 0\) +.*:137: Error: Improper insert size \(3, position 0\) +.*:140: Error: Improper insert size \(2, position 1\) +.*:141: Error: Improper insert size \(3, position 1\) +.*:143: Error: Improper insert size \(64, position 1\) +.*:144: Error: Improper insert size \(2, position 30\) +.*:146: Error: Improper insert size \(63, position 30\) +.*:147: Error: Improper insert size \(64, position 30\) +.*:150: Error: Improper insert size \(63, position 31\) +.*:151: Error: Improper insert size \(64, position 31\) +.*:156: Error: Improper position \(31\) +.*:159: Error: Improper position \(64\) +.*:162: Error: Improper insert size \(0, position 32\) +.*:165: Error: Improper insert size \(33, position 32\) +.*:175: Error: Improper insert size \(32, position 33\) +.*:178: Error: Improper insert size \(31, position 62\) +.*:179: Error: Improper insert size \(32, position 62\) +.*:181: Error: Improper insert size \(2, position 63\) +.*:182: Error: Improper insert size \(31, position 63\) +.*:183: Error: Improper insert size \(32, position 63\) diff --git a/gas/testsuite/gas/mips/mips64r2-ill.s b/gas/testsuite/gas/mips/mips64r2-ill.s new file mode 100644 index 0000000..b991b56 --- /dev/null +++ b/gas/testsuite/gas/mips/mips64r2-ill.s @@ -0,0 +1,186 @@ +# source file to test illegal mips64r2 instructions + + .set noreorder + .set noat + + .text +text_label: + + # dext macro position/size checks + + # constraint: 0 <= pos < 64 + dext $4, $5, -1, 1 # error (position) + dext $4, $5, 0, 1 + dext $4, $5, 63, 1 + dext $4, $5, 64, 1 # error (position) + + # constraint: 0 < size <= 64 + dext $4, $5, 0, 0 # error (size) + dext $4, $5, 0, 1 + dext $4, $5, 0, 64 + dext $4, $5, 0, 65 # error (size) + + # constraint: 0 < (pos+size) <= 64 + dext $4, $5, 0, 1 + dext $4, $5, 0, 2 + dext $4, $5, 0, 63 + dext $4, $5, 0, 64 + dext $4, $5, 1, 1 + dext $4, $5, 1, 2 + dext $4, $5, 1, 63 + dext $4, $5, 1, 64 # error (size) + dext $4, $5, 63, 1 + dext $4, $5, 63, 2 # error (size) + dext $4, $5, 63, 63 # error (size) + dext $4, $5, 63, 64 # error (size) + + # dextm instruction position/size checks + + # constraint: 0 <= pos < 32 + dextm $4, $5, -1, 33 # error (position) + dextm $4, $5, 0, 33 + dextm $4, $5, 31, 33 + dextm $4, $5, 32, 33 # error (position) + + # constraint: 32 < size <= 64 + dextm $4, $5, 0, 32 # error (size) + dextm $4, $5, 0, 33 + dextm $4, $5, 0, 64 + dextm $4, $5, 0, 65 # error (size) + + # constraint: 32 < (pos+size) <= 64 + dextm $4, $5, 0, 33 + dextm $4, $5, 0, 34 + dextm $4, $5, 0, 63 + dextm $4, $5, 0, 64 + dextm $4, $5, 1, 33 + dextm $4, $5, 1, 34 + dextm $4, $5, 1, 63 + dextm $4, $5, 1, 64 # error (size) + dextm $4, $5, 31, 33 + dextm $4, $5, 31, 34 # error (size) + dextm $4, $5, 31, 63 # error (size) + dextm $4, $5, 31, 64 # error (size) + + # dextu instruction position/size checks + + # constraint: 32 <= pos < 64 + dextu $4, $5, 31, 1 # error (position) + dextu $4, $5, 32, 1 + dextu $4, $5, 63, 1 + dextu $4, $5, 64, 1 # error (position) + + # constraint: 0 < size <= 32 + dextu $4, $5, 32, 0 # error (size) + dextu $4, $5, 32, 1 + dextu $4, $5, 32, 32 + dextu $4, $5, 32, 33 # error (size) + + # constraint: 32 < (pos+size) <= 64 + dextu $4, $5, 32, 1 + dextu $4, $5, 32, 2 + dextu $4, $5, 32, 31 + dextu $4, $5, 32, 32 + dextu $4, $5, 33, 1 + dextu $4, $5, 33, 2 + dextu $4, $5, 33, 31 + dextu $4, $5, 33, 32 # error (size) + dextu $4, $5, 63, 1 + dextu $4, $5, 63, 2 # error (size) + dextu $4, $5, 63, 31 # error (size) + dextu $4, $5, 63, 32 # error (size) + + # dins macro position/size checks + + # constraint: 0 <= pos < 64 + dins $4, $5, -1, 1 # error (position) + dins $4, $5, 0, 1 + dins $4, $5, 63, 1 + dins $4, $5, 64, 1 # error (position) + + # constraint: 0 < size <= 64 + dins $4, $5, 0, 0 # error (size) + dins $4, $5, 0, 1 + dins $4, $5, 0, 64 + dins $4, $5, 0, 65 # error (size) + + # constraint: 0 < (pos+size) <= 64 + dins $4, $5, 0, 1 + dins $4, $5, 0, 2 + dins $4, $5, 0, 63 + dins $4, $5, 0, 64 + dins $4, $5, 1, 1 + dins $4, $5, 1, 2 + dins $4, $5, 1, 63 + dins $4, $5, 1, 64 # error (size) + dins $4, $5, 63, 1 + dins $4, $5, 63, 2 # error (size) + dins $4, $5, 63, 63 # error (size) + dins $4, $5, 63, 64 # error (size) + + # dinsm instruction position/size checks + + # constraint: 0 <= pos < 32 + dinsm $4, $5, -1, 33 # error (position) + dinsm $4, $5, 0, 33 + dinsm $4, $5, 31, 33 + dinsm $4, $5, 32, 33 # error (position) + + # constraint: 2 <= size <= 64 + dinsm $4, $5, 31, 1 # error (size) + dinsm $4, $5, 31, 2 + dinsm $4, $5, 0, 64 + dinsm $4, $5, 0, 65 # error (size) + + # constraint: 32 < (pos+size) <= 64 + dinsm $4, $5, 0, 2 # error (size) + dinsm $4, $5, 0, 3 # error (size) + dinsm $4, $5, 0, 63 + dinsm $4, $5, 0, 64 + dinsm $4, $5, 1, 2 # error (size) + dinsm $4, $5, 1, 3 # error (size) + dinsm $4, $5, 1, 63 + dinsm $4, $5, 1, 64 # error (size) + dinsm $4, $5, 30, 2 # error (size) + dinsm $4, $5, 30, 3 + dinsm $4, $5, 30, 63 # error (size) + dinsm $4, $5, 30, 64 # error (size) + dinsm $4, $5, 31, 2 + dinsm $4, $5, 31, 3 + dinsm $4, $5, 31, 63 # error (size) + dinsm $4, $5, 31, 64 # error (size) + + # dinsu instruction position/size checks + + # constraint: 32 <= pos < 64 + dinsu $4, $5, 31, 1 # error (position) + dinsu $4, $5, 32, 1 + dinsu $4, $5, 63, 1 + dinsu $4, $5, 64, 1 # error (position) + + # constraint: 1 <= size <= 32 + dinsu $4, $5, 32, 0 # error (size) + dinsu $4, $5, 32, 1 + dinsu $4, $5, 32, 32 + dinsu $4, $5, 32, 33 # error (size) + + # constraint: 32 < (pos+size) <= 64 + dinsu $4, $5, 32, 1 + dinsu $4, $5, 32, 2 + dinsu $4, $5, 32, 31 + dinsu $4, $5, 32, 32 + dinsu $4, $5, 33, 1 + dinsu $4, $5, 33, 2 + dinsu $4, $5, 33, 31 + dinsu $4, $5, 33, 32 # error (size) + dinsu $4, $5, 62, 1 + dinsu $4, $5, 62, 2 + dinsu $4, $5, 62, 31 # error (size) + dinsu $4, $5, 62, 32 # error (size) + dinsu $4, $5, 63, 1 + dinsu $4, $5, 63, 2 # error (size) + dinsu $4, $5, 63, 31 # error (size) + dinsu $4, $5, 63, 32 # error (size) + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 diff --git a/gas/testsuite/gas/mips/mips64r2.d b/gas/testsuite/gas/mips/mips64r2.d new file mode 100644 index 0000000..8d33611 --- /dev/null +++ b/gas/testsuite/gas/mips/mips64r2.d @@ -0,0 +1,46 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric +#name: MIPS MIPS64r2 instructions + +# Check MIPS64r2 instruction assembly + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 7c620003 dext \$2,\$3,0x0,0x1 +0+0004 <[^>]*> 7c62f803 dext \$2,\$3,0x0,0x20 +0+0008 <[^>]*> 7c620001 dextm \$2,\$3,0x0,0x21 +0+000c <[^>]*> 7c62f801 dextm \$2,\$3,0x0,0x40 +0+0010 <[^>]*> 7c6207c3 dext \$2,\$3,0x1f,0x1 +0+0014 <[^>]*> 7c62ffc3 dext \$2,\$3,0x1f,0x20 +0+0018 <[^>]*> 7c6207c1 dextm \$2,\$3,0x1f,0x21 +0+001c <[^>]*> 7c620002 dextu \$2,\$3,0x20,0x1 +0+0020 <[^>]*> 7c62f802 dextu \$2,\$3,0x20,0x20 +0+0024 <[^>]*> 7c6207c2 dextu \$2,\$3,0x3f,0x1 +0+0028 <[^>]*> 7c625a81 dextm \$2,\$3,0xa,0x2c +0+002c <[^>]*> 7c625a82 dextu \$2,\$3,0x2a,0xc +0+0030 <[^>]*> 7c620007 dins \$2,\$3,0x0,0x1 +0+0034 <[^>]*> 7c62f807 dins \$2,\$3,0x0,0x20 +0+0038 <[^>]*> 7c620005 dinsm \$2,\$3,0x0,0x21 +0+003c <[^>]*> 7c62f805 dinsm \$2,\$3,0x0,0x40 +0+0040 <[^>]*> 7c62ffc7 dins \$2,\$3,0x1f,0x1 +0+0044 <[^>]*> 7c6207c5 dinsm \$2,\$3,0x1f,0x2 +0+0048 <[^>]*> 7c62ffc5 dinsm \$2,\$3,0x1f,0x21 +0+004c <[^>]*> 7c620006 dinsu \$2,\$3,0x20,0x1 +0+0050 <[^>]*> 7c62f806 dinsu \$2,\$3,0x20,0x20 +0+0054 <[^>]*> 7c62ffc6 dinsu \$2,\$3,0x3f,0x1 +0+0058 <[^>]*> 7c62aa85 dinsm \$2,\$3,0xa,0x2c +0+005c <[^>]*> 7c62aa86 dinsu \$2,\$3,0x2a,0xc +0+0060 <[^>]*> 002acf3e dror32 \$25,\$10,0x1c +0+0064 <[^>]*> 002ac93a dror \$25,\$10,0x4 +0+0068 <[^>]*> 002acf3a dror \$25,\$10,0x1c +0+006c <[^>]*> 002ac93e dror32 \$25,\$10,0x4 +0+0070 <[^>]*> 0004c82f dnegu \$25,\$4 +0+0074 <[^>]*> 032ac856 drorv \$25,\$10,\$25 +0+0078 <[^>]*> 008ac856 drorv \$25,\$10,\$4 +0+007c <[^>]*> 002ac93e dror32 \$25,\$10,0x4 +0+0080 <[^>]*> 008ac856 drorv \$25,\$10,\$4 +0+0084 <[^>]*> 7c0738a4 dsbh \$7,\$7 +0+0088 <[^>]*> 7c0a40a4 dsbh \$8,\$10 +0+008c <[^>]*> 7c073964 dshd \$7,\$7 +0+0090 <[^>]*> 7c0a4164 dshd \$8,\$10 + \.\.\. diff --git a/gas/testsuite/gas/mips/mips64r2.s b/gas/testsuite/gas/mips/mips64r2.s new file mode 100644 index 0000000..2034323 --- /dev/null +++ b/gas/testsuite/gas/mips/mips64r2.s @@ -0,0 +1,65 @@ +# source file to test assembly of mips64r2 instructions +# (assumes that mips32r2 instructions will be tested separately for mips64r2.) + + .set noreorder + .set noat + + .text +text_label: + + # unprivileged CPU instructions + + # Test macro's ability to turn "dext" into "dext", "dextm" and + # "dextu" as appropriate. Also, add some explicit tests of the + # actual instructions. + dext $2, $3, 0, 1 # dext + dext $2, $3, 0, 32 # dext + dext $2, $3, 0, 33 # dextm + dext $2, $3, 0, 64 # dextm + dext $2, $3, 31, 1 # dext + dext $2, $3, 31, 32 # dext + dext $2, $3, 31, 33 # dextm + dext $2, $3, 32, 1 # dextu + dext $2, $3, 32, 32 # dextu + dext $2, $3, 63, 1 # dextu + dextm $2, $3, 10, 44 + dextu $2, $3, 42, 12 + + # Test macro's ability to turn "dins" into "dins", "dinsm" and + # "dinsu" as appropriate. Also, add some explicit tests of the + # non-macro instructions. + dins $2, $3, 0, 1 # dins + dins $2, $3, 0, 32 # dins + dins $2, $3, 0, 33 # dinsm + dins $2, $3, 0, 64 # dinsm + dins $2, $3, 31, 1 # dins + dins $2, $3, 31, 2 # dinsm + dins $2, $3, 31, 33 # dinsm + dins $2, $3, 32, 1 # dinsu + dins $2, $3, 32, 32 # dinsu + dins $2, $3, 63, 1 # dinsu + dinsm $2, $3, 10, 44 + dinsu $2, $3, 42, 12 + + # This file checks that in fact HW rotate will + # be used for this arch, and checks assembly + # of the official MIPS mnemonics. (Note that disassembly + # uses the traditional "dror", "dror32" and "drorv" + # mnemonics.) Additional rotate tests are done by rol64-hw.d. + drotl $25, $10, 4 # dror32 + drotr $25, $10, 4 # dror + drotl $25, $10, 36 # dror + drotr $25, $10, 36 # dror32 + drotl $25, $10, $4 # neg / drorv + drotr $25, $10, $4 # drorv + drotr32 $25, $10, 4 # dror32 + drotrv $25, $10, $4 # drorv + + dsbh $7 + dsbh $8, $10 + + dshd $7 + dshd $8, $10 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index 160a75e..47216be 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,7 @@ +2003-09-30 Chris Demetriou <cgd@broadcom.com> + + * mips.h (E_MIPS_ARCH_64R2): New define. + 2003-09-23 DJ Delorie <dj@redhat.com> * sh.h (R_SH_SWITCH8, R_SH_GNU_VTINHERIT, R_SH_GNU_VTENTRY, diff --git a/include/elf/mips.h b/include/elf/mips.h index 4b36ff7..ce43158 100644 --- a/include/elf/mips.h +++ b/include/elf/mips.h @@ -151,6 +151,9 @@ END_RELOC_NUMBERS (R_MIPS_maxext) /* -mips32r2 code. */ #define E_MIPS_ARCH_32R2 0x70000000 +/* -mips64r2 code. */ +#define E_MIPS_ARCH_64R2 0x80000000 + /* The ABI of the file. Also see EF_MIPS_ABI2 above. */ #define EF_MIPS_ABI 0x0000F000 diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index aaea214..b248854 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,10 @@ +2003-09-30 Chris Demetriou <cgd@broadcom.com> + + * mips.h: Document +E, +F, +G, +H, and +I operand types. + Update documentation of I, +B and +C operand types. + (INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines. + (M_DEXT, M_DINS): New enum values. + 2003-09-04 Nick Clifton <nickc@redhat.com> * v850.h (PROCESSOR_V850E1): Define. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 65434a7..9dab620 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -236,11 +236,24 @@ struct mips_opcode "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT). Enforces: 0 <= pos < 32. "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB). - Requires that "+A" occur first to set position. + Requires that "+A" or "+E" occur first to set position. Enforces: 0 < (pos+size) <= 32. "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD). - Requires that "+A" occur first to set position. + Requires that "+A" or "+E" occur first to set position. Enforces: 0 < (pos+size) <= 32. + (Also used by "dext" w/ different limits, but limits for + that are checked by the M_DEXT macro.) + "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT). + Enforces: 32 <= pos < 64. + "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. Floating point instructions: "D" 5 bit destination register (OP_*_FD) @@ -265,7 +278,8 @@ struct mips_opcode Macro instructions: "A" General 32 bit expression - "I" 32 bit immediate + "I" 32 bit immediate (value placed in imm_expr). + "+I" 32 bit immediate (value placed in imm2_expr). "F" 64 bit floating point constant in .rdata "L" 64 bit floating point constant in .lit8 "f" 32 bit floating point constant @@ -292,7 +306,7 @@ struct mips_opcode Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: - "ABCD" + "ABCDEFGHI" */ /* These are the bits which may be set in the pinfo field of an @@ -385,6 +399,7 @@ struct mips_opcode #define INSN_ISA32 0x00000020 #define INSN_ISA64 0x00000040 #define INSN_ISA32R2 0x00000080 +#define INSN_ISA64R2 0x00000100 /* Masks used for MIPS-defined ASEs. */ #define INSN_ASE_MASK 0x0000f000 @@ -432,6 +447,8 @@ struct mips_opcode #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) +#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) + /* CPU defines, use instead of hardcoding processor number. Keep this in sync with bfd/archures.c in order for machine selection to work. */ @@ -460,6 +477,7 @@ struct mips_opcode #define CPU_MIPS32R2 33 #define CPU_MIPS5 5 #define CPU_MIPS64 64 +#define CPU_MIPS64R2 65 #define CPU_SB1 12310201 /* octal 'SB', 01. */ /* Test for membership in an ISA including chip specific ISAs. INSN @@ -542,6 +560,8 @@ enum M_DDIV_3I, M_DDIVU_3, M_DDIVU_3I, + M_DEXT, + M_DINS, M_DIV_3, M_DIV_3I, M_DIVU_3, diff --git a/ld/ChangeLog b/ld/ChangeLog index 496d3de..961ce66 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,7 @@ +2003-09-30 Chris Demetriou <cgd@broadcom.com> + + * ldmain.c (get_emulation): Ignore "-mips64r2". + 2003-09-03 Robert Millan <robertmh@gnu.org> * configure.host: Match GNU/KFreeBSD with new kfreebsd*-gnu diff --git a/ld/ldmain.c b/ld/ldmain.c index fb07a81..b18b580 100644 --- a/ld/ldmain.c +++ b/ld/ldmain.c @@ -602,7 +602,8 @@ get_emulation (int argc, char **argv) || strcmp (argv[i], "-mips5") == 0 || strcmp (argv[i], "-mips32") == 0 || strcmp (argv[i], "-mips32r2") == 0 - || strcmp (argv[i], "-mips64") == 0) + || strcmp (argv[i], "-mips64") == 0 + || strcmp (argv[i], "-mips64r2") == 0) { /* FIXME: The arguments -mips1, -mips2, -mips3, etc. are passed to the linker by some MIPS compilers. They diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index 900402c..643db87 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2003-09-30 Chris Demetriou <cgd@broadcom.com> + + * ld-mips-elf/mips-elf-flags.exp: Add tests for combinations + with MIPS64r2. + 2003-09-29 H.J. Lu <hongjiu.lu@intel.com> * lib/ld-lib.exp (proc is_elf64): New. diff --git a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp index b289a6d..73dd24e 100644 --- a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp +++ b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp @@ -133,6 +133,7 @@ isa_conflict { "-march=r3900 -32" "-march=r6000 -32" } 3900 6000 isa_conflict { "-march=r4010 -32" "-march=r4650 -32" } 4010 4650 isa_conflict { "-mips3 -mgp32 -32" "-mips32 -32" } 4000 isa32 isa_conflict { "-march=sb1 -mgp32 -32" "-mips32r2 -32" } sb1 isa32r2 +isa_conflict { "-march=sb1 -32" "-mips64r2 -32" } sb1 isa64r2 regsize_conflict { "-mips4 -mgp64 -mabi=o64" "-mips2 -32" } regsize_conflict { "-mips4 -mabi=o64" "-mips4 -mabi=32" } @@ -140,6 +141,7 @@ regsize_conflict { "-mips4 -mabi=eabi -mgp32" "-mips4 -mabi=eabi -mgp64" } regsize_conflict { "-march=vr5000 -mgp64 -mabi=o64" "-march=vr5000 -mgp32 -32" } regsize_conflict { "-mips32 -32" "-mips64 -mabi=o64" } regsize_conflict { "-mips32r2 -32" "-mips64 -mabi=o64" } +regsize_conflict { "-mips32r2 -32" "-mips64r2 -mabi=o64" } good_combination { "-mips4 -mgp32 -32" "-mips2 -32" } { mips4 o32 } good_combination { "-mips4 -mabi=32" "-mips2 -32" } { mips4 o32 } @@ -152,6 +154,7 @@ good_combination { "-march=vr4100 -32" "-march=vr4120 -32" } { 4120 } good_combination { "-march=vr5400 -32" "-march=vr5500 -32" "-mips4 -32" } { 5500 } good_combination { "-mips3 -32" "-mips4 -32" "-march=sb1 -32" "-mips5 -32" } { sb1 } good_combination { "-mips1 -32" "-march=3900 -32" } { 3900 } +good_combination { "-mips3 -32" "-mips64r2 -32" "-mips64 -32" } { mips64r2 } good_combination { "-march=vr4120 -mabi=32" "-mips3 -mabi=32" } { 4120 o32 } good_combination { "-march=sb1 -mgp32 -32" "-march=4000 -mgp32 -32" } { sb1 o32 } diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 1f0b2ab..e102fc6 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2003-09-30 Chris Demetriou <cgd@broadcom.com> + + * mips-dis.c (mips_arch_choices): Add entry for "mips64r2" + (print_insn_args): Add handing for +E, +F, +G, and +H. + * mips-opc.c (I65): New define for MIPS64r2. + (mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins", + "dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh", + and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to + be supported on MIPS64r2. + 2003-09-24 Dave Brolley <brolley@redhat.com> * frv-desc.c, frv-opc.c, frv-opc.h: Regenerated. diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index af6c445..43fcb3c 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -384,6 +384,12 @@ const struct mips_arch_choice mips_arch_choices[] = { mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), mips_hwr_names_numeric }, + { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, + ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_hwr_names_mips3264r2 }, + { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, mips_cp0_names_sb1, @@ -714,6 +720,7 @@ print_insn_args (d, l, pc, info) break; case 'C': + case 'H': msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); break; @@ -740,6 +747,21 @@ print_insn_args (d, l, pc, info) break; } + case 'E': + lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; + (*info->fprintf_func) (info->stream, "0x%x", lsb); + break; + + case 'F': + msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; + (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); + break; + + case 'G': + msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32; + (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); + break; + default: /* xgettext:c-format */ (*info->fprintf_func) (info->stream, diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 228357a..340a084 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -87,6 +87,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define I32 INSN_ISA32 #define I64 INSN_ISA64 #define I33 INSN_ISA32R2 +#define I65 INSN_ISA64R2 /* MIPS64 MIPS-3D ASE support. */ #define I16 INSN_MIPS16 @@ -481,6 +482,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 }, {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 }, {"deret", "", 0x4200001f, 0xffffffff, 0, I32|G2 }, +{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, I65 }, +{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, I65 }, +{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, I65 }, +{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, I65 }, /* For ddiv, see the comments about div. */ {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 }, @@ -491,6 +496,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 }, {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, I33 }, {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, I33 }, +{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, I65 }, +{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, I65 }, +{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, I65 }, +{"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, I65 }, /* The MIPS assembler treats the div opcode with two operands as though the first operand appeared twice (the first operand is both a source and a destination). To get the div machine instruction, @@ -559,9 +568,17 @@ const struct mips_opcode mips_builtin_opcodes[] = {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 }, {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 }, {"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 }, -{"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, N5 }, -{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, N5 }, -{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, N5 }, +{"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, N5|I65 }, +{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, N5|I65 }, +{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, N5|I65 }, +{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I65 }, +{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I65 }, +{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I65 }, +{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I65 }, +{"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, I65 }, +{"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, I65 }, +{"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, I65 }, +{"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, I65 }, {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */ |