[sim] Run spellcheck.sh in sim (part 1)

Run gdb/contrib/spellcheck.sh on directory sim.

Fix auto-corrected typos:
...
accessable -> accessible
accidently -> accidentally
accomodate -> accommodate
adress -> address
afair -> affair
agains -> against
agressively -> aggressively
annuled -> annulled
arbitary -> arbitrary
arround -> around
auxillary -> auxiliary
availablity -> availability
clasic -> classic
comming -> coming
controled -> controlled
controling -> controlling
destory -> destroy
existance -> existence
explictly -> explicitly
faciliate -> facilitate
fouth -> fourth
fullfilled -> fulfilled
guarentee -> guarantee
hinderance -> hindrance
independant -> independent
inital -> initial
loosing -> losing
occurance -> occurrence
occured -> occurred
occuring -> occurring
omited -> omitted
oportunity -> opportunity
parallely -> parallelly
permissable -> permissible
postive -> positive
powerfull -> powerful
preceed -> precede
preceeding -> preceding
preceeds -> precedes
primative -> primitive
probaly -> probably
programable -> programmable
propogate -> propagate
propper -> proper
recieve -> receive
reconized -> recognized
refered -> referred
refering -> referring
relevent -> relevant
responisble -> responsible
retreive -> retrieve
safty -> safety
specifiying -> specifying
spontanous -> spontaneous
sqaure -> square
successfull -> successful
supress -> suppress
sytem -> system
thru -> through
transfered -> transferred
trigered -> triggered
unfortunatly -> unfortunately
upto -> up to
usefull -> useful
wierd -> weird
writen -> written
doesnt -> doesn't
isnt -> isn't
...

Manually undid the "andd -> and" transformation in sim/testsuite/cr16/andd.cgs
and sim/cr16/simops.c.

Tested by rebuilding on x86_64-linux.

Approved-By: Tom Tromey <tom@tromey.com>

8 files changed, 11 insertions, 11 deletions

diff --git a/sim/testsuite/bfin/se_illegalcombination.S b/sim/testsuite/bfin/se_illegalcombination.S
index 85633d1..c3a0cc7 100644
--- a/sim/testsuite/bfin/se_illegalcombination.S
+++ b/sim/testsuite/bfin/se_illegalcombination.S
@@ -2,7 +2,7 @@
 // Description: Multi-issue Illegal Combinations
 # mach: bfin
 # sim: --environment operating
-# xfail: "missing a few checks; hardware doesnt seem to match PRM?" *-*
+# xfail: "missing a few checks; hardware doesn't seem to match PRM?" *-*
 
 #include "test.h"
 .include "testutils.inc"
diff --git a/sim/testsuite/bfin/se_undefinedinstruction1.S b/sim/testsuite/bfin/se_undefinedinstruction1.S
index 5337a74..fa1ab72 100644
--- a/sim/testsuite/bfin/se_undefinedinstruction1.S
+++ b/sim/testsuite/bfin/se_undefinedinstruction1.S
@@ -200,7 +200,7 @@ BEGIN:
     .dw 0x21 ;
     .dw 0x22 ;
     .dw 0x26 ;
-    .dw 0x27 ;	// XXX: hardware doesnt trigger illegal exception ?
+    .dw 0x27 ;	// XXX: hardware doesn't trigger illegal exception ?
     .dw 0x28 ;
     .dw 0x29 ;
     .dw 0x2A ;
diff --git a/sim/testsuite/bfin/se_undefinedinstruction2.S b/sim/testsuite/bfin/se_undefinedinstruction2.S
index d21e375..9d68ccb 100644
--- a/sim/testsuite/bfin/se_undefinedinstruction2.S
+++ b/sim/testsuite/bfin/se_undefinedinstruction2.S
@@ -175,12 +175,12 @@ BEGIN:
     .dw 0x10E ;
     .dw 0x124 ;
 .ifndef BFIN_HW
-	// XXX: hardware doesnt trigger illegal exception ?
+	// XXX: hardware doesn't trigger illegal exception ?
     .dw 0x125 ;
 .endif
     .dw 0x164 ;
 .ifndef BFIN_HW
-	// XXX: hardware doesnt trigger illegal exception ?
+	// XXX: hardware doesn't trigger illegal exception ?
     .dw 0x165 ;
 .endif
     .dw 0x128 ;
diff --git a/sim/testsuite/d10v/t-macros.i b/sim/testsuite/d10v/t-macros.i
index d6e155c..d5e85a4 100644
--- a/sim/testsuite/d10v/t-macros.i
+++ b/sim/testsuite/d10v/t-macros.i
@@ -174,7 +174,7 @@ _start:
 	.data
 1:	ldi r1, 2f@word
 	jmp r1
-;;; Successfull trap jumps back to here
+;;; Successful trap jumps back to here
 	.text
 ;;; Verify the PSW
 2:	mvfc	r2, cr0
diff --git a/sim/testsuite/frv/testutils.inc b/sim/testsuite/frv/testutils.inc
index 8261b4fa..3ff78f0 100644
--- a/sim/testsuite/frv/testutils.inc
+++ b/sim/testsuite/frv/testutils.inc
@@ -347,7 +347,7 @@ test_gr\@:
 	test_fr_iimmed	\val,fr31
 	.endm
 
-; Test CPR agains an immediate value
+; Test CPR against an immediate value
 	.macro test_cpr_limmed valh vall reg
 	addi		sp,-4,gr31
 	stc		\reg,@(gr31,gr0)
diff --git a/sim/testsuite/h8300/ldc.s b/sim/testsuite/h8300/ldc.s
index 3712a6c..74cba02 100644
--- a/sim/testsuite/h8300/ldc.s
+++ b/sim/testsuite/h8300/ldc.s
@@ -341,7 +341,7 @@ ldc_reg_sbr:
 
 	mov	#0xaaaaaaaa, er0
 	ldc	er0, sbr	; set sbr to 0xaaaaaaaa
- 	stc	sbr, er1	; retreive and check sbr value
+ 	stc	sbr, er1	; retrieve and check sbr value
 
 	test_h_gr32 0xaaaaaaaa er1
 	test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
@@ -358,7 +358,7 @@ ldc_reg_vbr:
 
 	mov	#0xaaaaaaaa, er0
 	ldc	er0, vbr	; set sbr to 0xaaaaaaaa
-	stc	vbr, er1	; retreive and check sbr value
+	stc	vbr, er1	; retrieve and check sbr value
 
 	test_h_gr32 0xaaaaaaaa er1
 	test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
diff --git a/sim/testsuite/h8300/stc.s b/sim/testsuite/h8300/stc.s
index 232bd5a..62b8ac0 100644
--- a/sim/testsuite/h8300/stc.s
+++ b/sim/testsuite/h8300/stc.s
@@ -304,7 +304,7 @@ stc_sbr_reg:
 
 	mov	#0xaaaaaaaa, er0
 	ldc	er0, sbr	; set sbr to 0xaaaaaaaa
- 	stc	sbr, er1	; retreive and check sbr value
+ 	stc	sbr, er1	; retrieve and check sbr value
 
 	test_h_gr32 0xaaaaaaaa er1
 	test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
@@ -321,7 +321,7 @@ stc_vbr_reg:
 
 	mov	#0xaaaaaaaa, er0
 	ldc	er0, vbr	; set sbr to 0xaaaaaaaa
-	stc	vbr, er1	; retreive and check sbr value
+	stc	vbr, er1	; retrieve and check sbr value
 
 	test_h_gr32 0xaaaaaaaa er1
 	test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
diff --git a/sim/testsuite/h8300/testutils.inc b/sim/testsuite/h8300/testutils.inc
index 9c2c27a..63d27d4 100644
--- a/sim/testsuite/h8300/testutils.inc
+++ b/sim/testsuite/h8300/testutils.inc
@@ -326,7 +326,7 @@ tccr\@:	.byte	0
 	mov.b	@tccr\@, r0l
 	.endm
 
-; Test that all (accessable) condition codes are clear
+; Test that all (accessible) condition codes are clear
 	.macro test_cc_clear
 	test_carry_clear
 	test_ovf_clear