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| author | Nelson Chu <nelson@rivosinc.com> | 2025-07-10 21:50:19 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2025-07-10 21:50:19 +0800 |
| commit | a6a177d0a200db9feb84aaa23c4fac02df172b61 (patch) | |
| tree | bb4ca3de1622c0035cce2e85fcf1ce0f5e7fd94a /sim/riscv | |
| parent | 7694eb6393db603911487a0f4f19d067b9186e0e (diff) | |
| download | binutils-master.zip binutils-master.tar.gz binutils-master.tar.bz2 | |
Diffstat (limited to 'sim/riscv')
| -rw-r--r-- | sim/riscv/sim-main.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 4c949c4..172c593 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -1302,7 +1302,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) case INSN_CLASS_ZAAMO: case INSN_CLASS_ZALRSC: return execute_a (cpu, iw, op); - case INSN_CLASS_C: + case INSN_CLASS_ZCA: /* Check whether model with C extension is selected. */ if (riscv_cpu->csr.misa & 4) return execute_c (cpu, iw, op); |