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author | Tom de Vries <tdevries@suse.de> | 2024-11-23 13:07:38 +0100 |
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committer | Tom de Vries <tdevries@suse.de> | 2024-11-23 13:07:38 +0100 |
commit | d2d240ff89b4d3359ea70cdb47d3e79294ca891a (patch) | |
tree | d277cf5c4263881d513deb2d7389c2a0c1f4610b /sim/igen/gen.c | |
parent | 8dfa29fcbd60bead4d67569bd14c818540959130 (diff) | |
download | binutils-d2d240ff89b4d3359ea70cdb47d3e79294ca891a.zip binutils-d2d240ff89b4d3359ea70cdb47d3e79294ca891a.tar.gz binutils-d2d240ff89b4d3359ea70cdb47d3e79294ca891a.tar.bz2 |
[sim] Run spellcheck.sh in sim (part 1)
Run gdb/contrib/spellcheck.sh on directory sim.
Fix auto-corrected typos:
...
accessable -> accessible
accidently -> accidentally
accomodate -> accommodate
adress -> address
afair -> affair
agains -> against
agressively -> aggressively
annuled -> annulled
arbitary -> arbitrary
arround -> around
auxillary -> auxiliary
availablity -> availability
clasic -> classic
comming -> coming
controled -> controlled
controling -> controlling
destory -> destroy
existance -> existence
explictly -> explicitly
faciliate -> facilitate
fouth -> fourth
fullfilled -> fulfilled
guarentee -> guarantee
hinderance -> hindrance
independant -> independent
inital -> initial
loosing -> losing
occurance -> occurrence
occured -> occurred
occuring -> occurring
omited -> omitted
oportunity -> opportunity
parallely -> parallelly
permissable -> permissible
postive -> positive
powerfull -> powerful
preceed -> precede
preceeding -> preceding
preceeds -> precedes
primative -> primitive
probaly -> probably
programable -> programmable
propogate -> propagate
propper -> proper
recieve -> receive
reconized -> recognized
refered -> referred
refering -> referring
relevent -> relevant
responisble -> responsible
retreive -> retrieve
safty -> safety
specifiying -> specifying
spontanous -> spontaneous
sqaure -> square
successfull -> successful
supress -> suppress
sytem -> system
thru -> through
transfered -> transferred
trigered -> triggered
unfortunatly -> unfortunately
upto -> up to
usefull -> useful
wierd -> weird
writen -> written
doesnt -> doesn't
isnt -> isn't
...
Manually undid the "andd -> and" transformation in sim/testsuite/cr16/andd.cgs
and sim/cr16/simops.c.
Tested by rebuilding on x86_64-linux.
Approved-By: Tom Tromey <tom@tromey.com>
Diffstat (limited to 'sim/igen/gen.c')
-rw-r--r-- | sim/igen/gen.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sim/igen/gen.c b/sim/igen/gen.c index 1499147..bf57162 100644 --- a/sim/igen/gen.c +++ b/sim/igen/gen.c @@ -644,7 +644,7 @@ insns_bit_useless (const insn_list *insns, const decode_table *rule, int bit_nr) /* Given only one constant value has been found, check through all the instructions to see if at least one conditional makes it - usefull */ + useful */ if (value >= 0 && is_useless) { for (entry = insns; entry != NULL; entry = entry->next) @@ -981,7 +981,7 @@ gen_entry_expand_opcode (gen_entry *table, condition->field->last); /* this is a requirement of a conditonal field - refering to another field */ + referring to another field */ ASSERT ((condition->field->first - condition->field->last) == (first_pos - last_pos)); |