x86: fold RegEip/RegRip and RegEiz/RegRiz

This allows to simplify the code in a number of places.

4 files changed, 27 insertions, 18 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 389a1b6..2fcec95 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,14 @@
+2018-08-06  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
+	(RegIP, RegIZ): Define.
+	* i386-reg.tbl: Adjust comments.
+	(rip): Use Qword instead of BaseIndex. Use RegIP.
+	(eip): Use Dword instead of BaseIndex. Use RegIP.
+	(riz): Add Qword. Use RegIZ.
+	(eiz): Add Dword. Use RegIZ.
+	* i386-tbl.h: Re-generate.
+
 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 
 	* i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 202804e..ecfdc7f 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -895,11 +895,9 @@ typedef struct
 #define RegRex64    0x2  /* Extended 8 bit register.  */
 #define RegVRex	    0x4  /* Extended vector register.  */
   unsigned char reg_num;
-#define RegRip	((unsigned char ) ~0)
-#define RegEip	(RegRip - 1)
+#define RegIP	((unsigned char ) ~0)
 /* EIZ and RIZ are fake index registers.  */
-#define RegEiz	(RegEip - 1)
-#define RegRiz	(RegEiz - 1)
+#define RegIZ	(RegIP - 1)
 /* FLAT is a fake segment register (Intel mode).  */
 #define RegFlat     ((unsigned char) ~0)
   signed char dw2_regnum[2];
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl
index d0ce53f..b3cb539 100644
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -283,14 +283,14 @@ bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
 bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
 bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval
 bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval
-// No type will make these registers rejected for all purposes except
+// No Reg will make these registers rejected for all purposes except
 // for addressing.  This saves creating one extra type for RIP/EIP.
-rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
-eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
-// No type will make these registers rejected for all purposes except
+rip, Qword, RegRex64, RegIP, Dw2Inval, 16
+eip, Dword, RegRex64, RegIP, 8, Dw2Inval
+// No Reg will make these registers rejected for all purposes except
 // for addressing.
-riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval
-eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
+riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
+eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
 // fp regs.
 st(0), FloatReg|Acc, 0, 0, 11, 33
 st(1), FloatReg, 0, 1, 12, 34
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 9493816..2bb6a34 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -73973,24 +73973,24 @@ const reg_entry i386_regtab[] =
     0, 3, { Dw2Inval, Dw2Inval } },
   { "rip",
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
 	0, 0 } },
-    RegRex64, RegRip, { Dw2Inval, 16 } },
+    RegRex64, RegIP, { Dw2Inval, 16 } },
   { "eip",
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0 } },
-    RegRex64, RegEip, { 8, Dw2Inval } },
+    RegRex64, RegIP, { 8, Dw2Inval } },
   { "riz",
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
 	0, 0 } },
-    RegRex64, RegRiz, { Dw2Inval, Dw2Inval } },
+    RegRex64, RegIZ, { Dw2Inval, Dw2Inval } },
   { "eiz",
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0 } },
-    0, RegEiz, { Dw2Inval, Dw2Inval } },
+    0, RegIZ, { Dw2Inval, Dw2Inval } },
   { "st(0)",
     { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,