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author | srinath <srinath.parvathaneni@arm.com> | 2024-07-08 17:44:33 +0100 |
---|---|---|
committer | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-07-08 17:48:23 +0100 |
commit | de7a30ceaa4df45d05e12338744f1ad20f1e4032 (patch) | |
tree | ada1bfe600a444decbd27f1feea75a3e66da4fa4 /opcodes | |
parent | d6ec64f93d13c4a4df5e9844a6ff93851ea643e8 (diff) | |
download | binutils-de7a30ceaa4df45d05e12338744f1ad20f1e4032.zip binutils-de7a30ceaa4df45d05e12338744f1ad20f1e4032.tar.gz binutils-de7a30ceaa4df45d05e12338744f1ad20f1e4032.tar.bz2 |
aarch64: Add support for sve2p1 pmov instruction.
This patch adds support for followign SVE2p1 instruction, spec is available here [1].
1. PMOV (to vector)
2. PMOV (to predicate)
Both pmov (to vector) and pmov (to predicate) have destination scalable vector
register and source scalable vector register respectively as an operand with no
suffix and optional index. To handle this case we have added 8 new operands in
this patch.
AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */
AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */
AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */
AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */
AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */
AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */
AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */
AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */
Since the index of the <Zd> operand is optional, the index part is
dropped in disassembly in both the cases of "no index" or "zero index".
As per spec: PMOV <Zd>{[<imm>]}, <Pn>.D
PMOV <Pn>.D, <Zd>{[<imm>]}
Example1:
Assembly: pmov z5[0], p6.d
Disassembly: pmov z5, p6.d
Assembly: pmov z5, p6.d
Disassembly: pmov z5, p6.d
Example2:
Assembly: pmov p4.b, z5[0]
Disassembly: pmov p4.b, z5
Assembly: pmov p4.b, z5
Disassembly: pmov p4.b, z5
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/aarch64-asm-2.c | 40 | ||||
-rw-r--r-- | opcodes/aarch64-dis-2.c | 492 | ||||
-rw-r--r-- | opcodes/aarch64-opc-2.c | 8 | ||||
-rw-r--r-- | opcodes/aarch64-opc.c | 34 | ||||
-rw-r--r-- | opcodes/aarch64-opc.h | 2 | ||||
-rw-r--r-- | opcodes/aarch64-tbl.h | 54 |
6 files changed, 409 insertions, 221 deletions
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 00d10f1..bfc2d80 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -687,12 +687,14 @@ aarch64_insert_operand (const aarch64_operand *self, case 267: case 268: case 269: + case 303: + case 307: return aarch64_ins_regno (self, info, code, inst, errors); case 6: case 119: case 120: - case 305: - case 308: + case 313: + case 316: return aarch64_ins_none (self, info, code, inst, errors); case 17: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -707,7 +709,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 37: case 38: case 39: - case 310: + case 318: return aarch64_ins_reglane (self, info, code, inst, errors); case 40: case 41: @@ -734,6 +736,12 @@ aarch64_insert_operand (const aarch64_operand *self, case 300: case 301: case 302: + case 304: + case 305: + case 306: + case 308: + case 309: + case 310: return aarch64_ins_simple_index (self, info, code, inst, errors); case 43: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -784,13 +792,13 @@ aarch64_insert_operand (const aarch64_operand *self, case 211: case 212: case 272: - case 303: - case 304: - case 306: - case 307: - case 309: + case 311: + case 312: case 314: case 315: + case 317: + case 322: + case 323: return aarch64_ins_imm (self, info, code, inst, errors); case 52: case 53: @@ -1002,16 +1010,16 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); case 284: return aarch64_ins_plain_shrimm (self, info, code, inst, errors); - case 311: - case 312: - case 313: - return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); - case 316: - case 317: - case 318: case 319: - return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 320: + case 321: + return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); + case 324: + case 325: + case 326: + case 327: + return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 328: return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 6458bbc..64407af 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -216,7 +216,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x000101x00xxxxxxxxxxxxxx luti4. */ - return 3401; + return 3409; } else { @@ -251,7 +251,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx01101xxxxxxxxxxxxxxxxx luti4. */ - return 3402; + return 3410; } } } @@ -375,7 +375,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010x11x1xxxx00xxxxxxxxxx movt. */ - return 3403; + return 3411; } } else @@ -1157,7 +1157,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000000101xxxxxxxxxxxxxxxx00xxx fmopa. */ - return 3469; + return 3477; } else { @@ -1165,7 +1165,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000000101xxxxxxxxxxxxxxxx01xxx fmopa. */ - return 3468; + return 3476; } } else @@ -1513,7 +1513,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xx0xxxxx1000xxx fmlall. */ - return 3462; + return 3470; } } } @@ -1543,7 +1543,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxxxxx1xxxxxx00xxxx fdot. */ - return 3447; + return 3455; } } else @@ -1915,7 +1915,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxxxxx0xxxxxx100xxx fmlall. */ - return 3461; + return 3469; } } } @@ -2020,7 +2020,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxxxxx1xxxxxx10xxxx fmlal. */ - return 3454; + return 3462; } } } @@ -2193,7 +2193,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxxxxx1xxxxxx11xxxx fmlal. */ - return 3453; + return 3461; } } } @@ -2235,7 +2235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010100xxxxxxxxxxxxxxxx0xxx fmlall. */ - return 3460; + return 3468; } else { @@ -2603,7 +2603,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx0xxxxxx111xxx fdot. */ - return 3440; + return 3448; } else { @@ -2672,7 +2672,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx001xxx fdot. */ - return 3441; + return 3449; } else { @@ -2751,7 +2751,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011100xxxxxxx0xxxxxxx0xxxx fmlal. */ - return 3452; + return 3460; } else { @@ -2806,7 +2806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxx0xx01xxxxx00xxxx fvdotb. */ - return 3471; + return 3479; } else { @@ -2824,7 +2824,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxxxxx0xxxxxx10xxxx fdot. */ - return 3446; + return 3454; } } } @@ -2898,7 +2898,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxxxxx1xxxxxx10xxxx fvdot. */ - return 3470; + return 3478; } } } @@ -2978,7 +2978,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx01xxxxxx1xxxx fvdott. */ - return 3472; + return 3480; } else { @@ -3155,7 +3155,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx000xxxx10000x fmlall. */ - return 3466; + return 3474; } else { @@ -3163,7 +3163,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx000xxxx10000x fmlall. */ - return 3467; + return 3475; } } } @@ -3218,7 +3218,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx000xxxxx00x1x fmlall. */ - return 3464; + return 3472; } else { @@ -3226,7 +3226,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx000xxxxx00x1x fmlall. */ - return 3465; + return 3473; } } } @@ -3280,7 +3280,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx100xxxx100xxx fdot. */ - return 3450; + return 3458; } else { @@ -3288,7 +3288,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx100xxxx100xxx fdot. */ - return 3451; + return 3459; } } } @@ -3350,7 +3350,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx00xx010xxxx1000xx fmlal. */ - return 3458; + return 3466; } else { @@ -3358,7 +3358,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx10xx010xxxx1000xx fmlal. */ - return 3459; + return 3467; } } } @@ -3413,7 +3413,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx010xxxxx001xx fmlal. */ - return 3456; + return 3464; } else { @@ -3421,7 +3421,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx010xxxxx001xx fmlal. */ - return 3457; + return 3465; } } } @@ -3490,7 +3490,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx001xxxxx000xx fmlall. */ - return 3463; + return 3471; } } else @@ -3573,7 +3573,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx011xxxxx00xxx fmlal. */ - return 3455; + return 3463; } } else @@ -3594,7 +3594,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x00xx111xxxxx00xxx fadd. */ - return 3404; + return 3412; } } else @@ -3613,7 +3613,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x10xx111xxxxx00xxx fadd. */ - return 3405; + return 3413; } } } @@ -3739,7 +3739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx100xxxx110xxx fdot. */ - return 3444; + return 3452; } else { @@ -3747,7 +3747,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx100xxxx110xxx fdot. */ - return 3445; + return 3453; } } } @@ -4038,7 +4038,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx100xxxxx01xxx fdot. */ - return 3448; + return 3456; } else { @@ -4046,7 +4046,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx100xxxxx01xxx fdot. */ - return 3449; + return 3457; } } } @@ -4317,7 +4317,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x00xx111xxxxx01xxx fsub. */ - return 3406; + return 3414; } } else @@ -4336,7 +4336,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x10xx111xxxxx01xxx fsub. */ - return 3407; + return 3415; } } } @@ -4398,7 +4398,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx100xxxxx11xxx fdot. */ - return 3442; + return 3450; } else { @@ -4406,7 +4406,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx100xxxxx11xxx fdot. */ - return 3443; + return 3451; } } } @@ -4941,7 +4941,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx101000xx1x0xxxx0 fscale. */ - return 3378; + return 3386; } } else @@ -5089,7 +5089,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x0100100111000xxxx0xxxxx fcvt. */ - return 3375; + return 3383; } else { @@ -5097,7 +5097,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x1100100111000xxxx0xxxxx bfcvt. */ - return 3370; + return 3378; } } else @@ -5106,7 +5106,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx110100111000xxxx0xxxxx fcvt. */ - return 3376; + return 3384; } } else @@ -5157,7 +5157,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx100111000xxxx1xxxxx fcvtn. */ - return 3377; + return 3385; } } } @@ -5240,7 +5240,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010010x110111000xxxxxxxxx0 f1cvt. */ - return 3371; + return 3379; } else { @@ -5248,7 +5248,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011010x110111000xxxxxxxxx0 f2cvt. */ - return 3372; + return 3380; } } else @@ -5259,7 +5259,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010110x110111000xxxxxxxxx0 bf1cvt. */ - return 3366; + return 3374; } else { @@ -5267,7 +5267,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011110x110111000xxxxxxxxx0 bf2cvt. */ - return 3367; + return 3375; } } } @@ -5302,7 +5302,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001001xxx10111000xxxxxxxxx1 f1cvtl. */ - return 3373; + return 3381; } else { @@ -5310,7 +5310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxx10111000xxxxxxxxx1 f2cvtl. */ - return 3374; + return 3382; } } else @@ -5321,7 +5321,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001011xxx10111000xxxxxxxxx1 bf1cvtl. */ - return 3368; + return 3376; } else { @@ -5329,7 +5329,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxx10111000xxxxxxxxx1 bf2cvtl. */ - return 3369; + return 3377; } } } @@ -5598,7 +5598,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1100xx100xxxx0 fscale. */ - return 3380; + return 3388; } } else @@ -5774,7 +5774,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1010xx100xxxx0 fscale. */ - return 3379; + return 3387; } else { @@ -5782,7 +5782,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1110xx100xxxx0 fscale. */ - return 3381; + return 3389; } } } @@ -10950,7 +10950,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x11010000xxxxxxx1xxxxxxxxxxxxx addpt. */ - return 3382; + return 3390; } else { @@ -10958,7 +10958,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010000xxxxxxx1xxxxxxxxxxxxx subpt. */ - return 3383; + return 3391; } } } @@ -11876,7 +11876,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxxx1011x11xxxxx0xxxxxxxxxxxxxxx maddpt. */ - return 3384; + return 3392; } else { @@ -11884,7 +11884,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxxx1011x11xxxxx1xxxxxxxxxxxxxxx msubpt. */ - return 3385; + return 3393; } } } @@ -11969,7 +11969,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx000100000xxxxxxxxxxxxx addpt. */ - return 3386; + return 3394; } else { @@ -12076,7 +12076,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx000101000xxxxxxxxxxxxx subpt. */ - return 3388; + return 3396; } else { @@ -12281,7 +12281,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx1xxxxx000010xxxxxxxxxx addpt. */ - return 3387; + return 3395; } else { @@ -12322,7 +12322,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx1xxxxx000011xxxxxxxxxx subpt. */ - return 3389; + return 3397; } else { @@ -13980,7 +13980,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx110100xxxxxxxxxx mlapt. */ - return 3391; + return 3399; } } else @@ -14010,7 +14010,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx110110xxxxxxxxxx madpt. */ - return 3390; + return 3398; } } } @@ -15164,7 +15164,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 110001x0x00xxxxx101xxxxxxxxxxxxx ld1q. */ - return 3327; + return 3335; } else { @@ -16696,7 +16696,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0x00xxxxx000xxxxxxxxxxxxx st3q. */ - return 3336; + return 3344; } else { @@ -16706,7 +16706,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0010xxxxx000xxxxxxxxxxxxx st2q. */ - return 3335; + return 3343; } else { @@ -16714,7 +16714,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0110xxxxx000xxxxxxxxxxxxx st4q. */ - return 3337; + return 3345; } } } @@ -17380,7 +17380,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x0xx01xxxx111xxxxxxxxxxxxx ld2q. */ - return 3328; + return 3336; } } } @@ -17516,7 +17516,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x0xx1xxxxx100xxxxxxxxxxxxx ld2q. */ - return 3331; + return 3339; } } else @@ -17661,7 +17661,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x00x1xxxxx000xxxxxxxxxxxxx st2q. */ - return 3338; + return 3346; } } else @@ -17704,7 +17704,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0101xxxxx000xxxxxxxxxxxxx st3q. */ - return 3339; + return 3347; } } else @@ -17745,7 +17745,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0111xxxxx000xxxxxxxxxxxxx st4q. */ - return 3340; + return 3348; } } } @@ -17774,7 +17774,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0001xxxxx0100x1xxxxxxxxxx fdot. */ - return 3427; + return 3435; } } else @@ -17783,7 +17783,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0001xxxxx0101xxxxxxxxxxxx fmlalb. */ - return 3429; + return 3437; } } else @@ -17824,7 +17824,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx0101xxxxxxxxxxxx fmlalt. */ - return 3439; + return 3447; } } else @@ -17857,7 +17857,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xx1xxxxxxxxxx fdot. */ - return 3425; + return 3433; } } else @@ -17928,7 +17928,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx100010xxxxxxxxxx fmlallbb. */ - return 3430; + return 3438; } } else @@ -17937,7 +17937,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1000x1xxxxxxxxxx fdot. */ - return 3426; + return 3434; } } else @@ -17946,7 +17946,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1100xxxxxxxxxxxx fmlallbb. */ - return 3431; + return 3439; } } else @@ -17955,7 +17955,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1x01xxxxxxxxxxxx fmlallbt. */ - return 3432; + return 3440; } } else @@ -17982,7 +17982,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx100010xxxxxxxxxx fmlalb. */ - return 3428; + return 3436; } } else @@ -18000,7 +18000,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx1100xxxxxxxxxxxx fmlalltb. */ - return 3435; + return 3443; } } else @@ -18009,7 +18009,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx1x01xxxxxxxxxxxx fmlalt. */ - return 3438; + return 3446; } } else @@ -18042,7 +18042,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx100xx1xxxxxxxxxx fdot. */ - return 3424; + return 3432; } } else @@ -18051,7 +18051,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx110xxxxxxxxxxxxx fmlallbt. */ - return 3433; + return 3441; } } else @@ -18083,7 +18083,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx110xxxxxxxxxxxxx fmlalltt. */ - return 3437; + return 3445; } } else @@ -18382,7 +18382,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0xx1xxxxx001xxxxxxxxxxxxx st1q. */ - return 3334; + return 3342; } } else @@ -18397,7 +18397,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1010xxxxxxxxxxxx fmlalltb. */ - return 3434; + return 3442; } else { @@ -18405,7 +18405,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1011xxxxxxxxxxxx fmlalltt. */ - return 3436; + return 3444; } } else @@ -19057,11 +19057,11 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 16) & 0x1) == 0) { - if (((word >> 17) & 0x1) == 0) + if (((word >> 19) & 0x1) == 0) { - if (((word >> 18) & 0x1) == 0) + if (((word >> 17) & 0x1) == 0) { - if (((word >> 19) & 0x1) == 0) + if (((word >> 18) & 0x1) == 0) { if (((word >> 20) & 0x1) == 0) { @@ -19082,59 +19082,147 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 000001x1xx1x1000001110xxxxxxxxxx - rev. */ - return 1869; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 000001x1xx100100001110xxxxxxxxxx + insr. */ + return 1559; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 000001x1xx110100001110xxxxxxxxxx + insr. */ + return 1560; + } } } else { - if (((word >> 20) & 0x1) == 0) + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 000001x1xx1x0x10001110xxxxxxxxxx + uunpklo. */ + return 2080; + } + } + else + { + if (((word >> 20) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 000001x1xx10x100001110xxxxxxxxxx - insr. */ - return 1559; + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 18) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 000001x1001010x0001110xxxxxxxxxx + pmov. */ + return 3327; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 000001x1001011x0001110xxxxxxxxxx + pmov. */ + return 3328; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 000001x101101xx0001110xxxxxxxxxx + pmov. */ + return 3329; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 000001x1xx11x100001110xxxxxxxxxx - insr. */ - return 1560; + 000001x11x101xx0001110xxxxxxxxxx + pmov. */ + return 3330; } } - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 000001x1xx1xxx10001110xxxxxxxxxx - uunpklo. */ - return 2080; + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 000001x1xx111xx0001110xxxxxxxxxx + rev. */ + return 1869; + } } } else { - if (((word >> 17) & 0x1) == 0) + if (((word >> 19) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 000001x1xx1xxx01001110xxxxxxxxxx - sunpkhi. */ - return 2016; + if (((word >> 17) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 000001x1xx1x0x01001110xxxxxxxxxx + sunpkhi. */ + return 2016; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 000001x1xx1x0x11001110xxxxxxxxxx + uunpkhi. */ + return 2079; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 000001x1xx1xxx11001110xxxxxxxxxx - uunpkhi. */ - return 2079; + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 18) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 000001x1001x10x1001110xxxxxxxxxx + pmov. */ + return 3331; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 000001x1001x11x1001110xxxxxxxxxx + pmov. */ + return 3332; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 000001x1011x1xx1001110xxxxxxxxxx + pmov. */ + return 3333; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 000001x11x1x1xx1001110xxxxxxxxxx + pmov. */ + return 3334; + } } } } @@ -20772,7 +20860,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101100xxxxxxxxxx luti2. */ - return 3396; + return 3404; } } else @@ -20781,7 +20869,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101x10xxxxxxxxxx luti2. */ - return 3397; + return 3405; } } else @@ -20794,7 +20882,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101001xxxxxxxxxx luti4. */ - return 3398; + return 3406; } else { @@ -20802,7 +20890,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101101xxxxxxxxxx luti4. */ - return 3399; + return 3407; } } else @@ -20811,7 +20899,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101x11xxxxxxxxxx luti4. */ - return 3400; + return 3408; } } } @@ -21762,7 +21850,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x00xxxxxxxxxx f1cvt. */ - return 3358; + return 3366; } else { @@ -21770,7 +21858,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x10xxxxxxxxxx bf1cvt. */ - return 3354; + return 3362; } } else @@ -21781,7 +21869,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x01xxxxxxxxxx f2cvt. */ - return 3359; + return 3367; } else { @@ -21789,7 +21877,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x11xxxxxxxxxx bf2cvt. */ - return 3355; + return 3363; } } } @@ -21834,7 +21922,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x00xxxxxxxxxx fcvtn. */ - return 3363; + return 3371; } else { @@ -21842,7 +21930,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x10xxxxxxxxxx bfcvtn. */ - return 3362; + return 3370; } } else @@ -21853,7 +21941,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x01xxxxxxxxxx fcvtnb. */ - return 3364; + return 3372; } else { @@ -21861,7 +21949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x11xxxxxxxxxx fcvtnt. */ - return 3365; + return 3373; } } } @@ -21922,7 +22010,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x00xxxxxxxxxx f1cvtlt. */ - return 3360; + return 3368; } else { @@ -21930,7 +22018,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x10xxxxxxxxxx bf1cvtlt. */ - return 3356; + return 3364; } } else @@ -21941,7 +22029,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x01xxxxxxxxxx f2cvtlt. */ - return 3361; + return 3369; } else { @@ -21949,7 +22037,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x11xxxxxxxxxx bf2cvtlt. */ - return 3357; + return 3365; } } } @@ -23275,7 +23363,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x01xxxx111xxxxxxxxxxxxx ld3q. */ - return 3329; + return 3337; } else { @@ -23283,7 +23371,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x01xxxx111xxxxxxxxxxxxx ld4q. */ - return 3330; + return 3338; } } } @@ -24456,7 +24544,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx100xxxxxxxxxxxxx ld3q. */ - return 3332; + return 3340; } else { @@ -24464,7 +24552,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx100xxxxxxxxxxxxx ld4q. */ - return 3333; + return 3341; } } else @@ -26529,7 +26617,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110100xxxxxxxx100xxxxxxxxxx luti2. */ - return 3392; + return 3400; } } } @@ -26543,7 +26631,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxxxx000xxxxxxxxxx luti4. */ - return 3394; + return 3402; } else { @@ -26551,7 +26639,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxxxx100xxxxxxxxxx luti4. */ - return 3395; + return 3403; } } else @@ -26560,7 +26648,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110110xxxxxxxxx00xxxxxxxxxx luti2. */ - return 3393; + return 3401; } } } @@ -26676,7 +26764,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x00xxxxxx10001xxxxxxxxxx fmlallbb. */ - return 3416; + return 3424; } else { @@ -26684,7 +26772,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x00xxxxxx10001xxxxxxxxxx fmlalltb. */ - return 3418; + return 3426; } } else @@ -26695,7 +26783,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x10xxxxxx10001xxxxxxxxxx fmlallbt. */ - return 3417; + return 3425; } else { @@ -26703,7 +26791,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x10xxxxxx10001xxxxxxxxxx fmlalltt. */ - return 3419; + return 3427; } } } @@ -26791,7 +26879,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x00xxxxxx11101xxxxxxxxxx fcvtn. */ - return 3349; + return 3357; } else { @@ -26799,7 +26887,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x00xxxxxx11101xxxxxxxxxx fcvtn2. */ - return 3350; + return 3358; } } else @@ -26808,7 +26896,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110x10xxxxxx11101xxxxxxxxxx fcvtn. */ - return 3351; + return 3359; } } } @@ -26951,7 +27039,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110x00xxxxxx11111xxxxxxxxxx fdot. */ - return 3408; + return 3416; } else { @@ -26961,7 +27049,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxx11111xxxxxxxxxx fdot. */ - return 3410; + return 3418; } else { @@ -26971,7 +27059,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110110xxxxxx11111xxxxxxxxxx fmlalb. */ - return 3412; + return 3420; } else { @@ -26979,7 +27067,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110110xxxxxx11111xxxxxxxxxx fmlalt. */ - return 3413; + return 3421; } } } @@ -27253,7 +27341,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110110xxxxx0x1111xxxxxxxxxx fscale. */ - return 3352; + return 3360; } } } @@ -28645,7 +28733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110001xxxx1011110xxxxxxxxxx f1cvtl. */ - return 3345; + return 3353; } else { @@ -28653,7 +28741,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110001xxxx1011110xxxxxxxxxx f1cvtl2. */ - return 3346; + return 3354; } } else @@ -28664,7 +28752,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110101xxxx1011110xxxxxxxxxx bf1cvtl. */ - return 3341; + return 3349; } else { @@ -28672,7 +28760,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110101xxxx1011110xxxxxxxxxx bf1cvtl2. */ - return 3342; + return 3350; } } } @@ -28686,7 +28774,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110011xxxx1011110xxxxxxxxxx f2cvtl. */ - return 3347; + return 3355; } else { @@ -28694,7 +28782,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110011xxxx1011110xxxxxxxxxx f2cvtl2. */ - return 3348; + return 3356; } } else @@ -28705,7 +28793,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110111xxxx1011110xxxxxxxxxx bf2cvtl. */ - return 3343; + return 3351; } else { @@ -28713,7 +28801,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110111xxxx1011110xxxxxxxxxx bf2cvtl2. */ - return 3344; + return 3352; } } } @@ -30712,7 +30800,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011101x1xxxxx111111xxxxxxxxxx fscale. */ - return 3353; + return 3361; } } } @@ -32428,7 +32516,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx0000x0xxxxxxxxxx fdot. */ - return 3409; + return 3417; } else { @@ -32458,7 +32546,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx0000x0xxxxxxxxxx fdot. */ - return 3411; + return 3419; } else { @@ -32468,7 +32556,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx0000x0xxxxxxxxxx fmlalb. */ - return 3414; + return 3422; } else { @@ -32476,7 +32564,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx0000x0xxxxxxxxxx fmlalt. */ - return 3415; + return 3423; } } } @@ -33018,7 +33106,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x010111100xxxxxx1000x0xxxxxxxxxx fmlallbb. */ - return 3420; + return 3428; } else { @@ -33026,7 +33114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x110111100xxxxxx1000x0xxxxxxxxxx fmlalltb. */ - return 3422; + return 3430; } } else @@ -33057,7 +33145,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111x1xxxxxx1000x0xxxxxxxxxx fmlallbt. */ - return 3421; + return 3429; } else { @@ -33065,7 +33153,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111x1xxxxxx1000x0xxxxxxxxxx fmlalltt. */ - return 3423; + return 3431; } } } @@ -34553,12 +34641,14 @@ aarch64_extract_operand (const aarch64_operand *self, case 267: case 268: case 269: + case 303: + case 307: return aarch64_ext_regno (self, info, code, inst, errors); case 6: case 119: case 120: - case 305: - case 308: + case 313: + case 316: return aarch64_ext_none (self, info, code, inst, errors); case 11: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -34578,7 +34668,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 37: case 38: case 39: - case 310: + case 318: return aarch64_ext_reglane (self, info, code, inst, errors); case 40: case 41: @@ -34605,6 +34695,12 @@ aarch64_extract_operand (const aarch64_operand *self, case 300: case 301: case 302: + case 304: + case 305: + case 306: + case 308: + case 309: + case 310: return aarch64_ext_simple_index (self, info, code, inst, errors); case 43: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -34656,13 +34752,13 @@ aarch64_extract_operand (const aarch64_operand *self, case 211: case 212: case 272: - case 303: - case 304: - case 306: - case 307: - case 309: + case 311: + case 312: case 314: case 315: + case 317: + case 322: + case 323: return aarch64_ext_imm (self, info, code, inst, errors); case 52: case 53: @@ -34876,16 +34972,16 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); case 284: return aarch64_ext_plain_shrimm (self, info, code, inst, errors); - case 311: - case 312: - case 313: - return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); - case 316: - case 317: - case 318: case 319: - return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 320: + case 321: + return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); + case 324: + case 325: + case 326: + case 327: + return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 328: return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index d42fea4..926b310 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -327,6 +327,14 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_14}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_15}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX4_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm4_14}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register with option zero index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm17_1}, "an SVE vector register with optional one bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm17_2}, "an SVE vector register with optional two bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_SVE_i3h, FLD_imm17_2}, "an SVE vector register with optional three bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register with option zero index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd, FLD_imm17_1}, "an SVE vector register with optional one bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd, FLD_imm17_2}, "an SVE vector register with optional two bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd, FLD_SVE_i3h, FLD_imm17_2}, "an SVE vector register with optional three bit index"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_10}, "VLx2 or VLx4"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_13}, "VLx2 or VLx4"}, {AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "ZT0"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 0b09055..0e72610 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -387,6 +387,8 @@ const aarch64_field fields[] = { 5, 14 }, /* imm14: in test bit and branch instructions. */ { 0, 16 }, /* imm16_0: in udf instruction. */ { 5, 16 }, /* imm16_5: in exception instructions. */ + { 17, 1 }, /* imm17_1: in 1 bit element index. */ + { 17, 2 }, /* imm17_2: in 2 bits element index. */ { 5, 19 }, /* imm19: e.g. in CBZ. */ { 0, 26 }, /* imm26: in unconditional branch instructions. */ { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */ @@ -1874,6 +1876,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SME_Zn_INDEX3_14: case AARCH64_OPND_SME_Zn_INDEX3_15: case AARCH64_OPND_SME_Zn_INDEX4_14: + case AARCH64_OPND_SVE_Zn0_INDEX: + case AARCH64_OPND_SVE_Zn1_17_INDEX: + case AARCH64_OPND_SVE_Zn2_18_INDEX: + case AARCH64_OPND_SVE_Zn3_22_INDEX: + case AARCH64_OPND_SVE_Zd0_INDEX: + case AARCH64_OPND_SVE_Zd1_17_INDEX: + case AARCH64_OPND_SVE_Zd2_18_INDEX: + case AARCH64_OPND_SVE_Zd3_22_INDEX: size = get_operand_fields_width (get_operand_from_code (type)) - 5; if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, (1 << size) - 1)) @@ -4248,11 +4258,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zt: case AARCH64_OPND_SME_Zm: if (opnd->qualifier == AARCH64_OPND_QLF_NIL) - snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno)); + snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno)); else - snprintf (buf, size, "%s", - style_reg (styler, "z%d.%s", opnd->reg.regno, - aarch64_get_qualifier_name (opnd->qualifier))); + snprintf (buf, size, "%s", + style_reg (styler, "z%d.%s", opnd->reg.regno, + aarch64_get_qualifier_name (opnd->qualifier))); break; case AARCH64_OPND_SVE_ZnxN: @@ -4307,6 +4317,22 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, style_imm (styler, "%" PRIi64, opnd->reglane.index)); break; + case AARCH64_OPND_SVE_Zn0_INDEX: + case AARCH64_OPND_SVE_Zn1_17_INDEX: + case AARCH64_OPND_SVE_Zn2_18_INDEX: + case AARCH64_OPND_SVE_Zn3_22_INDEX: + case AARCH64_OPND_SVE_Zd0_INDEX: + case AARCH64_OPND_SVE_Zd1_17_INDEX: + case AARCH64_OPND_SVE_Zd2_18_INDEX: + case AARCH64_OPND_SVE_Zd3_22_INDEX: + if (opnd->reglane.index == 0) + snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno)); + else + snprintf (buf, size, "%s[%s]", + style_reg (styler, "z%d", opnd->reglane.regno), + style_imm (styler, "%" PRIi64, opnd->reglane.index)); + break; + case AARCH64_OPND_SME_ZAda_1b: case AARCH64_OPND_SME_ZAda_2b: case AARCH64_OPND_SME_ZAda_3b: diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index e97ea5d..4931096 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -191,6 +191,8 @@ enum aarch64_field_kind FLD_imm14, FLD_imm16_0, FLD_imm16_5, + FLD_imm17_1, + FLD_imm17_2, FLD_imm19, FLD_imm26, FLD_immb, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 0bd2cc0..ad0d8ae 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1567,6 +1567,10 @@ QLF3(S_B,P_Z,S_B), \ QLF3(S_B,P_M,S_B), \ } +#define OP_SVE_BU \ +{ \ + QLF2(S_B,NIL), \ +} #define OP_SVE_BUB \ { \ QLF3(S_B,NIL,S_B), \ @@ -1869,9 +1873,21 @@ { \ QLF3(S_S,P_Z,NIL), \ } -#define OP_SVE_UB \ -{ \ - QLF2(NIL,S_B), \ +#define OP_SVE_UB \ +{ \ + QLF2(NIL,S_B), \ +} +#define OP_SVE_UD \ +{ \ + QLF2(NIL,S_D), \ +} +#define OP_SVE_UH \ +{ \ + QLF2(NIL,S_H), \ +} +#define OP_SVE_US \ +{ \ + QLF2(NIL,S_S), \ } #define OP_SVE_UUD \ { \ @@ -6649,6 +6665,16 @@ const struct aarch64_opcode aarch64_opcode_table[] = SVE2p1_INSN("zipq1",0x4400e000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), SVE2p1_INSN("zipq2",0x4400e400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), + SVE2p1_INSN("pmov",0x052a3800, 0xfffffc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn0_INDEX), OP_SVE_BU, 0, 0), + SVE2p1_INSN("pmov",0x052c3800, 0xfffdfc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn1_17_INDEX), OP_SVE_HU, 0, 0), + SVE2p1_INSN("pmov",0x05683800, 0xfff9fc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn2_18_INDEX), OP_SVE_SU, 0, 0), + SVE2p1_INSN("pmov",0x05a83800, 0xffb9fc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn3_22_INDEX), OP_SVE_DU, 0, 0), + + SVE2p1_INSN("pmov",0x052b3800, 0xfffffe00, sve_misc, 0, OP2 (SVE_Zd0_INDEX, SVE_Pg4_5), OP_SVE_UB, 0, 0), + SVE2p1_INSN("pmov",0x052d3800, 0xfffdfe00, sve_misc, 0, OP2 (SVE_Zd1_17_INDEX, SVE_Pg4_5), OP_SVE_UH, 0, 0), + SVE2p1_INSN("pmov",0x05693800, 0xfff9fe00, sve_misc, 0, OP2 (SVE_Zd2_18_INDEX, SVE_Pg4_5), OP_SVE_US, 0, 0), + SVE2p1_INSN("pmov",0x05a93800, 0xffb9fe00, sve_misc, 0, OP2 (SVE_Zd3_22_INDEX, SVE_Pg4_5), OP_SVE_UD, 0, 0), + SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0), SVE2p1_INSN("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, F_OD (2), 0), SVE2p1_INSN("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, F_OD (3), 0), @@ -7478,6 +7504,28 @@ const struct aarch64_opcode aarch64_opcode_table[] = F(FLD_SVE_Zn, FLD_imm3_15), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX4_14", 0, \ F(FLD_SVE_Zn, FLD_imm4_14), "an indexed SVE vector register") \ + Y(SVE_REG, regno, "SVE_Zn0_INDEX", 0, F(FLD_SVE_Zn), \ + "an SVE vector register with option zero index") \ + Y(SVE_REG, simple_index, "SVE_Zn1_17_INDEX", 0, \ + F(FLD_SVE_Zn, FLD_imm17_1), \ + "an SVE vector register with optional one bit index") \ + Y(SVE_REG, simple_index, "SVE_Zn2_18_INDEX", 0, \ + F(FLD_SVE_Zn, FLD_imm17_2), \ + "an SVE vector register with optional two bit index") \ + Y(SVE_REG, simple_index, "SVE_Zn3_22_INDEX", 0, \ + F(FLD_SVE_Zn, FLD_SVE_i3h, FLD_imm17_2), \ + "an SVE vector register with optional three bit index") \ + Y(SVE_REG, regno, "SVE_Zd0_INDEX", 0, F(FLD_SVE_Zd), \ + "an SVE vector register with option zero index") \ + Y(SVE_REG, simple_index, "SVE_Zd1_17_INDEX", 0, \ + F(FLD_SVE_Zd, FLD_imm17_1), \ + "an SVE vector register with optional one bit index") \ + Y(SVE_REG, simple_index, "SVE_Zd2_18_INDEX", 0, \ + F(FLD_SVE_Zd, FLD_imm17_2), \ + "an SVE vector register with optional two bit index") \ + Y(SVE_REG, simple_index, "SVE_Zd3_22_INDEX", 0, \ + F(FLD_SVE_Zd, FLD_SVE_i3h, FLD_imm17_2), \ + "an SVE vector register with optional three bit index") \ Y(IMMEDIATE, imm, "SME_VLxN_10", 0, F(FLD_SME_VL_10), \ "VLx2 or VLx4") \ Y(IMMEDIATE, imm, "SME_VLxN_13", 0, F(FLD_SME_VL_13), \ |