Update function declarations to ISO C90 formatting

93 files changed, 7693 insertions, 9412 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1f80d89..2269c7c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,62 @@
+2005-07-01  Nick Clifton  <nickc@redhat.com>
+
+	* a29k-dis.c: Update to ISO C90 style function declarations and
+	fix formatting.
+	* alpha-opc.c: Likewise.
+	* arc-dis.c: Likewise.
+	* arc-opc.c: Likewise.
+	* avr-dis.c: Likewise.
+	* cgen-asm.in: Likewise.
+	* cgen-dis.in: Likewise.
+	* cgen-ibld.in: Likewise.
+	* cgen-opc.c: Likewise.
+	* cris-dis.c: Likewise.
+	* d10v-dis.c: Likewise.
+	* d30v-dis.c: Likewise.
+	* d30v-opc.c: Likewise.
+	* dis-buf.c: Likewise.
+	* dlx-dis.c: Likewise.
+	* h8300-dis.c: Likewise.
+	* h8500-dis.c: Likewise.
+	* hppa-dis.c: Likewise.
+	* i370-dis.c: Likewise.
+	* i370-opc.c: Likewise.
+	* m10200-dis.c: Likewise.
+	* m10300-dis.c: Likewise.
+	* m68k-dis.c: Likewise.
+	* m88k-dis.c: Likewise.
+	* mips-dis.c: Likewise.
+	* mmix-dis.c: Likewise.
+	* msp430-dis.c: Likewise.
+	* ns32k-dis.c: Likewise.
+	* or32-dis.c: Likewise.
+	* or32-opc.c: Likewise.
+	* pdp11-dis.c: Likewise.
+	* pj-dis.c: Likewise.
+	* s390-dis.c: Likewise.
+	* sh-dis.c: Likewise.
+	* sh64-dis.c: Likewise.
+	* sparc-dis.c: Likewise.
+	* sparc-opc.c: Likewise.
+	* sysdep.h: Likewise.
+	* tic30-dis.c: Likewise.
+	* tic4x-dis.c: Likewise.
+	* tic80-dis.c: Likewise.
+	* v850-dis.c: Likewise.
+	* v850-opc.c: Likewise.
+	* vax-dis.c: Likewise.
+	* w65-dis.c: Likewise.
+	* z8kgen.c: Likewise.
+	
+	* fr30-*: Regenerate.
+	* frv-*: Regenerate.
+	* ip2k-*: Regenerate.
+	* iq2000-*: Regenerate.
+	* m32r-*: Regenerate.
+	* ms1-*: Regenerate.
+	* openrisc-*: Regenerate.
+	* xstormy16-*: Regenerate.
+
 2005-06-23  Ben Elliston  <bje@gnu.org>
 
 	* m68k-dis.c: Use ISC C90.
diff --git a/opcodes/a29k-dis.c b/opcodes/a29k-dis.c
index 0a04203..861e51b 100644
--- a/opcodes/a29k-dis.c
+++ b/opcodes/a29k-dis.c
@@ -3,46 +3,34 @@
    Free Software Foundation, Inc.
    Contributed by Cygnus Support.  Written by Jim Kingdon.
 
-This file is part of GDB.
+   This file is part of GDB and GNU Binutils.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include "sysdep.h"
 #include "dis-asm.h"
 #include "opcode/a29k.h"
 
-static void print_general PARAMS ((int, struct disassemble_info *));
-static void print_special PARAMS ((unsigned int, struct disassemble_info *));
-static int is_delayed_branch PARAMS ((int));
-static void find_bytes_little
-  PARAMS ((char *, unsigned char *, unsigned char *, unsigned char *,
-	   unsigned char *));
-static void find_bytes_big
-  PARAMS ((char *, unsigned char *, unsigned char *, unsigned char *,
-	   unsigned char *));
-static int print_insn PARAMS ((bfd_vma, struct disassemble_info *));
-
-
 /* Print a symbolic representation of a general-purpose
    register number NUM on STREAM.
    NUM is a number as found in the instruction, not as found in
    debugging symbols; it must be in the range 0-255.  */
+
 static void
-print_general (num, info)
-     int num;
-     struct disassemble_info *info;
+print_general (int num, struct disassemble_info *info)
 {
   if (num < 128)
     (*info->fprintf_func) (info->stream, "gr%d", num);
@@ -55,29 +43,31 @@ print_general (num, info)
    The mnemonics used by the AMD assembler are not quite the same
    as the ones in the User's Manual.  We use the ones that the
    assembler uses.  */
+
 static void
-print_special (num, info)
-     unsigned int num;
-     struct disassemble_info *info;
+print_special (unsigned int num, struct disassemble_info *info)
 {
   /* Register names of registers 0-SPEC0_NUM-1.  */
-  static char *spec0_names[] = {
-    "vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr",
-    "pc0", "pc1", "pc2", "mmu", "lru", "rsn", "rma0", "rmc0", "rma1", "rmc1",
-    "spc0", "spc1", "spc2", "iba0", "ibc0", "iba1", "ibc1", "dba", "dbc",
-    "cir", "cdr"
+  static char *spec0_names[] =
+    {
+      "vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr",
+      "pc0", "pc1", "pc2", "mmu", "lru", "rsn", "rma0", "rmc0", "rma1", "rmc1",
+      "spc0", "spc1", "spc2", "iba0", "ibc0", "iba1", "ibc1", "dba", "dbc",
+      "cir", "cdr"
     };
 #define SPEC0_NUM ((sizeof spec0_names) / (sizeof spec0_names[0]))
 
   /* Register names of registers 128-128+SPEC128_NUM-1.  */
-  static char *spec128_names[] = {
-    "ipc", "ipa", "ipb", "q", "alu", "bp", "fc", "cr"
+  static char *spec128_names[] =
+    {
+      "ipc", "ipa", "ipb", "q", "alu", "bp", "fc", "cr"
     };
 #define SPEC128_NUM ((sizeof spec128_names) / (sizeof spec128_names[0]))
 
   /* Register names of registers 160-160+SPEC160_NUM-1.  */
-  static char *spec160_names[] = {
-    "fpe", "inte", "fps", "sr163", "exop"
+  static char *spec160_names[] =
+    {
+      "fpe", "inte", "fps", "sr163", "exop"
     };
 #define SPEC160_NUM ((sizeof spec160_names) / (sizeof spec160_names[0]))
 
@@ -92,9 +82,9 @@ print_special (num, info)
 }
 
 /* Is an instruction with OPCODE a delayed branch?  */
+
 static int
-is_delayed_branch (opcode)
-     int opcode;
+is_delayed_branch (int opcode)
 {
   return (opcode == 0xa8 || opcode == 0xa9 || opcode == 0xa0 || opcode == 0xa1
 	  || opcode == 0xa4 || opcode == 0xa5
@@ -105,13 +95,13 @@ is_delayed_branch (opcode)
 }
 
 /* Now find the four bytes of INSN and put them in *INSN{0,8,16,24}.  */
+
 static void
-find_bytes_big (insn, insn0, insn8, insn16, insn24)
-     char *insn;
-     unsigned char *insn0;
-     unsigned char *insn8;
-     unsigned char *insn16;
-     unsigned char *insn24;
+find_bytes_big (char *insn,
+		unsigned char *insn0,
+		unsigned char *insn8,
+		unsigned char *insn16,
+		unsigned char *insn24)
 {
   *insn24 = insn[0];
   *insn16 = insn[1];
@@ -120,12 +110,11 @@ find_bytes_big (insn, insn0, insn8, insn16, insn24)
 }
 
 static void
-find_bytes_little (insn, insn0, insn8, insn16, insn24)
-     char *insn;
-     unsigned char *insn0;
-     unsigned char *insn8;
-     unsigned char *insn16;
-     unsigned char *insn24;
+find_bytes_little (char *insn,
+		   unsigned char *insn0,
+		   unsigned char *insn8,
+		   unsigned char *insn16,
+		   unsigned char *insn24)
 {
   *insn24 = insn[3];
   *insn16 = insn[2];
@@ -134,16 +123,14 @@ find_bytes_little (insn, insn0, insn8, insn16, insn24)
 }
 
 typedef void (*find_byte_func_type)
-     PARAMS ((char *, unsigned char *, unsigned char *,
-	      unsigned char *, unsigned char *));
+     (char *, unsigned char *, unsigned char *,
+      unsigned char *, unsigned char *);
 
 /* Print one instruction from MEMADDR on INFO->STREAM.
    Return the size of the instruction (always 4 on a29k).  */
 
 static int
-print_insn (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn (bfd_vma memaddr, struct disassemble_info *info)
 {
   /* The raw instruction.  */
   char insn[4];
@@ -169,11 +156,15 @@ print_insn (memaddr, info)
 
   printf ("%02x%02x%02x%02x ", insn24, insn16, insn8, insn0);
 
-  /* Handle the nop (aseq 0x40,gr1,gr1) specially */
-  if ((insn24==0x70) && (insn16==0x40) && (insn8==0x01) && (insn0==0x01)) {
-    (*info->fprintf_func) (info->stream,"nop");
-    return 4;
-  }
+  /* Handle the nop (aseq 0x40,gr1,gr1) specially.  */
+  if (   (insn24 == 0x70)
+      && (insn16 == 0x40)
+      && (insn8 == 0x01)
+      && (insn0 == 0x01))
+    {
+      (*info->fprintf_func) (info->stream,"nop");
+      return 4;
+    }
 
   /* The opcode is always in insn24.  */
   for (opcode = &a29k_opcodes[0];
@@ -206,18 +197,19 @@ print_insn (memaddr, info)
 		  break;
 
 		case 'x':
-		  (*info->fprintf_func) (info->stream, "0x%x", (insn16 << 8) + insn0);
+		  (*info->fprintf_func) (info->stream, "0x%x",
+					 (insn16 << 8) + insn0);
 		  break;
 
 		case 'h':
 		  /* This used to be %x for binutils.  */
 		  (*info->fprintf_func) (info->stream, "0x%x",
-				    (insn16 << 24) + (insn0 << 16));
+					 (insn16 << 24) + (insn0 << 16));
 		  break;
 
 		case 'X':
 		  (*info->fprintf_func) (info->stream, "%d",
-				    ((insn16 << 8) + insn0) | 0xffff0000);
+					 ((insn16 << 8) + insn0) | 0xffff0000);
 		  break;
 
 		case 'P':
@@ -274,7 +266,8 @@ print_insn (memaddr, info)
 		  break;
 
 		case 'F':
-		  (*info->fprintf_func) (info->stream, "%d", (insn16 >> 2) & 15);
+		  (*info->fprintf_func) (info->stream, "%d",
+					 (insn16 >> 2) & 15);
 		  break;
 
 		case 'C':
@@ -308,14 +301,14 @@ print_insn (memaddr, info)
 		     call _printf
 		     consth _foo
 		     */
-		  (*find_byte_func) (prev_insn, &prev_insn0, &prev_insn8,
-				     &prev_insn16, &prev_insn24);
+		  (*find_byte_func) (prev_insn, & prev_insn0, & prev_insn8,
+				     & prev_insn16, & prev_insn24);
 		  if (is_delayed_branch (prev_insn24))
 		    {
 		      errcode = (*info->read_memory_func)
-			(memaddr - 8, (bfd_byte *) &prev_insn[0], 4, info);
-		      (*find_byte_func) (prev_insn, &prev_insn0, &prev_insn8,
-					 &prev_insn16, &prev_insn24);
+			(memaddr - 8, (bfd_byte *) & prev_insn[0], 4, info);
+		      (*find_byte_func) (prev_insn, & prev_insn0, & prev_insn8,
+					 & prev_insn16, & prev_insn24);
 		    }
 		}
 
@@ -347,20 +340,18 @@ print_insn (memaddr, info)
 }
 
 /* Disassemble an big-endian a29k instruction.  */
+
 int
-print_insn_big_a29k (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_big_a29k (bfd_vma memaddr, struct disassemble_info *info)
 {
   info->private_data = (PTR) find_bytes_big;
   return print_insn (memaddr, info);
 }
 
 /* Disassemble a little-endian a29k instruction.  */
+
 int
-print_insn_little_a29k (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_little_a29k (bfd_vma memaddr, struct disassemble_info *info)
 {
   info->private_data = (PTR) find_bytes_little;
   return print_insn (memaddr, info);
diff --git a/opcodes/alpha-opc.c b/opcodes/alpha-opc.c
index f342e78..897de40 100644
--- a/opcodes/alpha-opc.c
+++ b/opcodes/alpha-opc.c
@@ -1,5 +1,5 @@
 /* alpha-opc.c -- Alpha AXP opcode list
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
    Contributed by Richard Henderson <rth@cygnus.com>,
    patterned after the PPC opcode handling written by Ian Lance Taylor.
@@ -54,28 +54,147 @@
    _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital
    Order Number EC-QAEQB-TE, preliminary revision dated April 1995.  */
 
-/* Local insertion and extraction functions */
-
-static unsigned insert_rba PARAMS((unsigned, int, const char **));
-static unsigned insert_rca PARAMS((unsigned, int, const char **));
-static unsigned insert_za PARAMS((unsigned, int, const char **));
-static unsigned insert_zb PARAMS((unsigned, int, const char **));
-static unsigned insert_zc PARAMS((unsigned, int, const char **));
-static unsigned insert_bdisp PARAMS((unsigned, int, const char **));
-static unsigned insert_jhint PARAMS((unsigned, int, const char **));
-static unsigned insert_ev6hwjhint PARAMS((unsigned, int, const char **));
-
-static int extract_rba PARAMS((unsigned, int *));
-static int extract_rca PARAMS((unsigned, int *));
-static int extract_za PARAMS((unsigned, int *));
-static int extract_zb PARAMS((unsigned, int *));
-static int extract_zc PARAMS((unsigned, int *));
-static int extract_bdisp PARAMS((unsigned, int *));
-static int extract_jhint PARAMS((unsigned, int *));
-static int extract_ev6hwjhint PARAMS((unsigned, int *));
+/* The RB field when it is the same as the RA field in the same insn.
+   This operand is marked fake.  The insertion function just copies
+   the RA field into the RB field, and the extraction function just
+   checks that the fields are the same. */
 
+static unsigned
+insert_rba (unsigned insn,
+	    int value ATTRIBUTE_UNUSED,
+	    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | (((insn >> 21) & 0x1f) << 16);
+}
+
+static int
+extract_rba (unsigned insn, int *invalid)
+{
+  if (invalid != (int *) NULL
+      && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
+    *invalid = 1;
+  return 0;
+}
+
+/* The same for the RC field.  */
+
+static unsigned
+insert_rca (unsigned insn,
+	    int value ATTRIBUTE_UNUSED,
+	    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | ((insn >> 21) & 0x1f);
+}
+
+static int
+extract_rca (unsigned insn, int *invalid)
+{
+  if (invalid != (int *) NULL
+      && ((insn >> 21) & 0x1f) != (insn & 0x1f))
+    *invalid = 1;
+  return 0;
+}
+
+/* Fake arguments in which the registers must be set to ZERO.  */
+
+static unsigned
+insert_za (unsigned insn,
+	   int value ATTRIBUTE_UNUSED,
+	   const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | (31 << 21);
+}
+
+static int
+extract_za (unsigned insn, int *invalid)
+{
+  if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
+    *invalid = 1;
+  return 0;
+}
+
+static unsigned
+insert_zb (unsigned insn,
+	   int value ATTRIBUTE_UNUSED,
+	   const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | (31 << 16);
+}
+
+static int
+extract_zb (unsigned insn, int *invalid)
+{
+  if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
+    *invalid = 1;
+  return 0;
+}
+
+static unsigned
+insert_zc (unsigned insn,
+	   int value ATTRIBUTE_UNUSED,
+	   const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | 31;
+}
+
+static int
+extract_zc (unsigned insn, int *invalid)
+{
+  if (invalid != (int *) NULL && (insn & 0x1f) != 31)
+    *invalid = 1;
+  return 0;
+}
+
+
+/* The displacement field of a Branch format insn.  */
+
+static unsigned
+insert_bdisp (unsigned insn, int value, const char **errmsg)
+{
+  if (errmsg != (const char **)NULL && (value & 3))
+    *errmsg = _("branch operand unaligned");
+  return insn | ((value / 4) & 0x1FFFFF);
+}
+
+static int
+extract_bdisp (unsigned insn, int *invalid ATTRIBUTE_UNUSED)
+{
+  return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
+}
+
+/* The hint field of a JMP/JSR insn.  */
+
+static unsigned
+insert_jhint (unsigned insn, int value, const char **errmsg)
+{
+  if (errmsg != (const char **)NULL && (value & 3))
+    *errmsg = _("jump hint unaligned");
+  return insn | ((value / 4) & 0x3FFF);
+}
+
+static int
+extract_jhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED)
+{
+  return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
+}
+
+/* The hint field of an EV6 HW_JMP/JSR insn.  */
+
+static unsigned
+insert_ev6hwjhint (unsigned insn, int value, const char **errmsg)
+{
+  if (errmsg != (const char **)NULL && (value & 3))
+    *errmsg = _("jump hint unaligned");
+  return insn | ((value / 4) & 0x1FFF);
+}
+
+static int
+extract_ev6hwjhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED)
+{
+  return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);
+}
 
-/* The operands table  */
+/* The operands table.   */
 
 const struct alpha_operand alpha_operands[] =
 {
@@ -84,7 +203,7 @@ const struct alpha_operand alpha_operands[] =
 #define UNUSED		0
   { 0, 0, 0, 0, 0, 0 },
 
-  /* The plain integer register fields */
+  /* The plain integer register fields.  */
 #define RA		(UNUSED + 1)
   { 5, 21, 0, AXP_OPERAND_IR, 0, 0 },
 #define RB		(RA + 1)
@@ -92,7 +211,7 @@ const struct alpha_operand alpha_operands[] =
 #define RC		(RB + 1)
   { 5, 0, 0, AXP_OPERAND_IR, 0, 0 },
 
-  /* The plain fp register fields */
+  /* The plain fp register fields.  */
 #define FA		(RC + 1)
   { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },
 #define FB		(FA + 1)
@@ -100,7 +219,7 @@ const struct alpha_operand alpha_operands[] =
 #define FC		(FB + 1)
   { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },
 
-  /* The integer registers when they are ZERO */
+  /* The integer registers when they are ZERO.  */
 #define ZA		(FC + 1)
   { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },
 #define ZB		(ZA + 1)
@@ -108,53 +227,53 @@ const struct alpha_operand alpha_operands[] =
 #define ZC		(ZB + 1)
   { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },
 
-  /* The RB field when it needs parentheses */
+  /* The RB field when it needs parentheses.  */
 #define PRB		(ZC + 1)
   { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },
 
-  /* The RB field when it needs parentheses _and_ a preceding comma */
+  /* The RB field when it needs parentheses _and_ a preceding comma.  */
 #define CPRB		(PRB + 1)
   { 5, 16, 0,
     AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },
 
-  /* The RB field when it must be the same as the RA field */
+  /* The RB field when it must be the same as the RA field.  */
 #define RBA		(CPRB + 1)
   { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },
 
-  /* The RC field when it must be the same as the RB field */
+  /* The RC field when it must be the same as the RB field.  */
 #define RCA		(RBA + 1)
   { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },
 
-  /* The RC field when it can *default* to RA */
+  /* The RC field when it can *default* to RA.  */
 #define DRC1		(RCA + 1)
   { 5, 0, 0,
     AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
 
-  /* The RC field when it can *default* to RB */
+  /* The RC field when it can *default* to RB.  */
 #define DRC2		(DRC1 + 1)
   { 5, 0, 0,
     AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
 
-  /* The FC field when it can *default* to RA */
+  /* The FC field when it can *default* to RA.  */
 #define DFC1		(DRC2 + 1)
   { 5, 0, 0,
     AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
 
-  /* The FC field when it can *default* to RB */
+  /* The FC field when it can *default* to RB.  */
 #define DFC2		(DFC1 + 1)
   { 5, 0, 0,
     AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
 
-  /* The unsigned 8-bit literal of Operate format insns */
+  /* The unsigned 8-bit literal of Operate format insns.  */
 #define LIT		(DFC2 + 1)
   { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },
 
   /* The signed 16-bit displacement of Memory format insns.  From here
-     we can't tell what relocation should be used, so don't use a default. */
+     we can't tell what relocation should be used, so don't use a default.  */
 #define MDISP		(LIT + 1)
   { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },
 
-  /* The signed "23-bit" aligned displacement of Branch format insns */
+  /* The signed "23-bit" aligned displacement of Branch format insns.  */
 #define BDISP		(MDISP + 1)
   { 21, 0, BFD_RELOC_23_PCREL_S2, 
     AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
@@ -163,23 +282,23 @@ const struct alpha_operand alpha_operands[] =
 #define PALFN		(BDISP + 1)
   { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },
 
-  /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */
+  /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint.  */
 #define JMPHINT		(PALFN + 1)
   { 14, 0, BFD_RELOC_ALPHA_HINT,
     AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
     insert_jhint, extract_jhint },
 
-  /* The optional hint to RET/JSR_COROUTINE */
+  /* The optional hint to RET/JSR_COROUTINE.  */
 #define RETHINT		(JMPHINT + 1)
   { 14, 0, -RETHINT,
     AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },
 
-  /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */
+  /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns.  */
 #define EV4HWDISP	(RETHINT + 1)
 #define EV6HWDISP	(EV4HWDISP)
   { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
 
-  /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */
+  /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns.  */
 #define EV4HWINDEX	(EV4HWDISP + 1)
   { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
 
@@ -188,20 +307,20 @@ const struct alpha_operand alpha_operands[] =
 #define EV4EXTHWINDEX	(EV4HWINDEX + 1)
   { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
 
-  /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */
+  /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns.  */
 #define EV5HWDISP	(EV4EXTHWINDEX + 1)
   { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
 
-  /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */
+  /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns.  */
 #define EV5HWINDEX	(EV5HWDISP + 1)
   { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
 
   /* The 16-bit combined index/scoreboard mask for the ev6
-     hw_m[ft]pr (pal19/pal1d) insns */
+     hw_m[ft]pr (pal19/pal1d) insns.  */
 #define EV6HWINDEX	(EV5HWINDEX + 1)
   { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
 
-  /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */
+  /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn.  */
 #define EV6HWJMPHINT	(EV6HWINDEX+ 1)
   { 8, 0, -EV6HWJMPHINT,
     AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
@@ -210,230 +329,57 @@ const struct alpha_operand alpha_operands[] =
 
 const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
 
-/* The RB field when it is the same as the RA field in the same insn.
-   This operand is marked fake.  The insertion function just copies
-   the RA field into the RB field, and the extraction function just
-   checks that the fields are the same. */
-
-static unsigned
-insert_rba(insn, value, errmsg)
-     unsigned insn;
-     int value ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
-{
-  return insn | (((insn >> 21) & 0x1f) << 16);
-}
-
-static int
-extract_rba(insn, invalid)
-     unsigned insn;
-     int *invalid;
-{
-  if (invalid != (int *) NULL
-      && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
-    *invalid = 1;
-  return 0;
-}
-
-
-/* The same for the RC field */
-
-static unsigned
-insert_rca(insn, value, errmsg)
-     unsigned insn;
-     int value ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
-{
-  return insn | ((insn >> 21) & 0x1f);
-}
-
-static int
-extract_rca(insn, invalid)
-     unsigned insn;
-     int *invalid;
-{
-  if (invalid != (int *) NULL
-      && ((insn >> 21) & 0x1f) != (insn & 0x1f))
-    *invalid = 1;
-  return 0;
-}
-
-
-/* Fake arguments in which the registers must be set to ZERO */
-
-static unsigned
-insert_za(insn, value, errmsg)
-     unsigned insn;
-     int value ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
-{
-  return insn | (31 << 21);
-}
-
-static int
-extract_za(insn, invalid)
-     unsigned insn;
-     int *invalid;
-{
-  if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
-    *invalid = 1;
-  return 0;
-}
-
-static unsigned
-insert_zb(insn, value, errmsg)
-     unsigned insn;
-     int value ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
-{
-  return insn | (31 << 16);
-}
-
-static int
-extract_zb(insn, invalid)
-     unsigned insn;
-     int *invalid;
-{
-  if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
-    *invalid = 1;
-  return 0;
-}
-
-static unsigned
-insert_zc(insn, value, errmsg)
-     unsigned insn;
-     int value ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
-{
-  return insn | 31;
-}
-
-static int
-extract_zc(insn, invalid)
-     unsigned insn;
-     int *invalid;
-{
-  if (invalid != (int *) NULL && (insn & 0x1f) != 31)
-    *invalid = 1;
-  return 0;
-}
-
-
-/* The displacement field of a Branch format insn.  */
-
-static unsigned
-insert_bdisp(insn, value, errmsg)
-     unsigned insn;
-     int value;
-     const char **errmsg;
-{
-  if (errmsg != (const char **)NULL && (value & 3))
-    *errmsg = _("branch operand unaligned");
-  return insn | ((value / 4) & 0x1FFFFF);
-}
-
-static int
-extract_bdisp(insn, invalid)
-     unsigned insn;
-     int *invalid ATTRIBUTE_UNUSED;
-{
-  return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
-}
-
-
-/* The hint field of a JMP/JSR insn.  */
-
-static unsigned
-insert_jhint(insn, value, errmsg)
-     unsigned insn;
-     int value;
-     const char **errmsg;
-{
-  if (errmsg != (const char **)NULL && (value & 3))
-    *errmsg = _("jump hint unaligned");
-  return insn | ((value / 4) & 0x3FFF);
-}
-
-static int
-extract_jhint(insn, invalid)
-     unsigned insn;
-     int *invalid ATTRIBUTE_UNUSED;
-{
-  return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
-}
-
-/* The hint field of an EV6 HW_JMP/JSR insn.  */
-
-static unsigned
-insert_ev6hwjhint(insn, value, errmsg)
-     unsigned insn;
-     int value;
-     const char **errmsg;
-{
-  if (errmsg != (const char **)NULL && (value & 3))
-    *errmsg = _("jump hint unaligned");
-  return insn | ((value / 4) & 0x1FFF);
-}
-
-static int
-extract_ev6hwjhint(insn, invalid)
-     unsigned insn;
-     int *invalid ATTRIBUTE_UNUSED;
-{
-  return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);
-}
-
 
-/* Macros used to form opcodes */
+/* Macros used to form opcodes.  */
 
-/* The main opcode */
+/* The main opcode.  */
 #define OP(x)		(((x) & 0x3F) << 26)
 #define OP_MASK		0xFC000000
 
-/* Branch format instructions */
+/* Branch format instructions.  */
 #define BRA_(oo)	OP(oo)
 #define BRA_MASK	OP_MASK
 #define BRA(oo)		BRA_(oo), BRA_MASK
 
-/* Floating point format instructions */
+/* Floating point format instructions.  */
 #define FP_(oo,fff)	(OP(oo) | (((fff) & 0x7FF) << 5))
 #define FP_MASK		(OP_MASK | 0xFFE0)
 #define FP(oo,fff)	FP_(oo,fff), FP_MASK
 
-/* Memory format instructions */
+/* Memory format instructions.  */
 #define MEM_(oo)	OP(oo)
 #define MEM_MASK	OP_MASK
 #define MEM(oo)		MEM_(oo), MEM_MASK
 
-/* Memory/Func Code format instructions */
+/* Memory/Func Code format instructions.  */
 #define MFC_(oo,ffff)	(OP(oo) | ((ffff) & 0xFFFF))
 #define MFC_MASK	(OP_MASK | 0xFFFF)
 #define MFC(oo,ffff)	MFC_(oo,ffff), MFC_MASK
 
-/* Memory/Branch format instructions */
+/* Memory/Branch format instructions.  */
 #define MBR_(oo,h)	(OP(oo) | (((h) & 3) << 14))
 #define MBR_MASK	(OP_MASK | 0xC000)
 #define MBR(oo,h)	MBR_(oo,h), MBR_MASK
 
 /* Operate format instructions.  The OPRL variant specifies a
-   literal second argument. */
+   literal second argument.  */
 #define OPR_(oo,ff)	(OP(oo) | (((ff) & 0x7F) << 5))
 #define OPRL_(oo,ff)	(OPR_((oo),(ff)) | 0x1000)
 #define OPR_MASK	(OP_MASK | 0x1FE0)
 #define OPR(oo,ff)	OPR_(oo,ff), OPR_MASK
 #define OPRL(oo,ff)	OPRL_(oo,ff), OPR_MASK
 
-/* Generic PALcode format instructions */
+/* Generic PALcode format instructions.  */
 #define PCD_(oo)	OP(oo)
 #define PCD_MASK	OP_MASK
 #define PCD(oo)		PCD_(oo), PCD_MASK
 
-/* Specific PALcode instructions */
+/* Specific PALcode instructions.  */
 #define SPCD_(oo,ffff)	(OP(oo) | ((ffff) & 0x3FFFFFF))
 #define SPCD_MASK	0xFFFFFFFF
 #define SPCD(oo,ffff)	SPCD_(oo,ffff), SPCD_MASK
 
-/* Hardware memory (hw_{ld,st}) instructions */
+/* Hardware memory (hw_{ld,st}) instructions.  */
 #define EV4HWMEM_(oo,f)	(OP(oo) | (((f) & 0xF) << 12))
 #define EV4HWMEM_MASK	(OP_MASK | 0xF000)
 #define EV4HWMEM(oo,f)	EV4HWMEM_(oo,f), EV4HWMEM_MASK
@@ -459,7 +405,7 @@ extract_ev6hwjhint(insn, invalid)
 #define CIX			AXP_OPCODE_CIX
 #define MAX			AXP_OPCODE_MAX
 
-/* Common combinations of arguments */
+/* Common combinations of arguments.  */
 #define ARG_NONE		{ 0 }
 #define ARG_BRA			{ RA, BDISP }
 #define ARG_FBRA		{ FA, BDISP }
@@ -519,10 +465,10 @@ extract_ev6hwjhint(insn, invalid)
 
    EV56 UNA	opcodes that were introduced as of the ev56 with
    		presumably undefined results on previous implementations
-		that were not assigned to a particular extension.
-*/
+		that were not assigned to a particular extension.  */
 
-const struct alpha_opcode alpha_opcodes[] = {
+const struct alpha_opcode alpha_opcodes[] =
+{
   { "halt",		SPCD(0x00,0x0000), BASE, ARG_NONE },
   { "draina",		SPCD(0x00,0x0002), BASE, ARG_NONE },
   { "bpt",		SPCD(0x00,0x0080), BASE, ARG_NONE },
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index f614cc3..fe835ae 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -1,5 +1,5 @@
 /* Instruction printing code for the ARC.
-   Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002
+   Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005
    Free Software Foundation, Inc.
    Contributed by Doug Evans (dje@cygnus.com).
 
@@ -15,7 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include "ansidecl.h"
 #include "libiberty.h"
@@ -34,11 +35,11 @@
 #define dbg (0)
 #endif
 
-
 /* Classification of the opcodes for the decoder to print 
    the instructions.  */
 
-typedef enum { 
+typedef enum
+{
   CLASS_A4_ARITH,	     
   CLASS_A4_OP3_GENERAL,
   CLASS_A4_FLAG,
@@ -56,7 +57,6 @@ typedef enum {
   CLASS_A4_LR
 } a4_decoding_class;
 
-
 #define BIT(word,n)	((word) & (1 << n))
 #define BITS(word,s,e)  (((word) << (31 - e)) >> (s + (31 - e)))
 #define OPCODE(word)	(BITS ((word), 27, 31))
@@ -64,7 +64,6 @@ typedef enum {
 #define FIELDB(word)	(BITS ((word), 15, 20))
 #define FIELDC(word)	(BITS ((word),  9, 14))
 
-
 /* FIELD D is signed in all of its uses, so we make sure argument is
    treated as signed for bit shifting purposes:  */
 #define FIELDD(word)	(BITS (((signed int)word), 0, 8))
@@ -146,15 +145,15 @@ typedef enum {
     }						\
   while (0)
 
-#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
-#define IS_REG(x)   (field##x##isReg)
-#define WRITE_FORMAT_LB_Rx_RB(x)     WRITE_FORMAT(x,"[","]","","")
-#define WRITE_FORMAT_x_COMMA_LB(x)   WRITE_FORMAT(x,"",",[","",",[")
-#define WRITE_FORMAT_COMMA_x_RB(x)   WRITE_FORMAT(x,",","]",",","]")
-#define WRITE_FORMAT_x_RB(x)         WRITE_FORMAT(x,"","]","","]")
-#define WRITE_FORMAT_COMMA_x(x)      WRITE_FORMAT(x,",","",",","")
-#define WRITE_FORMAT_x_COMMA(x)      WRITE_FORMAT(x,"",",","",",")
-#define WRITE_FORMAT_x(x)            WRITE_FORMAT(x,"","","","")
+#define IS_SMALL(x)                 (((field##x) < 256) && ((field##x) > -257))
+#define IS_REG(x)                    (field##x##isReg)
+#define WRITE_FORMAT_LB_Rx_RB(x)     WRITE_FORMAT (x, "[","]","","")
+#define WRITE_FORMAT_x_COMMA_LB(x)   WRITE_FORMAT (x, "",",[","",",[")
+#define WRITE_FORMAT_COMMA_x_RB(x)   WRITE_FORMAT (x, ",","]",",","]")
+#define WRITE_FORMAT_x_RB(x)         WRITE_FORMAT (x, "","]","","]")
+#define WRITE_FORMAT_COMMA_x(x)      WRITE_FORMAT (x, ",","",",","")
+#define WRITE_FORMAT_x_COMMA(x)      WRITE_FORMAT (x, "",",","",",")
+#define WRITE_FORMAT_x(x)            WRITE_FORMAT (x, "","","","")
 #define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString,		\
 				     (IS_REG (x) ? cb1"%r"ca1 :		\
 				      usesAuxReg ? cb"%a"ca :		\
@@ -169,25 +168,8 @@ typedef enum {
 
 static char comment_prefix[] = "\t; ";
 
-static const char *core_reg_name PARAMS ((struct arcDisState *, int));
-static const char *aux_reg_name PARAMS ((struct arcDisState *, int));
-static const char *cond_code_name PARAMS ((struct arcDisState *, int));
-static const char *instruction_name
-  PARAMS ((struct arcDisState *, int, int, int *));
-static void mwerror PARAMS ((struct arcDisState *, const char *));
-static const char *post_address PARAMS ((struct arcDisState *, int));
-static void write_comments_
-  PARAMS ((struct arcDisState *, int, int, long int));
-static void write_instr_name_
-  PARAMS ((struct arcDisState *, const char *, int, int, int, int, int, int));
-static int dsmOneArcInst PARAMS ((bfd_vma, struct arcDisState *));
-static const char *_coreRegName PARAMS ((void *, int));
-static int decodeInstr PARAMS ((bfd_vma, disassemble_info *));
-
 static const char *
-core_reg_name (state, val)
-     struct arcDisState * state;
-     int                  val;
+core_reg_name (struct arcDisState * state, int val)
 {
   if (state->coreRegName)
     return (*state->coreRegName)(state->_this, val);
@@ -195,9 +177,7 @@ core_reg_name (state, val)
 }
 
 static const char *
-aux_reg_name (state, val)
-     struct arcDisState * state;
-     int                  val;
+aux_reg_name (struct arcDisState * state, int val)
 {
   if (state->auxRegName)
     return (*state->auxRegName)(state->_this, val);
@@ -205,9 +185,7 @@ aux_reg_name (state, val)
 }
 
 static const char *
-cond_code_name (state, val)
-     struct arcDisState * state;
-     int                  val;
+cond_code_name (struct arcDisState * state, int val)
 {
   if (state->condCodeName)
     return (*state->condCodeName)(state->_this, val);
@@ -215,11 +193,10 @@ cond_code_name (state, val)
 }
 
 static const char *
-instruction_name (state, op1, op2, flags)
-     struct arcDisState * state;
-     int    op1;
-     int    op2;
-     int *  flags;
+instruction_name (struct arcDisState * state,
+		  int    op1,
+		  int    op2,
+		  int *  flags)
 {
   if (state->instName)
     return (*state->instName)(state->_this, op1, op2, flags);
@@ -227,18 +204,14 @@ instruction_name (state, op1, op2, flags)
 }
 
 static void
-mwerror (state, msg)
-     struct arcDisState * state;
-     const char * msg;
+mwerror (struct arcDisState * state, const char * msg)
 {
   if (state->err != 0)
     (*state->err)(state->_this, (msg));
 }
 
 static const char *
-post_address (state, addr)
-     struct arcDisState * state;
-     int addr;
+post_address (struct arcDisState * state, int addr)
 {
   static char id[3 * ARRAY_SIZE (state->addresses)];
   int j, i = state->acnt;
@@ -257,22 +230,16 @@ post_address (state, addr)
   return "";
 }
 
-static void my_sprintf PARAMS ((struct arcDisState *, char *, const char *,
-				...));
-
 static void
-my_sprintf VPARAMS ((struct arcDisState *state, char *buf, const char *format,
-		     ...))
+arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...)
 {
   char *bp;
   const char *p;
   int size, leading_zero, regMap[2];
   long auxNum;
+  va_list ap;
 
-  VA_OPEN (ap, format);
-  VA_FIXEDARG (ap, struct arcDisState *, state);
-  VA_FIXEDARG (ap, char *, buf);
-  VA_FIXEDARG (ap, const char *, format);
+  va_start (ap, format);
 
   bp = buf;
   *bp = 0;
@@ -413,7 +380,7 @@ my_sprintf VPARAMS ((struct arcDisState *state, char *buf, const char *format,
 		    if (ext)
 		      sprintf (bp, "%s", ext);
 		    else
-		      my_sprintf (state, bp, "%h", val);
+		      arc_sprintf (state, bp, "%h", val);
 		  }
 		  break;
 		}
@@ -435,15 +402,14 @@ my_sprintf VPARAMS ((struct arcDisState *state, char *buf, const char *format,
       }
 
  DOCOMM: *bp = 0;
-  VA_CLOSE (ap);
+  va_end (ap);
 }
 
 static void
-write_comments_(state, shimm, is_limm, limm_value)
-     struct arcDisState * state;
-     int shimm;
-     int is_limm;
-     long limm_value;
+write_comments_(struct arcDisState * state,
+		int shimm,
+		int is_limm,
+		long limm_value)
 {
   if (state->commentBuffer != 0)
     {
@@ -468,25 +434,25 @@ write_comments_(state, shimm, is_limm, limm_value)
     }
 }
 
-#define write_comments2(x) write_comments_(state, x, is_limm, limm_value)
-#define write_comments() write_comments2(0)
+#define write_comments2(x) write_comments_ (state, x, is_limm, limm_value)
+#define write_comments()   write_comments2 (0)
 
-static const char *condName[] = {
+static const char *condName[] =
+{
   /* 0..15.  */
   ""   , "z"  , "nz" , "p"  , "n"  , "c"  , "nc" , "v"  ,
   "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
 };
 
 static void
-write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem)
-     struct arcDisState * state;
-     const char * instrName;
-     int cond;
-     int condCodeIsPartOfName;
-     int flag;
-     int signExtend;
-     int addrWriteBack;
-     int directMem;
+write_instr_name_(struct arcDisState * state,
+		  const char * instrName,
+		  int cond,
+		  int condCodeIsPartOfName,
+		  int flag,
+		  int signExtend,
+		  int addrWriteBack,
+		  int directMem)
 {
   strcpy (state->instrBuffer, instrName);
 
@@ -540,7 +506,8 @@ write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend
     }									\
   while (0)
 
-enum {
+enum
+{
   op_LD0 = 0, op_LD1 = 1, op_ST  = 2, op_3   = 3,
   op_BC  = 4, op_BLC = 5, op_LPC = 6, op_JC  = 7,
   op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11,
@@ -550,9 +517,7 @@ enum {
 extern disassemble_info tm_print_insn_info;
 
 static int
-dsmOneArcInst (addr, state)
-     bfd_vma              addr;
-     struct arcDisState * state;
+dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
 {
   int condCodeIsPartOfName = 0;
   a4_decoding_class decodingClass;
@@ -641,7 +606,7 @@ dsmOneArcInst (addr, state)
 	}
       else
 	{
-	  switch (BITS (state->words[0],10,11))
+	  switch (BITS (state->words[0], 10, 11))
 	    {
 	    case 0:
 	      instrName = "ld";
@@ -665,14 +630,14 @@ dsmOneArcInst (addr, state)
       break;
 
     case op_ST:
-      if (BIT (state->words[0],25))
+      if (BIT (state->words[0], 25))
 	{
 	  instrName = "sr";
 	  decodingClass = CLASS_A4_SR;
 	}
       else
 	{
-	  switch (BITS (state->words[0],22,23))
+	  switch (BITS (state->words[0], 22, 23))
 	    {
 	    case 0:
 	      instrName = "st";
@@ -727,7 +692,7 @@ dsmOneArcInst (addr, state)
 	case  0x3f:
 	  {
 	    decodingClass = CLASS_A4_OP3_SUBOPC3F;
-	    switch( FIELDD (state->words[0]) )
+	    switch (FIELDD (state->words[0]))
 	      {
 	      case 0:
 		instrName = "brk";
@@ -822,7 +787,7 @@ dsmOneArcInst (addr, state)
     case op_XOR:
       if (state->words[0] == 0x7fffffff)
 	{
-	  /* nop encoded as xor -1, -1, -1  */
+	  /* NOP encoded as xor -1, -1, -1.   */
 	  instrName = "nop";
 	  decodingClass = CLASS_A4_OP3_SUBOPC3F;
 	}
@@ -866,7 +831,7 @@ dsmOneArcInst (addr, state)
 	  if (!repeatsOp)
 	    WRITE_FORMAT_COMMA_x (C);
 	  WRITE_NOP_COMMENT ();
-	  my_sprintf (state, state->operandBuffer, formatString,
+	  arc_sprintf (state, state->operandBuffer, formatString,
 		      fieldA, fieldB, fieldC);
 	}
       else
@@ -874,7 +839,7 @@ dsmOneArcInst (addr, state)
 	  WRITE_FORMAT_x (B);
 	  if (!repeatsOp)
 	    WRITE_FORMAT_COMMA_x (C);
-	  my_sprintf (state, state->operandBuffer, formatString,
+	  arc_sprintf (state, state->operandBuffer, formatString,
 		      fieldB, fieldC);
 	}
       write_comments ();
@@ -891,13 +856,13 @@ dsmOneArcInst (addr, state)
 	  WRITE_FORMAT_x (A);
 	  WRITE_FORMAT_COMMA_x (B);
 	  WRITE_NOP_COMMENT ();
-	  my_sprintf (state, state->operandBuffer, formatString,
+	  arc_sprintf (state, state->operandBuffer, formatString,
 		      fieldA, fieldB);
 	}
       else
 	{
 	  WRITE_FORMAT_x (B);
-	  my_sprintf (state, state->operandBuffer, formatString, fieldB);
+	  arc_sprintf (state, state->operandBuffer, formatString, fieldB);
 	}
       write_comments ();
       break;
@@ -905,17 +870,17 @@ dsmOneArcInst (addr, state)
     case CLASS_A4_FLAG:
       CHECK_FIELD_B ();
       CHECK_FLAG_COND_NULLIFY ();
-      flag = 0; /* this is the FLAG instruction -- it's redundant  */
+      flag = 0; /* This is the FLAG instruction -- it's redundant.  */
 
       write_instr_name ();
       WRITE_FORMAT_x (B);
-      my_sprintf (state, state->operandBuffer, formatString, fieldB);
+      arc_sprintf (state, state->operandBuffer, formatString, fieldB);
       write_comments ();
       break;
 
     case CLASS_A4_BRANCH:
       fieldA = BITS (state->words[0],7,26) << 2;
-      fieldA = (fieldA << 10) >> 10; /* make it signed  */
+      fieldA = (fieldA << 10) >> 10; /* Make it signed.  */
       fieldA += addr + 4;
       CHECK_FLAG_COND_NULLIFY ();
       flag = 0;
@@ -932,8 +897,8 @@ dsmOneArcInst (addr, state)
 	     lr dest<- func addr; j [dest]"  */
 	}
 
-      strcat (formatString, "%s"); /* address/label name */
-      my_sprintf (state, state->operandBuffer, formatString,
+      strcat (formatString, "%s"); /* Address/label name.  */
+      arc_sprintf (state, state->operandBuffer, formatString,
 		  post_address (state, fieldA));
       write_comments ();
       break;
@@ -949,12 +914,12 @@ dsmOneArcInst (addr, state)
       if (!fieldBisReg)
 	{
 	  fieldAisReg = 0;
-	  fieldA = (fieldB >> 25) & 0x7F; /* flags */
+	  fieldA = (fieldB >> 25) & 0x7F; /* Flags.  */
 	  fieldB = (fieldB & 0xFFFFFF) << 2;
 	  state->flow = is_linked ? direct_call : direct_jump;
 	  add_target (fieldB);
-	  /* screwy JLcc requires .jd mode to execute correctly
-	   * but we pretend it is .nd (no delay slot).  */
+	  /* Screwy JLcc requires .jd mode to execute correctly
+	     but we pretend it is .nd (no delay slot).  */
 	  if (is_linked && state->nullifyMode == BR_exec_when_jump)
 	    state->nullifyMode = BR_exec_when_no_jump;
 	}
@@ -962,24 +927,24 @@ dsmOneArcInst (addr, state)
 	{
 	  state->flow = is_linked ? indirect_call : indirect_jump;
 	  /* We should also treat this as indirect call if NOT linked
-	   * but the preceding instruction was a "lr blink,[status]"
-	   * and we have a delay slot with "add blink,blink,2".
-	   * For now we can't detect such.  */
+	     but the preceding instruction was a "lr blink,[status]"
+	     and we have a delay slot with "add blink,blink,2".
+	     For now we can't detect such.  */
 	  state->register_for_indirect_jump = fieldB;
 	}
 
       write_instr_name ();
       strcat (formatString,
-	      IS_REG (B) ? "[%r]" : "%s"); /* address/label name  */
+	      IS_REG (B) ? "[%r]" : "%s"); /* Address/label name.  */
       if (fieldA != 0)
 	{
 	  fieldAisReg = 0;
 	  WRITE_FORMAT_COMMA_x (A);
 	}
       if (IS_REG (B))
-	my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
+	arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
       else
-	my_sprintf (state, state->operandBuffer, formatString,
+	arc_sprintf (state, state->operandBuffer, formatString,
 		    post_address (state, fieldB), fieldA);
       write_comments ();
       break;
@@ -1005,9 +970,9 @@ dsmOneArcInst (addr, state)
 	state->_offset += fieldC;
       state->_mem_load = 1;
 
-      directMem     = BIT (state->words[0],5);
-      addrWriteBack = BIT (state->words[0],3);
-      signExtend    = BIT (state->words[0],0);
+      directMem     = BIT (state->words[0], 5);
+      addrWriteBack = BIT (state->words[0], 3);
+      signExtend    = BIT (state->words[0], 0);
 
       write_instr_name ();
       WRITE_FORMAT_x_COMMA_LB(A);
@@ -1017,7 +982,7 @@ dsmOneArcInst (addr, state)
 	fieldB = fieldC;
 
       WRITE_FORMAT_x_RB (C);
-      my_sprintf (state, state->operandBuffer, formatString,
+      arc_sprintf (state, state->operandBuffer, formatString,
 		  fieldA, fieldB, fieldC);
       write_comments ();
       break;
@@ -1036,7 +1001,7 @@ dsmOneArcInst (addr, state)
       state->_mem_load = 1;
       if (fieldBisReg)
 	state->ea_reg1 = fieldB;
-      /* field B is either a shimm (same as fieldC) or limm (different!)
+      /* Field B is either a shimm (same as fieldC) or limm (different!)
 	 Say ea is not present, so only one of us will do the name lookup.  */
       else
 	state->_offset += fieldB, state->_ea_present = 0;
@@ -1063,7 +1028,7 @@ dsmOneArcInst (addr, state)
 	  else
 	    WRITE_FORMAT_RB ();
 	}
-      my_sprintf (state, state->operandBuffer, formatString,
+      arc_sprintf (state, state->operandBuffer, formatString,
 		  fieldA, fieldB, fieldC);
       write_comments ();
       break;
@@ -1081,26 +1046,26 @@ dsmOneArcInst (addr, state)
       state->_offset = fieldA;
       if (fieldBisReg)
 	state->ea_reg1 = fieldB;
-      /* field B is either a shimm (same as fieldA) or limm (different!)
+      /* Field B is either a shimm (same as fieldA) or limm (different!)
 	 Say ea is not present, so only one of us will do the name lookup.
 	 (for is_limm we do the name translation here).  */
       else
 	state->_offset += fieldB, state->_ea_present = 0;
 
-      directMem     = BIT(state->words[0],26);
-      addrWriteBack = BIT(state->words[0],24);
+      directMem     = BIT (state->words[0], 26);
+      addrWriteBack = BIT (state->words[0], 24);
 
-      write_instr_name();
+      write_instr_name ();
       WRITE_FORMAT_x_COMMA_LB(C);
 
       if (!fieldBisReg)
 	{
 	  fieldB = state->_offset;
-	  WRITE_FORMAT_x_RB(B);
+	  WRITE_FORMAT_x_RB (B);
 	}
       else
 	{
-	  WRITE_FORMAT_x(B);
+	  WRITE_FORMAT_x (B);
 	  if (fieldBisReg && fieldA != 0)
 	    {
 	      fieldAisReg = 0;
@@ -1109,9 +1074,9 @@ dsmOneArcInst (addr, state)
 	  else
 	    WRITE_FORMAT_RB();
 	}
-      my_sprintf (state, state->operandBuffer, formatString,
+      arc_sprintf (state, state->operandBuffer, formatString,
 		  fieldC, fieldB, fieldA);
-      write_comments2(fieldA);
+      write_comments2 (fieldA);
       break;
 
     case CLASS_A4_SR:
@@ -1119,37 +1084,36 @@ dsmOneArcInst (addr, state)
       CHECK_FIELD_B();
       CHECK_FIELD_C();
 
-      write_instr_name();
+      write_instr_name ();
       WRITE_FORMAT_x_COMMA_LB(C);
       /* Try to print B as an aux reg if it is not a core reg.  */
       usesAuxReg = 1;
-      WRITE_FORMAT_x(B);
-      WRITE_FORMAT_RB();
-      my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
-      write_comments();
+      WRITE_FORMAT_x (B);
+      WRITE_FORMAT_RB ();
+      arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
+      write_comments ();
       break;
 
     case CLASS_A4_OP3_SUBOPC3F:
-      write_instr_name();
+      write_instr_name ();
       state->operandBuffer[0] = '\0';
       break;
 
     case CLASS_A4_LR:
       /* LR instruction */
-      CHECK_FIELD_A();
-      CHECK_FIELD_B();
+      CHECK_FIELD_A ();
+      CHECK_FIELD_B ();
 
-      write_instr_name();
-      WRITE_FORMAT_x_COMMA_LB(A);
+      write_instr_name ();
+      WRITE_FORMAT_x_COMMA_LB (A);
       /* Try to print B as an aux reg if it is not a core reg. */
       usesAuxReg = 1;
-      WRITE_FORMAT_x(B);
-      WRITE_FORMAT_RB();
-      my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
-      write_comments();
+      WRITE_FORMAT_x (B);
+      WRITE_FORMAT_RB ();
+      arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
+      write_comments ();
       break;
 
-
     default:
       mwerror (state, "Bad decoding class in ARC disassembler");
       break;
@@ -1161,23 +1125,23 @@ dsmOneArcInst (addr, state)
 
 
 /* Returns the name the user specified core extension register.  */
+
 static const char *
-_coreRegName(arg, regval)
-     void * arg ATTRIBUTE_UNUSED;
-     int regval;
+_coreRegName(void * arg ATTRIBUTE_UNUSED, int regval)
 {
   return arcExtMap_coreRegName (regval);
 }
 
 /* Returns the name the user specified AUX extension register.  */
+
 static const char *
 _auxRegName(void *_this ATTRIBUTE_UNUSED, int regval)
 {
   return arcExtMap_auxRegName(regval);
 }
 
-
 /* Returns the name the user specified condition code name.  */
+
 static const char *
 _condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
 {
@@ -1185,6 +1149,7 @@ _condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
 }
 
 /* Returns the name the user specified extension instruction.  */
+
 static const char *
 _instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
 {
@@ -1193,15 +1158,15 @@ _instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
 
 /* Decode an instruction returning the size of the instruction
    in bytes or zero if unrecognized.  */
+
 static int
-decodeInstr (address, info)
-     bfd_vma            address; /* Address of this instruction.  */
-     disassemble_info * info;
+decodeInstr (bfd_vma            address, /* Address of this instruction.  */
+	     disassemble_info * info)
 {
   int status;
   bfd_byte buffer[4];
-  struct arcDisState s;	/* ARC Disassembler state  */
-  void *stream = info->stream; /* output stream  */
+  struct arcDisState s;		/* ARC Disassembler state.  */
+  void *stream = info->stream; 	/* Output stream.  */
   fprintf_ftype func = info->fprintf_func;
   int bytes;
 
@@ -1218,9 +1183,9 @@ decodeInstr (address, info)
     s.words[0] = bfd_getl32(buffer);
   else
     s.words[0] = bfd_getb32(buffer);
-  /* always read second word in case of limm  */
+  /* Always read second word in case of limm.  */
 
-  /* we ignore the result since last insn may not have a limm  */
+  /* We ignore the result since last insn may not have a limm.  */
   status = (*info->read_memory_func) (address + 4, buffer, 4, info);
   if (info->endian == BFD_ENDIAN_LITTLE)
     s.words[1] = bfd_getl32(buffer);
@@ -1233,23 +1198,24 @@ decodeInstr (address, info)
   s.condCodeName = _condCodeName;
   s.instName = _instName;
 
-  /* disassemble  */
-  bytes = dsmOneArcInst(address, (void *)&s);
+  /* Disassemble.  */
+  bytes = dsmOneArcInst (address, (void *)& s);
 
-  /* display the disassembly instruction  */
+  /* Display the disassembly instruction.  */
   (*func) (stream, "%08x ", s.words[0]);
   (*func) (stream, "    ");
-
   (*func) (stream, "%-10s ", s.instrBuffer);
 
-  if (__TRANSLATION_REQUIRED(s))
+  if (__TRANSLATION_REQUIRED (s))
     {
       bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
+
       (*info->print_address_func) ((bfd_vma) addr, info);
       (*func) (stream, "\n");
     }
   else
     (*func) (stream, "%s",s.operandBuffer);
+
   return s.instructionLen;
 }
 
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 465200f..7de071f 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1,5 +1,5 @@
 /* Opcode table for the ARC.
-   Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2004
+   Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2004, 2005
    Free Software Foundation, Inc.
    Contributed by Doug Evans (dje@cygnus.com).
 
@@ -22,14 +22,70 @@
 #include "ansidecl.h"
 #include "bfd.h"
 #include "opcode/arc.h"
+#include "opintl.h"
 
+enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM};
+
+#define OPERANDS 3
+
+enum operand ls_operand[OPERANDS];
+
+struct arc_opcode *arc_ext_opcodes;
+struct arc_ext_operand_value *arc_ext_operands;
+
+#define LS_VALUE  0
+#define LS_DEST   0
+#define LS_BASE   1
+#define LS_OFFSET 2
+
+/* Given a format letter, yields the index into `arc_operands'.
+   eg: arc_operand_map['a'] = REGA.  */
+unsigned char arc_operand_map[256];
+
+/* Nonzero if we've seen an 'f' suffix (in certain insns).  */
+static int flag_p;
+
+/* Nonzero if we've finished processing the 'f' suffix.  */
+static int flagshimm_handled_p;
+
+/* Nonzero if we've seen a 'a' suffix (address writeback).  */
+static int addrwb_p;
+
+/* Nonzero if we've seen a 'q' suffix (condition code).  */
+static int cond_p;
+
+/* Nonzero if we've inserted a nullify condition.  */
+static int nullify_p;
+
+/* The value of the a nullify condition we inserted.  */
+static int nullify;
+
+/* Nonzero if we've inserted jumpflags.  */
+static int jumpflags_p;
+
+/* Nonzero if we've inserted a shimm.  */
+static int shimm_p;
+
+/* The value of the shimm we inserted (each insn only gets one but it can
+   appear multiple times).  */
+static int shimm;
+
+/* Nonzero if we've inserted a limm (during assembly) or seen a limm
+   (during disassembly).  */
+static int limm_p;
+
+/* The value of the limm we inserted.  Each insn only gets one but it can
+   appear multiple times.  */
+static long limm;
+
 #define INSERT_FN(fn) \
-static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \
-			    int, const struct arc_operand_value *, long, \
-			    const char **))
+static arc_insn fn (arc_insn, const struct arc_operand *, \
+		    int, const struct arc_operand_value *, long, \
+		    const char **)
+
 #define EXTRACT_FN(fn) \
-static long fn PARAMS ((arc_insn *, const struct arc_operand *, \
-			int, const struct arc_operand_value **, int *))
+static long fn (arc_insn *, const struct arc_operand *, \
+		int, const struct arc_operand_value **, int *)
 
 INSERT_FN (insert_reg);
 INSERT_FN (insert_shimmfinish);
@@ -60,20 +116,6 @@ EXTRACT_FN (extract_reladdr);
 EXTRACT_FN (extract_jumpflags);
 EXTRACT_FN (extract_unopmacro);
 
-enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM};
-
-#define OPERANDS 3
-
-enum operand ls_operand[OPERANDS];
-
-struct arc_opcode *arc_ext_opcodes;
-struct arc_ext_operand_value *arc_ext_operands;
-
-#define LS_VALUE  0
-#define LS_DEST   0
-#define LS_BASE   1
-#define LS_OFFSET 2
-
 /* Various types of ARC operands, including insn suffixes.  */
 
 /* Insn format values:
@@ -124,39 +166,39 @@ struct arc_ext_operand_value *arc_ext_operands;
 
 const struct arc_operand arc_operands[] =
 {
-/* place holder (??? not sure if needed).  */
+/* Place holder (??? not sure if needed).  */
 #define UNUSED 0
   { 0, 0, 0, 0, 0, 0 },
 
-/* register A or shimm/limm indicator.  */
+/* Register A or shimm/limm indicator.  */
 #define REGA (UNUSED + 1)
   { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
 
-/* register B or shimm/limm indicator.  */
+/* Register B or shimm/limm indicator.  */
 #define REGB (REGA + 1)
   { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
 
-/* register C or shimm/limm indicator.  */
+/* Register C or shimm/limm indicator.  */
 #define REGC (REGB + 1)
   { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
 
-/* fake operand used to insert shimm value into most instructions.  */
+/* Fake operand used to insert shimm value into most instructions.  */
 #define SHIMMFINISH (REGC + 1)
   { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 },
 
-/* fake operand used to insert limm value into most instructions.  */
+/* Fake operand used to insert limm value into most instructions.  */
 #define LIMMFINISH (SHIMMFINISH + 1)
   { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 },
 
-/* shimm operand when there is no reg indicator (st).  */
+/* Shimm operand when there is no reg indicator (st).  */
 #define ST_OFFSET (LIMMFINISH + 1)
   { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset },
 
-/* shimm operand when there is no reg indicator (ld).  */
+/* Shimm operand when there is no reg indicator (ld).  */
 #define LD_OFFSET (ST_OFFSET + 1)
   { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset },
 
-/* operand for base.  */
+/* Operand for base.  */
 #define BASE (LD_OFFSET + 1)
   { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg},
 
@@ -176,88 +218,88 @@ const struct arc_operand arc_operands[] =
 #define SYNTAX_LD (SYNTAX_ST + 1)
   { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax },
 
-/* flag update bit (insertion is defered until we know how).  */
+/* Flag update bit (insertion is defered until we know how).  */
 #define FLAG (SYNTAX_LD + 1)
   { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag },
 
-/* fake utility operand to finish 'f' suffix handling.  */
+/* Fake utility operand to finish 'f' suffix handling.  */
 #define FLAGFINISH (FLAG + 1)
   { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 },
 
-/* fake utility operand to set the 'f' flag for the "flag" insn.  */
+/* Fake utility operand to set the 'f' flag for the "flag" insn.  */
 #define FLAGINSN (FLAGFINISH + 1)
   { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 },
 
-/* branch delay types.  */
+/* Branch delay types.  */
 #define DELAY (FLAGINSN + 1)
   { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 },
 
-/* conditions.  */
+/* Conditions.  */
 #define COND (DELAY + 1)
   { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond },
 
-/* set `cond_p' to 1 to ensure a constant is treated as a limm.  */
+/* Set `cond_p' to 1 to ensure a constant is treated as a limm.  */
 #define FORCELIMM (COND + 1)
   { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 },
 
-/* branch address; b, bl, and lp insns.  */
+/* Branch address; b, bl, and lp insns.  */
 #define BRANCH (FORCELIMM + 1)
   { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr },
 
-/* jump address; j insn (this is basically the same as 'L' except that the
+/* Jump address; j insn (this is basically the same as 'L' except that the
    value is right shifted by 2).  */
 #define JUMP (BRANCH + 1)
   { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 },
 
-/* jump flags; j{,l} insn value or'ed into 'J' addr for flag values.  */
+/* Jump flags; j{,l} insn value or'ed into 'J' addr for flag values.  */
 #define JUMPFLAGS (JUMP + 1)
   { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags },
 
-/* size field, stored in bit 1,2.  */
+/* Size field, stored in bit 1,2.  */
 #define SIZE1 (JUMPFLAGS + 1)
   { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* size field, stored in bit 10,11.  */
+/* Size field, stored in bit 10,11.  */
 #define SIZE10 (SIZE1 + 1)
   { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* size field, stored in bit 22,23.  */
+/* Size field, stored in bit 22,23.  */
 #define SIZE22 (SIZE10 + 1)
   { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* sign extend field, stored in bit 0.  */
+/* Sign extend field, stored in bit 0.  */
 #define SIGN0 (SIZE22 + 1)
   { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* sign extend field, stored in bit 9.  */
+/* Sign extend field, stored in bit 9.  */
 #define SIGN9 (SIGN0 + 1)
   { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* address write back, stored in bit 3.  */
+/* Address write back, stored in bit 3.  */
 #define ADDRESS3 (SIGN9 + 1)
   { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
 
-/* address write back, stored in bit 12.  */
+/* Address write back, stored in bit 12.  */
 #define ADDRESS12 (ADDRESS3 + 1)
   { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
 
-/* address write back, stored in bit 24.  */
+/* Address write back, stored in bit 24.  */
 #define ADDRESS24 (ADDRESS12 + 1)
   { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
 
-/* cache bypass, stored in bit 5.  */
+/* Cache bypass, stored in bit 5.  */
 #define CACHEBYPASS5 (ADDRESS24 + 1)
   { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* cache bypass, stored in bit 14.  */
+/* Cache bypass, stored in bit 14.  */
 #define CACHEBYPASS14 (CACHEBYPASS5 + 1)
   { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* cache bypass, stored in bit 26.  */
+/* Cache bypass, stored in bit 26.  */
 #define CACHEBYPASS26 (CACHEBYPASS14 + 1)
   { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* unop macro, used to copy REGB to REGC.  */
+/* Unop macro, used to copy REGB to REGC.  */
 #define UNOPMACRO (CACHEBYPASS26 + 1)
   { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro },
 
@@ -275,410 +317,22 @@ const struct arc_operand arc_operands[] =
 #define AUXREG (REG + 1)
   { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 },
 
-/* end of list place holder.  */
+/* End of list place holder.  */
   { 0, 0, 0, 0, 0, 0 }
 };
 
-/* Given a format letter, yields the index into `arc_operands'.
-   eg: arc_operand_map['a'] = REGA.  */
-unsigned char arc_operand_map[256];
-
-/* ARC instructions.
-
-   Longer versions of insns must appear before shorter ones (if gas sees
-   "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is
-   junk).  This isn't necessary for `ld' because of the trailing ']'.
-
-   Instructions that are really macros based on other insns must appear
-   before the real insn so they're chosen when disassembling.  Eg: The `mov'
-   insn is really the `and' insn.  */
-
-struct arc_opcode arc_opcodes[] =
-{
-  /* Base case instruction set (core versions 5-8)  */
-
-  /* "mov" is really an "and".  */
-  { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 },
-  /* "asl" is really an "add".  */
-  { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
-  /* "lsl" is really an "add".  */
-  { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
-  /* "nop" is really an "xor".  */
-  { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 },
-  /* "rlc" is really an "adc".  */
-  { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 },
-  { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 },
-  { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 },
-  { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 },
-  { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 },
-  { "bic%.q%.f %a,%b,%c%F%S%L",	I(-1), I(14), ARC_MACH_5, 0, 0 },
-  { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
-  { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
-  { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 },
-  { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 },
-  { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 },
-  { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 },
-  { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 },
-  { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 },
-  /* %Q: force cond_p=1 -> no shimm values. This insn allows an
-     optional flags spec.  */
-  { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
-  { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
-  /* This insn allows an optional flags spec.  */
-  { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
-  { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
-  /* Put opcode 1 ld insns first so shimm gets prefered over limm.
-     "[%b]" is before "[%b,%o]" so 0 offsets don't get printed.  */
-  { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 },
-  { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
-  { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
-  { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1),	I(1)|R(0,13,1), ARC_MACH_5, 0, 0 },
-  { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 },
-  { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 },
-  { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 },
-  { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 },
-  { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 },
-  { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 },
-  { "sbc%.q%.f %a,%b,%c%F%S%L",	I(-1), I(11), ARC_MACH_5, 0, 0 },
-  { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 },
-  { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 },
-  { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 },
-  /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed.  */
-  { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
-  { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
-  { "sub%.q%.f %a,%b,%c%F%S%L",	I(-1), I(10), ARC_MACH_5, 0, 0 },
-  { "xor%.q%.f %a,%b,%c%F%S%L",	I(-1), I(15), ARC_MACH_5, 0, 0 }
-};
-
-const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
-
-const struct arc_operand_value arc_reg_names[] =
-{
-  /* Core register set r0-r63.  */
-
-  /* r0-r28 - general purpose registers.  */
-  { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 },
-  { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 },
-  { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 },
-  { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 },
-  { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 },
-  { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 },
-  { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 },
-  { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 },
-  { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 },
-  { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 },
-  /* Maskable interrupt link register.  */
-  { "ilink1", 29, REG, 0 },
-  /* Maskable interrupt link register.  */
-  { "ilink2", 30, REG, 0 },
-  /* Branch-link register.  */
-  { "blink", 31, REG, 0 },
-
-  /* r32-r59 reserved for extensions.  */
-  { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 },
-  { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 },
-  { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 },
-  { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 },
-  { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 },
-  { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 },
-  { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 },
-  { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 },
-  { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 },
-  { "r59", 59, REG, 0 },
-
-  /* Loop count register (24 bits).  */
-  { "lp_count", 60, REG, 0 },
-  /* Short immediate data indicator setting flags.  */
-  { "r61", 61, REG, ARC_REGISTER_READONLY },
-  /* Long immediate data indicator setting flags.  */
-  { "r62", 62, REG, ARC_REGISTER_READONLY },
-  /* Short immediate data indicator not setting flags.  */
-  { "r63", 63, REG, ARC_REGISTER_READONLY },
-
-  /* Small-data base register.  */
-  { "gp", 26, REG, 0 },
-  /* Frame pointer.  */
-  { "fp", 27, REG, 0 },
-  /* Stack pointer.  */
-  { "sp", 28, REG, 0 },
-
-  { "r29", 29, REG, 0 },
-  { "r30", 30, REG, 0 },
-  { "r31", 31, REG, 0 },
-  { "r60", 60, REG, 0 },
-
-  /* Auxiliary register set.  */
-
-  /* Auxiliary register address map:
-     0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation
-     0xfffffeff-0x80000000 - customer limm allocation
-     0x7fffffff-0x00000100 - ARC limm allocation
-     0x000000ff-0x00000000 - ARC shimm allocation  */
-
-  /* Base case auxiliary registers (shimm address).  */
-  { "status",         0x00, AUXREG, 0 },
-  { "semaphore",      0x01, AUXREG, 0 },
-  { "lp_start",       0x02, AUXREG, 0 },
-  { "lp_end",         0x03, AUXREG, 0 },
-  { "identity",       0x04, AUXREG, ARC_REGISTER_READONLY },
-  { "debug",          0x05, AUXREG, 0 },
-};
-
-const int arc_reg_names_count =
-  sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
-
-/* The suffix table.
-   Operands with the same name must be stored together.  */
-
-const struct arc_operand_value arc_suffixes[] =
-{
-  /* Entry 0 is special, default values aren't printed by the disassembler.  */
-  { "", 0, -1, 0 },
-
-  /* Base case condition codes.  */
-  { "al", 0, COND, 0 },
-  { "ra", 0, COND, 0 },
-  { "eq", 1, COND, 0 },
-  { "z", 1, COND, 0 },
-  { "ne", 2, COND, 0 },
-  { "nz", 2, COND, 0 },
-  { "pl", 3, COND, 0 },
-  { "p", 3, COND, 0 },
-  { "mi", 4, COND, 0 },
-  { "n", 4, COND, 0 },
-  { "cs", 5, COND, 0 },
-  { "c", 5, COND, 0 },
-  { "lo", 5, COND, 0 },
-  { "cc", 6, COND, 0 },
-  { "nc", 6, COND, 0 },
-  { "hs", 6, COND, 0 },
-  { "vs", 7, COND, 0 },
-  { "v", 7, COND, 0 },
-  { "vc", 8, COND, 0 },
-  { "nv", 8, COND, 0 },
-  { "gt", 9, COND, 0 },
-  { "ge", 10, COND, 0 },
-  { "lt", 11, COND, 0 },
-  { "le", 12, COND, 0 },
-  { "hi", 13, COND, 0 },
-  { "ls", 14, COND, 0 },
-  { "pnz", 15, COND, 0 },
-
-  /* Condition codes 16-31 reserved for extensions.  */
-
-  { "f", 1, FLAG, 0 },
-
-  { "nd", ARC_DELAY_NONE, DELAY, 0 },
-  { "d", ARC_DELAY_NORMAL, DELAY, 0 },
-  { "jd", ARC_DELAY_JUMP, DELAY, 0 },
-
-  { "b", 1, SIZE1, 0 },
-  { "b", 1, SIZE10, 0 },
-  { "b", 1, SIZE22, 0 },
-  { "w", 2, SIZE1, 0 },
-  { "w", 2, SIZE10, 0 },
-  { "w", 2, SIZE22, 0 },
-  { "x", 1, SIGN0, 0 },
-  { "x", 1, SIGN9, 0 },
-  { "a", 1, ADDRESS3, 0 },
-  { "a", 1, ADDRESS12, 0 },
-  { "a", 1, ADDRESS24, 0 },
-
-  { "di", 1, CACHEBYPASS5, 0 },
-  { "di", 1, CACHEBYPASS14, 0 },
-  { "di", 1, CACHEBYPASS26, 0 },
-};
-
-const int arc_suffixes_count =
-  sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
-
-/* Indexed by first letter of opcode.  Points to chain of opcodes with same
-   first letter.  */
-static struct arc_opcode *opcode_map[26 + 1];
-
-/* Indexed by insn code.  Points to chain of opcodes with same insn code.  */
-static struct arc_opcode *icode_map[32];
-
-/* Configuration flags.  */
-
-/* Various ARC_HAVE_XXX bits.  */
-static int cpu_type;
-
-/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value.  */
-
-int
-arc_get_opcode_mach (bfd_mach, big_p)
-     int bfd_mach, big_p;
-{
-  static int mach_type_map[] =
-  {
-    ARC_MACH_5,
-    ARC_MACH_6,
-    ARC_MACH_7,
-    ARC_MACH_8
-  };
-  return mach_type_map[bfd_mach - bfd_mach_arc_5] | (big_p ? ARC_MACH_BIG : 0);
-}
-
-/* Initialize any tables that need it.
-   Must be called once at start up (or when first needed).
-
-   FLAGS is a set of bits that say what version of the cpu we have,
-   and in particular at least (one of) ARC_MACH_XXX.  */
-
-void
-arc_opcode_init_tables (flags)
-     int flags;
-{
-  static int init_p = 0;
-
-  cpu_type = flags;
-
-  /* We may be intentionally called more than once (for example gdb will call
-     us each time the user switches cpu).  These tables only need to be init'd
-     once though.  */
-  if (!init_p)
-    {
-      register int i,n;
-
-      memset (arc_operand_map, 0, sizeof (arc_operand_map));
-      n = sizeof (arc_operands) / sizeof (arc_operands[0]);
-      for (i = 0; i < n; ++i)
-	arc_operand_map[arc_operands[i].fmt] = i;
-
-      memset (opcode_map, 0, sizeof (opcode_map));
-      memset (icode_map, 0, sizeof (icode_map));
-      /* Scan the table backwards so macros appear at the front.  */
-      for (i = arc_opcodes_count - 1; i >= 0; --i)
-	{
-	  int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax);
-	  int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value);
-
-	  arc_opcodes[i].next_asm = opcode_map[opcode_hash];
-	  opcode_map[opcode_hash] = &arc_opcodes[i];
-
-	  arc_opcodes[i].next_dis = icode_map[icode_hash];
-	  icode_map[icode_hash] = &arc_opcodes[i];
-	}
-
-      init_p = 1;
-    }
-}
-
-/* Return non-zero if OPCODE is supported on the specified cpu.
-   Cpu selection is made when calling `arc_opcode_init_tables'.  */
-
-int
-arc_opcode_supported (opcode)
-     const struct arc_opcode *opcode;
-{
-  if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type)
-    return 1;
-  return 0;
-}
-
-/* Return the first insn in the chain for assembling INSN.  */
-
-const struct arc_opcode *
-arc_opcode_lookup_asm (insn)
-     const char *insn;
-{
-  return opcode_map[ARC_HASH_OPCODE (insn)];
-}
-
-/* Return the first insn in the chain for disassembling INSN.  */
-
-const struct arc_opcode *
-arc_opcode_lookup_dis (insn)
-     unsigned int insn;
-{
-  return icode_map[ARC_HASH_ICODE (insn)];
-}
-
-/* Nonzero if we've seen an 'f' suffix (in certain insns).  */
-static int flag_p;
-
-/* Nonzero if we've finished processing the 'f' suffix.  */
-static int flagshimm_handled_p;
-
-/* Nonzero if we've seen a 'a' suffix (address writeback).  */
-static int addrwb_p;
-
-/* Nonzero if we've seen a 'q' suffix (condition code).  */
-static int cond_p;
-
-/* Nonzero if we've inserted a nullify condition.  */
-static int nullify_p;
-
-/* The value of the a nullify condition we inserted.  */
-static int nullify;
-
-/* Nonzero if we've inserted jumpflags.  */
-static int jumpflags_p;
-
-/* Nonzero if we've inserted a shimm.  */
-static int shimm_p;
-
-/* The value of the shimm we inserted (each insn only gets one but it can
-   appear multiple times).  */
-static int shimm;
-
-/* Nonzero if we've inserted a limm (during assembly) or seen a limm
-   (during disassembly).  */
-static int limm_p;
-
-/* The value of the limm we inserted.  Each insn only gets one but it can
-   appear multiple times.  */
-static long limm;
-
-/* Insertion functions.  */
-
-/* Called by the assembler before parsing an instruction.  */
-
-void
-arc_opcode_init_insert ()
-{
-  int i;
-
-  for(i = 0; i < OPERANDS; i++)
-    ls_operand[i] = OP_NONE;
-
-  flag_p = 0;
-  flagshimm_handled_p = 0;
-  cond_p = 0;
-  addrwb_p = 0;
-  shimm_p = 0;
-  limm_p = 0;
-  jumpflags_p = 0;
-  nullify_p = 0;
-  nullify = 0; /* the default is important.  */
-}
-
-/* Called by the assembler to see if the insn has a limm operand.
-   Also called by the disassembler to see if the insn contains a limm.  */
-
-int
-arc_opcode_limm_p (limmp)
-     long *limmp;
-{
-  if (limmp)
-    *limmp = limm;
-  return limm_p;
-}
-
 /* Insert a value into a register field.
    If REG is NULL, then this is actually a constant.
 
    We must also handle auxiliary registers for lr/sr insns.  */
 
 static arc_insn
-insert_reg (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     long value;
-     const char **errmsg;
+insert_reg (arc_insn insn,
+	    const struct arc_operand *operand,
+	    int mods,
+	    const struct arc_operand_value *reg,
+	    long value,
+	    const char **errmsg)
 {
   static char buf[100];
   enum operand op_type = OP_NONE;
@@ -700,7 +354,7 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
 	  int marker;
 
 	  op_type = OP_SHIMM;
-	  /* forget about shimm as dest mlm.  */
+	  /* Forget about shimm as dest mlm.  */
 
 	  if ('a' != operand->fmt)
 	    {
@@ -711,7 +365,7 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
 	    }
 	  else
 	    {
-	      /* don't request flag setting on shimm as dest.  */
+	      /* Don't request flag setting on shimm as dest.  */
 	      marker = ARC_REG_SHIMM;
 	    }
 	  insn |= marker << operand->shift;
@@ -727,9 +381,7 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
 	  /* The constant is stored later.  */
 	}
       else
-	{
-	  *errmsg = "unable to fit different valued constants into instruction";
-	}
+	*errmsg = _("unable to fit different valued constants into instruction");
     }
   else
     {
@@ -738,18 +390,18 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
       if (reg->type == AUXREG)
 	{
 	  if (!(mods & ARC_MOD_AUXREG))
-	    *errmsg = "auxiliary register not allowed here";
+	    *errmsg = _("auxiliary register not allowed here");
 	  else
 	    {
-	      if ((insn & I(-1)) == I(2)) /* check for use validity.  */
+	      if ((insn & I(-1)) == I(2)) /* Check for use validity.  */
 		{
 		  if (reg->flags & ARC_REGISTER_READONLY)
-		    *errmsg = "attempt to set readonly register";
+		    *errmsg = _("attempt to set readonly register");
 		}
 	      else
 		{
 		  if (reg->flags & ARC_REGISTER_WRITEONLY)
-		    *errmsg = "attempt to read writeonly register";
+		    *errmsg = _("attempt to read writeonly register");
 		}
 	      insn |= ARC_REG_SHIMM << operand->shift;
 	      insn |= reg->value << arc_operands[reg->type].shift;
@@ -761,17 +413,17 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
 	  if ('a' == operand->fmt || ((insn & I(-1)) < I(2)))
 	    {
 	      if (reg->flags & ARC_REGISTER_READONLY)
-		*errmsg = "attempt to set readonly register";
+		*errmsg = _("attempt to set readonly register");
 	    }
 	  if ('a' != operand->fmt)
 	    {
 	      if (reg->flags & ARC_REGISTER_WRITEONLY)
-		*errmsg = "attempt to read writeonly register";
+		*errmsg = _("attempt to read writeonly register");
 	    }
 	  /* We should never get an invalid register number here.  */
 	  if ((unsigned int) reg->value > 60)
 	    {
-	      sprintf (buf, "invalid register number `%d'", reg->value);
+	      sprintf (buf, _("invalid register number `%d'"), reg->value);
 	      *errmsg = buf;
 	    }
 	  insn |= reg->value << operand->shift;
@@ -804,13 +456,12 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
 /* Called when we see an 'f' flag.  */
 
 static arc_insn
-insert_flag (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand ATTRIBUTE_UNUSED;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
-     long value ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_flag (arc_insn insn,
+	     const struct arc_operand *operand ATTRIBUTE_UNUSED,
+	     int mods ATTRIBUTE_UNUSED,
+	     const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
+	     long value ATTRIBUTE_UNUSED,
+	     const char **errmsg ATTRIBUTE_UNUSED)
 {
   /* We can't store anything in the insn until we've parsed the registers.
      Just record the fact that we've got this flag.  `insert_reg' will use it
@@ -822,13 +473,12 @@ insert_flag (insn, operand, mods, reg, value, errmsg)
 /* Called when we see an nullify condition.  */
 
 static arc_insn
-insert_nullify (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
-     long value;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_nullify (arc_insn insn,
+		const struct arc_operand *operand,
+		int mods ATTRIBUTE_UNUSED,
+		const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
+		long value,
+		const char **errmsg ATTRIBUTE_UNUSED)
 {
   nullify_p = 1;
   insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
@@ -841,13 +491,12 @@ insert_nullify (insn, operand, mods, reg, value, errmsg)
    we've parsed the registers.  */
 
 static arc_insn
-insert_flagfinish (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
-     long value ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_flagfinish (arc_insn insn,
+		   const struct arc_operand *operand,
+		   int mods ATTRIBUTE_UNUSED,
+		   const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
+		   long value ATTRIBUTE_UNUSED,
+		   const char **errmsg ATTRIBUTE_UNUSED)
 {
   if (flag_p && !flagshimm_handled_p)
     {
@@ -862,13 +511,12 @@ insert_flagfinish (insn, operand, mods, reg, value, errmsg)
 /* Called when we see a conditional flag (eg: .eq).  */
 
 static arc_insn
-insert_cond (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
-     long value;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_cond (arc_insn insn,
+	     const struct arc_operand *operand,
+	     int mods ATTRIBUTE_UNUSED,
+	     const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
+	     long value,
+	     const char **errmsg ATTRIBUTE_UNUSED)
 {
   cond_p = 1;
   insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
@@ -882,39 +530,36 @@ insert_cond (insn, operand, mods, reg, value, errmsg)
    ??? The mechanism is sound.  Access to it is a bit klunky right now.  */
 
 static arc_insn
-insert_forcelimm (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand ATTRIBUTE_UNUSED;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
-     long value ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_forcelimm (arc_insn insn,
+		  const struct arc_operand *operand ATTRIBUTE_UNUSED,
+		  int mods ATTRIBUTE_UNUSED,
+		  const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
+		  long value ATTRIBUTE_UNUSED,
+		  const char **errmsg ATTRIBUTE_UNUSED)
 {
   cond_p = 1;
   return insn;
 }
 
 static arc_insn
-insert_addr_wb (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
-     long value ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_addr_wb (arc_insn insn,
+		const struct arc_operand *operand,
+		int mods ATTRIBUTE_UNUSED,
+		const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
+		long value ATTRIBUTE_UNUSED,
+		const char **errmsg ATTRIBUTE_UNUSED)
 {
   addrwb_p = 1 << operand->shift;
   return insn;
 }
 
 static arc_insn
-insert_base (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     long value;
-     const char **errmsg;
+insert_base (arc_insn insn,
+	     const struct arc_operand *operand,
+	     int mods,
+	     const struct arc_operand_value *reg,
+	     long value,
+	     const char **errmsg)
 {
   if (reg != NULL)
     {
@@ -927,10 +572,10 @@ insert_base (insn, operand, mods, reg, value, errmsg)
     {
       if (shimm_p && value != shimm)
 	{
-	  /* convert the previous shimm operand to a limm.  */
+	  /* Convert the previous shimm operand to a limm.  */
 	  limm_p = 1;
 	  limm = shimm;
-	  insn &= ~C(-1); /* we know where the value is in insn.  */
+	  insn &= ~C(-1); /* We know where the value is in insn.  */
 	  insn |= C(ARC_REG_LIMM);
 	  ls_operand[LS_VALUE] = OP_LIMM;
 	}
@@ -944,7 +589,7 @@ insert_base (insn, operand, mods, reg, value, errmsg)
     {
       if (limm_p && value != limm)
 	{
-	  *errmsg = "too many long constants";
+	  *errmsg = _("too many long constants");
 	  return insn;
 	}
       limm_p = 1;
@@ -960,13 +605,12 @@ insert_base (insn, operand, mods, reg, value, errmsg)
    match operand syntax here. we catch bad combinations later.  */
 
 static arc_insn
-insert_offset (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     long value;
-     const char **errmsg;
+insert_offset (arc_insn insn,
+	       const struct arc_operand *operand,
+	       int mods,
+	       const struct arc_operand_value *reg,
+	       long value,
+	       const char **errmsg)
 {
   long minval, maxval;
 
@@ -975,9 +619,9 @@ insert_offset (insn, operand, mods, reg, value, errmsg)
       arc_insn myinsn;
       myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift;
       ls_operand[LS_OFFSET] = OP_REG;
-      if (operand->flags & ARC_OPERAND_LOAD) /* not if store, catch it later.  */
-	if ((insn & I(-1)) != I(1)) /* not if opcode == 1, catch it later.  */
-	  insn |= C(myinsn);
+      if (operand->flags & ARC_OPERAND_LOAD) /* Not if store, catch it later.  */
+	if ((insn & I(-1)) != I(1)) /* Not if opcode == 1, catch it later.  */
+	  insn |= C (myinsn);
     }
   else
     {
@@ -996,9 +640,8 @@ insert_offset (insn, operand, mods, reg, value, errmsg)
       if ((cond_p && !limm_p) || (value < minval || value > maxval))
 	{
 	  if (limm_p && value != limm)
-	    {
-	      *errmsg = "too many long constants";
-	    }
+	    *errmsg = _("too many long constants");
+
 	  else
 	    {
 	      limm_p = 1;
@@ -1016,27 +659,30 @@ insert_offset (insn, operand, mods, reg, value, errmsg)
 	    *errmsg = "need too many limms";
 	  else if (shimm_p && value != shimm)
 	    {
-	      /* check for bad operand combinations before we lose info about them.  */
+	      /* Check for bad operand combinations
+		 before we lose info about them.  */
 	      if ((insn & I(-1)) == I(1))
 		{
-		  *errmsg = "to many shimms in load";
+		  *errmsg = _("to many shimms in load");
 		  goto out;
 		}
 	      if (limm_p && operand->flags & ARC_OPERAND_LOAD)
 		{
-		  *errmsg = "too many long constants";
+		  *errmsg = _("too many long constants");
 		  goto out;
 		}
-	      /* convert what we thought was a shimm to a limm.  */
+	      /* Convert what we thought was a shimm to a limm.  */
 	      limm_p = 1;
 	      limm = shimm;
-	      if (ls_operand[LS_VALUE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE)
+	      if (ls_operand[LS_VALUE] == OP_SHIMM
+		  && operand->flags & ARC_OPERAND_STORE)
 		{
 		  insn &= ~C(-1);
 		  insn |= C(ARC_REG_LIMM);
 		  ls_operand[LS_VALUE] = OP_LIMM;
 		}
-	      if (ls_operand[LS_BASE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE)
+	      if (ls_operand[LS_BASE] == OP_SHIMM
+		  && operand->flags & ARC_OPERAND_STORE)
 		{
 		  insn &= ~B(-1);
 		  insn |= B(ARC_REG_LIMM);
@@ -1055,12 +701,11 @@ insert_offset (insn, operand, mods, reg, value, errmsg)
 /* Used in st insns to do final disasemble syntax check.  */
 
 static long
-extract_st_syntax (insn, operand, mods, opval, invalid)
-     arc_insn *insn;
-     const struct arc_operand *operand ATTRIBUTE_UNUSED;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
-     int *invalid;
+extract_st_syntax (arc_insn *insn,
+		   const struct arc_operand *operand ATTRIBUTE_UNUSED,
+		   int mods ATTRIBUTE_UNUSED,
+		   const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
+		   int *invalid)
 {
 #define ST_SYNTAX(V,B,O) \
 ((ls_operand[LS_VALUE]  == (V) && \
@@ -1086,36 +731,34 @@ extract_st_syntax (insn, operand, mods, opval, invalid)
 }
 
 int
-arc_limm_fixup_adjust(insn)
-     arc_insn insn;
+arc_limm_fixup_adjust (arc_insn insn)
 {
   int retval = 0;
 
-  /* check for st shimm,[limm].  */
+  /* Check for st shimm,[limm].  */
   if ((insn & (I(-1) | C(-1) | B(-1))) ==
       (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM)))
     {
       retval = insn & 0x1ff;
-      if (retval & 0x100) /* sign extend 9 bit offset.  */
+      if (retval & 0x100) /* Sign extend 9 bit offset.  */
 	retval |= ~0x1ff;
     }
-  return -retval; /* negate offset for return.  */
+  return -retval; /* Negate offset for return.  */
 }
 
 /* Used in st insns to do final syntax check.  */
 
 static arc_insn
-insert_st_syntax (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand ATTRIBUTE_UNUSED;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
-     long value ATTRIBUTE_UNUSED;
-     const char **errmsg;
+insert_st_syntax (arc_insn insn,
+		  const struct arc_operand *operand ATTRIBUTE_UNUSED,
+		  int mods ATTRIBUTE_UNUSED,
+		  const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
+		  long value ATTRIBUTE_UNUSED,
+		  const char **errmsg)
 {
-  if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm != 0)
+  if (ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE) && shimm != 0)
     {
-      /* change an illegal insn into a legal one, it's easier to
+      /* Change an illegal insn into a legal one, it's easier to
 	 do it here than to try to handle it during operand scan.  */
       limm_p = 1;
       limm = shimm;
@@ -1126,15 +769,15 @@ insert_st_syntax (insn, operand, mods, reg, value, errmsg)
       ls_operand[LS_VALUE] = OP_LIMM;
     }
 
-  if (ST_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE))
+  if (ST_SYNTAX (OP_REG, OP_SHIMM, OP_NONE)
+      || ST_SYNTAX (OP_LIMM, OP_SHIMM, OP_NONE))
     {
-      /* try to salvage this syntax.  */
-      if (shimm & 0x1) /* odd shimms won't work.  */
+      /* Try to salvage this syntax.  */
+      if (shimm & 0x1) /* Odd shimms won't work.  */
 	{
-	  if (limm_p) /* do we have a limm already?  */
-	    {
-	      *errmsg = "impossible store";
-	    }
+	  if (limm_p) /* Do we have a limm already?  */
+	    *errmsg = _("impossible store");
+
 	  limm_p = 1;
 	  limm = shimm;
 	  shimm = 0;
@@ -1152,56 +795,54 @@ insert_st_syntax (insn, operand, mods, reg, value, errmsg)
 	}
     }
   if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE))
-    {
-      limm += arc_limm_fixup_adjust(insn);
-    }
-  if (!(ST_SYNTAX(OP_REG,OP_REG,OP_NONE)
-	|| ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE)
-	|| ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
-	|| ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
-	|| (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0))
-	|| ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)
-	|| ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE)
-	|| ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM)
-	|| ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM)
-	|| ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM)
-	|| ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE)
-	|| ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM)))
-    *errmsg = "st operand error";
+    limm += arc_limm_fixup_adjust(insn);
+
+  if (!   (ST_SYNTAX (OP_REG,OP_REG,OP_NONE)
+	|| ST_SYNTAX (OP_REG,OP_LIMM,OP_NONE)
+	|| ST_SYNTAX (OP_REG,OP_REG,OP_SHIMM)
+	|| ST_SYNTAX (OP_REG,OP_SHIMM,OP_SHIMM)
+	|| (ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0))
+	|| ST_SYNTAX (OP_SHIMM,OP_LIMM,OP_NONE)
+	|| ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE)
+	|| ST_SYNTAX (OP_SHIMM,OP_REG,OP_SHIMM)
+	|| ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_SHIMM)
+	|| ST_SYNTAX (OP_LIMM,OP_SHIMM,OP_SHIMM)
+	|| ST_SYNTAX (OP_LIMM,OP_REG,OP_NONE)
+	|| ST_SYNTAX (OP_LIMM,OP_REG,OP_SHIMM)))
+    *errmsg = _("st operand error");
   if (addrwb_p)
     {
       if (ls_operand[LS_BASE] != OP_REG)
-	*errmsg = "address writeback not allowed";
+	*errmsg = _("address writeback not allowed");
       insn |= addrwb_p;
     }
   if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm)
-    *errmsg = "store value must be zero";
+    *errmsg = _("store value must be zero");
   return insn;
 }
 
 /* Used in ld insns to do final syntax check.  */
 
 static arc_insn
-insert_ld_syntax (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand ATTRIBUTE_UNUSED;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
-     long value ATTRIBUTE_UNUSED;
-     const char **errmsg;
+insert_ld_syntax (arc_insn insn,
+		  const struct arc_operand *operand ATTRIBUTE_UNUSED,
+		  int mods ATTRIBUTE_UNUSED,
+		  const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
+		  long value ATTRIBUTE_UNUSED,
+		  const char **errmsg)
 {
-#define LD_SYNTAX(D,B,O) \
-((ls_operand[LS_DEST]  == (D) && \
-  ls_operand[LS_BASE]   == (B) && \
-  ls_operand[LS_OFFSET] == (O)))
+#define LD_SYNTAX(D, B, O) \
+  (   (ls_operand[LS_DEST]   == (D) \
+    && ls_operand[LS_BASE]   == (B) \
+    && ls_operand[LS_OFFSET] == (O)))
 
-  int test = insn & I(-1);
+  int test = insn & I (-1);
 
-  if (!(test == I(1)))
+  if (!(test == I (1)))
     {
       if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
 	   || ls_operand[LS_OFFSET] == OP_SHIMM))
-	*errmsg = "invalid load/shimm insn";
+	*errmsg = _("invalid load/shimm insn");
     }
   if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE)
 	|| LD_SYNTAX(OP_REG,OP_REG,OP_REG)
@@ -1210,11 +851,11 @@ insert_ld_syntax (insn, operand, mods, reg, value, errmsg)
 	|| (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1)))
 	|| LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
 	|| (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1)))))
-    *errmsg = "ld operand error";
+    *errmsg = _("ld operand error");
   if (addrwb_p)
     {
       if (ls_operand[LS_BASE] != OP_REG)
-	*errmsg = "address writeback not allowed";
+	*errmsg = _("address writeback not allowed");
       insn |= addrwb_p;
     }
   return insn;
@@ -1223,12 +864,11 @@ insert_ld_syntax (insn, operand, mods, reg, value, errmsg)
 /* Used in ld insns to do final syntax check.  */
 
 static long
-extract_ld_syntax (insn, operand, mods, opval, invalid)
-     arc_insn *insn;
-     const struct arc_operand *operand ATTRIBUTE_UNUSED;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
-     int *invalid;
+extract_ld_syntax (arc_insn *insn,
+		   const struct arc_operand *operand ATTRIBUTE_UNUSED,
+		   int mods ATTRIBUTE_UNUSED,
+		   const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
+		   int *invalid)
 {
   int test = insn[0] & I(-1);
 
@@ -1238,14 +878,14 @@ extract_ld_syntax (insn, operand, mods, opval, invalid)
 	   || ls_operand[LS_OFFSET] == OP_SHIMM))
 	*invalid = 1;
     }
-  if (!((LD_SYNTAX(OP_REG,OP_REG,OP_NONE) && (test == I(1)))
-	|| LD_SYNTAX(OP_REG,OP_REG,OP_REG)
-	|| LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
-	|| (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1)))
-	|| (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1)))
-	|| (LD_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) && (shimm == 0))
-	|| LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
-	|| (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1)))))
+  if (!(   (LD_SYNTAX (OP_REG, OP_REG, OP_NONE) && (test == I(1)))
+	||  LD_SYNTAX (OP_REG, OP_REG, OP_REG)
+	||  LD_SYNTAX (OP_REG, OP_REG, OP_SHIMM)
+	|| (LD_SYNTAX (OP_REG, OP_REG, OP_LIMM) && !(test == I(1)))
+	|| (LD_SYNTAX (OP_REG, OP_LIMM, OP_REG) && !(test == I(1)))
+	|| (LD_SYNTAX (OP_REG, OP_SHIMM, OP_NONE) && (shimm == 0))
+	||  LD_SYNTAX (OP_REG, OP_SHIMM, OP_SHIMM)
+	|| (LD_SYNTAX (OP_REG, OP_LIMM, OP_NONE) && (test == I(1)))))
     *invalid = 1;
   return 0;
 }
@@ -1254,13 +894,12 @@ extract_ld_syntax (insn, operand, mods, opval, invalid)
    value (if present) into the insn.  */
 
 static arc_insn
-insert_shimmfinish (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
-     long value ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_shimmfinish (arc_insn insn,
+		    const struct arc_operand *operand,
+		    int mods ATTRIBUTE_UNUSED,
+		    const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
+		    long value ATTRIBUTE_UNUSED,
+		    const char **errmsg ATTRIBUTE_UNUSED)
 {
   if (shimm_p)
     insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift;
@@ -1280,50 +919,39 @@ insert_shimmfinish (insn, operand, mods, reg, value, errmsg)
    a 2 word quantity.  That's too much so we don't handle them.  */
 
 static arc_insn
-insert_limmfinish (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand ATTRIBUTE_UNUSED;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
-     long value ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_limmfinish (arc_insn insn,
+		   const struct arc_operand *operand ATTRIBUTE_UNUSED,
+		   int mods ATTRIBUTE_UNUSED,
+		   const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
+		   long value ATTRIBUTE_UNUSED,
+		   const char **errmsg ATTRIBUTE_UNUSED)
 {
-#if 0
-  if (limm_p)
-    ; /* nothing to do, gas does it.  */
-#endif
   return insn;
 }
 
 static arc_insn
-insert_jumpflags (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
-     long value;
-     const char **errmsg;
+insert_jumpflags (arc_insn insn,
+		  const struct arc_operand *operand,
+		  int mods ATTRIBUTE_UNUSED,
+		  const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
+		  long value,
+		  const char **errmsg)
 {
   if (!flag_p)
-    {
-      *errmsg = "jump flags, but no .f seen";
-    }
-  if (!limm_p)
-    {
-      *errmsg = "jump flags, but no limm addr";
-    }
-  if (limm & 0xfc000000)
-    {
-      *errmsg = "flag bits of jump address limm lost";
-    }
-  if (limm & 0x03000000)
-    {
-      *errmsg = "attempt to set HR bits";
-    }
-  if ((value & ((1 << operand->bits) - 1)) != value)
-    {
-      *errmsg = "bad jump flags value";
-    }
+    *errmsg = _("jump flags, but no .f seen");
+
+  else if (!limm_p)
+    *errmsg = _("jump flags, but no limm addr");
+
+  else if (limm & 0xfc000000)
+    *errmsg = _("flag bits of jump address limm lost");
+
+  else if (limm & 0x03000000)
+    *errmsg = _("attempt to set HR bits");
+
+  else if ((value & ((1 << operand->bits) - 1)) != value)
+    *errmsg = _("bad jump flags value");
+
   jumpflags_p = 1;
   limm = ((limm & ((1 << operand->shift) - 1))
 	  | ((value & ((1 << operand->bits) - 1)) << operand->shift));
@@ -1333,13 +961,12 @@ insert_jumpflags (insn, operand, mods, reg, value, errmsg)
 /* Called at the end of unary operand macros to copy the B field to C.  */
 
 static arc_insn
-insert_unopmacro (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
-     long value ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_unopmacro (arc_insn insn,
+		  const struct arc_operand *operand,
+		  int mods ATTRIBUTE_UNUSED,
+		  const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
+		  long value ATTRIBUTE_UNUSED,
+		  const char **errmsg ATTRIBUTE_UNUSED)
 {
   insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift;
   return insn;
@@ -1348,16 +975,15 @@ insert_unopmacro (insn, operand, mods, reg, value, errmsg)
 /* Insert a relative address for a branch insn (b, bl, or lp).  */
 
 static arc_insn
-insert_reladdr (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
-     long value;
-     const char **errmsg;
+insert_reladdr (arc_insn insn,
+		const struct arc_operand *operand,
+		int mods ATTRIBUTE_UNUSED,
+		const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
+		long value,
+		const char **errmsg)
 {
   if (value & 3)
-    *errmsg = "branch address not on 4 byte boundary";
+    *errmsg = _("branch address not on 4 byte boundary");
   insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift;
   return insn;
 }
@@ -1377,30 +1003,23 @@ insert_reladdr (insn, operand, mods, reg, value, errmsg)
    set the default correctly, though.  */
 
 static arc_insn
-insert_absaddr (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand ATTRIBUTE_UNUSED;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
-     long value ATTRIBUTE_UNUSED;
-     const char **errmsg;
+insert_absaddr (arc_insn insn,
+		const struct arc_operand *operand ATTRIBUTE_UNUSED,
+		int mods ATTRIBUTE_UNUSED,
+		const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
+		long value ATTRIBUTE_UNUSED,
+		const char **errmsg)
 {
   if (limm_p)
     {
-      /* if it is a jump and link, .jd must be specified.  */
-      if (insn & R(-1,9,1))
+      /* If it is a jump and link, .jd must be specified.  */
+      if (insn & R (-1, 9, 1))
 	{
 	  if (!nullify_p)
-	    {
-	      insn |=  0x02 << 5;  /* default nullify to .jd.  */
-	    }
-	  else
-	    {
-	      if (nullify != 0x02)
-		{
-		  *errmsg = "must specify .jd or no nullify suffix";
-		}
-	    }
+	    insn |=  0x02 << 5;  /* Default nullify to .jd.  */
+
+	  else if (nullify != 0x02)
+	    *errmsg = _("must specify .jd or no nullify suffix");
 	}
     }
   return insn;
@@ -1413,14 +1032,36 @@ insert_absaddr (insn, operand, mods, reg, value, errmsg)
    a suffix table entry for the "false" case, so values of zero must be
    obtained from the return value (*OPVAL == NULL).  */
 
-static const struct arc_operand_value *lookup_register (int type, long regno);
-
 /* Called by the disassembler before printing an instruction.  */
 
 void
-arc_opcode_init_extract ()
+arc_opcode_init_extract (void)
 {
-  arc_opcode_init_insert();
+  arc_opcode_init_insert ();
+}
+
+static const struct arc_operand_value *
+lookup_register (int type, long regno)
+{
+  const struct arc_operand_value *r,*end;
+  struct arc_ext_operand_value *ext_oper = arc_ext_operands;
+
+  while (ext_oper)
+    {
+      if (ext_oper->operand.type == type && ext_oper->operand.value == regno)
+	return (&ext_oper->operand);
+      ext_oper = ext_oper->next;
+    }
+
+  if (type == REG)
+    return &arc_reg_names[regno];
+
+  /* ??? This is a little slow and can be speeded up.  */
+  for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count;
+       r < end; ++r)
+    if (type == r->type	&& regno == r->value)
+      return r;
+  return 0;
 }
 
 /* As we're extracting registers, keep an eye out for the 'f' indicator
@@ -1431,12 +1072,11 @@ arc_opcode_init_extract ()
    constants with special names.  */
 
 static long
-extract_reg (insn, operand, mods, opval, invalid)
-     arc_insn *insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value **opval;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_reg (arc_insn *insn,
+	     const struct arc_operand *operand,
+	     int mods,
+	     const struct arc_operand_value **opval,
+	     int *invalid ATTRIBUTE_UNUSED)
 {
   int regno;
   long value;
@@ -1449,7 +1089,7 @@ extract_reg (insn, operand, mods, opval, invalid)
   if (regno == ARC_REG_SHIMM)
     {
       op_type = OP_SHIMM;
-      /* always return zero if dest is a shimm  mlm.  */
+      /* Always return zero if dest is a shimm  mlm.  */
 
       if ('a' != operand->fmt)
 	{
@@ -1462,16 +1102,13 @@ extract_reg (insn, operand, mods, opval, invalid)
 	  flagshimm_handled_p = 1;
 	}
       else
-	{
-	  value = 0;
-	}
+	value = 0;
     }
   else if (regno == ARC_REG_SHIMM_UPDATE)
     {
       op_type = OP_SHIMM;
 
-      /* always return zero if dest is a shimm  mlm.  */
-
+      /* Always return zero if dest is a shimm  mlm.  */
       if ('a' != operand->fmt)
 	{
 	  value = *insn & 511;
@@ -1479,9 +1116,8 @@ extract_reg (insn, operand, mods, opval, invalid)
 	    value -= 512;
 	}
       else
-	{
-	  value = 0;
-	}
+	value = 0;
+
       flag_p = 1;
       flagshimm_handled_p = 1;
     }
@@ -1490,17 +1126,18 @@ extract_reg (insn, operand, mods, opval, invalid)
       op_type = OP_LIMM;
       value = insn[1];
       limm_p = 1;
-      /* if this is a jump instruction (j,jl), show new pc correctly.  */
+
+      /* If this is a jump instruction (j,jl), show new pc correctly.  */
       if (0x07 == ((*insn & I(-1)) >> 27))
-	{
-	  value = (value & 0xffffff);
-	}
+	value = (value & 0xffffff);
     }
+
   /* It's a register, set OPVAL (that's the only way we distinguish registers
      from constants here).  */
   else
     {
       const struct arc_operand_value *reg = lookup_register (REG, regno);
+
       op_type = OP_REG;
 
       if (reg == NULL)
@@ -1521,6 +1158,7 @@ extract_reg (insn, operand, mods, opval, invalid)
       if (reg != NULL && opval != NULL)
 	*opval = reg;
     }
+
   switch(operand->fmt)
     {
     case 'a':
@@ -1547,12 +1185,11 @@ extract_reg (insn, operand, mods, opval, invalid)
    This value is actually stored in the register field.  */
 
 static long
-extract_flag (insn, operand, mods, opval, invalid)
-     arc_insn *insn;
-     const struct arc_operand *operand;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value **opval;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_flag (arc_insn *insn,
+	      const struct arc_operand *operand,
+	      int mods ATTRIBUTE_UNUSED,
+	      const struct arc_operand_value **opval,
+	      int *invalid ATTRIBUTE_UNUSED)
 {
   int f;
   const struct arc_operand_value *val;
@@ -1578,12 +1215,11 @@ extract_flag (insn, operand, mods, opval, invalid)
    zero.  */
 
 static long
-extract_cond (insn, operand, mods, opval, invalid)
-     arc_insn *insn;
-     const struct arc_operand *operand;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value **opval;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_cond (arc_insn *insn,
+	      const struct arc_operand *operand,
+	      int mods ATTRIBUTE_UNUSED,
+	      const struct arc_operand_value **opval,
+	      int *invalid ATTRIBUTE_UNUSED)
 {
   long cond;
   const struct arc_operand_value *val;
@@ -1605,12 +1241,11 @@ extract_cond (insn, operand, mods, opval, invalid)
    We return the value as a real address (not right shifted by 2).  */
 
 static long
-extract_reladdr (insn, operand, mods, opval, invalid)
-     arc_insn *insn;
-     const struct arc_operand *operand;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_reladdr (arc_insn *insn,
+		 const struct arc_operand *operand,
+		 int mods ATTRIBUTE_UNUSED,
+		 const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
+		 int *invalid ATTRIBUTE_UNUSED)
 {
   long addr;
 
@@ -1621,14 +1256,14 @@ extract_reladdr (insn, operand, mods, opval, invalid)
   return addr << 2;
 }
 
-/* extract the flags bits from a j or jl long immediate.  */
+/* Extract the flags bits from a j or jl long immediate.  */
+
 static long
-extract_jumpflags(insn, operand, mods, opval, invalid)
-     arc_insn *insn;
-     const struct arc_operand *operand;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
-     int *invalid;
+extract_jumpflags (arc_insn *insn,
+		   const struct arc_operand *operand,
+		   int mods ATTRIBUTE_UNUSED,
+		   const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
+		   int *invalid)
 {
   if (!flag_p || !limm_p)
     *invalid = 1;
@@ -1636,15 +1271,14 @@ extract_jumpflags(insn, operand, mods, opval, invalid)
 	  ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0);
 }
 
-/* extract st insn's offset.  */
+/* Extract st insn's offset.  */
 
 static long
-extract_st_offset (insn, operand, mods, opval, invalid)
-     arc_insn *insn;
-     const struct arc_operand *operand;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
-     int *invalid;
+extract_st_offset (arc_insn *insn,
+		   const struct arc_operand *operand,
+		   int mods ATTRIBUTE_UNUSED,
+		   const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
+		   int *invalid)
 {
   int value = 0;
 
@@ -1657,21 +1291,19 @@ extract_st_offset (insn, operand, mods, opval, invalid)
 	ls_operand[LS_OFFSET] = OP_SHIMM;
     }
   else
-    {
-      *invalid = 1;
-    }
-  return(value);
+    *invalid = 1;
+
+  return value;
 }
 
-/* extract ld insn's offset.  */
+/* Extract ld insn's offset.  */
 
 static long
-extract_ld_offset (insn, operand, mods, opval, invalid)
-     arc_insn *insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value **opval;
-     int *invalid;
+extract_ld_offset (arc_insn *insn,
+		   const struct arc_operand *operand,
+		   int mods,
+		   const struct arc_operand_value **opval,
+		   int *invalid)
 {
   int test = insn[0] & I(-1);
   int value;
@@ -1683,9 +1315,10 @@ extract_ld_offset (insn, operand, mods, opval, invalid)
 	value -= 512;
       if (value)
 	ls_operand[LS_OFFSET] = OP_SHIMM;
-      return(value);
+
+      return value;
     }
-  /* if it isn't in the insn, it's concealed behind reg 'c'.  */
+  /* If it isn't in the insn, it's concealed behind reg 'c'.  */
   return extract_reg (insn, &arc_operands[arc_operand_map['c']],
 		      mods, opval, invalid);
 }
@@ -1695,12 +1328,11 @@ extract_ld_offset (insn, operand, mods, opval, invalid)
    and we don't want the disassembler to confuse them.  */
 
 static long
-extract_unopmacro (insn, operand, mods, opval, invalid)
-     arc_insn *insn;
-     const struct arc_operand *operand ATTRIBUTE_UNUSED;
-     int mods ATTRIBUTE_UNUSED;
-     const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
-     int *invalid;
+extract_unopmacro (arc_insn *insn,
+		   const struct arc_operand *operand ATTRIBUTE_UNUSED,
+		   int mods ATTRIBUTE_UNUSED,
+		   const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
+		   int *invalid)
 {
   /* This misses the case where B == ARC_REG_SHIMM_UPDATE &&
      C == ARC_REG_SHIMM (or vice versa).  No big deal.  Those insns will get
@@ -1711,98 +1343,404 @@ extract_unopmacro (insn, operand, mods, opval, invalid)
       *invalid = 1;
   return 0;
 }
+
+/* ARC instructions.
 
-/* Utility for the extraction functions to return the index into
-   `arc_suffixes'.  */
+   Longer versions of insns must appear before shorter ones (if gas sees
+   "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is
+   junk).  This isn't necessary for `ld' because of the trailing ']'.
 
-const struct arc_operand_value *
-arc_opcode_lookup_suffix (type, value)
-     const struct arc_operand *type;
-     int value;
+   Instructions that are really macros based on other insns must appear
+   before the real insn so they're chosen when disassembling.  Eg: The `mov'
+   insn is really the `and' insn.  */
+
+struct arc_opcode arc_opcodes[] =
 {
-  register const struct arc_operand_value *v,*end;
-  struct arc_ext_operand_value *ext_oper = arc_ext_operands;
+  /* Base case instruction set (core versions 5-8).  */
 
-  while (ext_oper)
+  /* "mov" is really an "and".  */
+  { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 },
+  /* "asl" is really an "add".  */
+  { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
+  /* "lsl" is really an "add".  */
+  { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
+  /* "nop" is really an "xor".  */
+  { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 },
+  /* "rlc" is really an "adc".  */
+  { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 },
+  { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 },
+  { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 },
+  { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 },
+  { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 },
+  { "bic%.q%.f %a,%b,%c%F%S%L",	I(-1), I(14), ARC_MACH_5, 0, 0 },
+  { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+  { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+  { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 },
+  { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 },
+  { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 },
+  { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 },
+  { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 },
+  { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 },
+  /* %Q: force cond_p=1 -> no shimm values. This insn allows an
+     optional flags spec.  */
+  { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+  { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+  /* This insn allows an optional flags spec.  */
+  { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+  { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+  /* Put opcode 1 ld insns first so shimm gets prefered over limm.
+     "[%b]" is before "[%b,%o]" so 0 offsets don't get printed.  */
+  { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 },
+  { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
+  { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
+  { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1),	I(1)|R(0,13,1), ARC_MACH_5, 0, 0 },
+  { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 },
+  { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 },
+  { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 },
+  { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 },
+  { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 },
+  { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 },
+  { "sbc%.q%.f %a,%b,%c%F%S%L",	I(-1), I(11), ARC_MACH_5, 0, 0 },
+  { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 },
+  { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 },
+  { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 },
+  /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed.  */
+  { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
+  { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
+  { "sub%.q%.f %a,%b,%c%F%S%L",	I(-1), I(10), ARC_MACH_5, 0, 0 },
+  { "xor%.q%.f %a,%b,%c%F%S%L",	I(-1), I(15), ARC_MACH_5, 0, 0 }
+};
+
+const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
+
+const struct arc_operand_value arc_reg_names[] =
+{
+  /* Core register set r0-r63.  */
+
+  /* r0-r28 - general purpose registers.  */
+  { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 },
+  { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 },
+  { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 },
+  { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 },
+  { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 },
+  { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 },
+  { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 },
+  { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 },
+  { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 },
+  { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 },
+  /* Maskable interrupt link register.  */
+  { "ilink1", 29, REG, 0 },
+  /* Maskable interrupt link register.  */
+  { "ilink2", 30, REG, 0 },
+  /* Branch-link register.  */
+  { "blink", 31, REG, 0 },
+
+  /* r32-r59 reserved for extensions.  */
+  { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 },
+  { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 },
+  { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 },
+  { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 },
+  { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 },
+  { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 },
+  { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 },
+  { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 },
+  { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 },
+  { "r59", 59, REG, 0 },
+
+  /* Loop count register (24 bits).  */
+  { "lp_count", 60, REG, 0 },
+  /* Short immediate data indicator setting flags.  */
+  { "r61", 61, REG, ARC_REGISTER_READONLY },
+  /* Long immediate data indicator setting flags.  */
+  { "r62", 62, REG, ARC_REGISTER_READONLY },
+  /* Short immediate data indicator not setting flags.  */
+  { "r63", 63, REG, ARC_REGISTER_READONLY },
+
+  /* Small-data base register.  */
+  { "gp", 26, REG, 0 },
+  /* Frame pointer.  */
+  { "fp", 27, REG, 0 },
+  /* Stack pointer.  */
+  { "sp", 28, REG, 0 },
+
+  { "r29", 29, REG, 0 },
+  { "r30", 30, REG, 0 },
+  { "r31", 31, REG, 0 },
+  { "r60", 60, REG, 0 },
+
+  /* Auxiliary register set.  */
+
+  /* Auxiliary register address map:
+     0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation
+     0xfffffeff-0x80000000 - customer limm allocation
+     0x7fffffff-0x00000100 - ARC limm allocation
+     0x000000ff-0x00000000 - ARC shimm allocation  */
+
+  /* Base case auxiliary registers (shimm address).  */
+  { "status",         0x00, AUXREG, 0 },
+  { "semaphore",      0x01, AUXREG, 0 },
+  { "lp_start",       0x02, AUXREG, 0 },
+  { "lp_end",         0x03, AUXREG, 0 },
+  { "identity",       0x04, AUXREG, ARC_REGISTER_READONLY },
+  { "debug",          0x05, AUXREG, 0 },
+};
+
+const int arc_reg_names_count =
+  sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
+
+/* The suffix table.
+   Operands with the same name must be stored together.  */
+
+const struct arc_operand_value arc_suffixes[] =
+{
+  /* Entry 0 is special, default values aren't printed by the disassembler.  */
+  { "", 0, -1, 0 },
+
+  /* Base case condition codes.  */
+  { "al", 0, COND, 0 },
+  { "ra", 0, COND, 0 },
+  { "eq", 1, COND, 0 },
+  { "z", 1, COND, 0 },
+  { "ne", 2, COND, 0 },
+  { "nz", 2, COND, 0 },
+  { "pl", 3, COND, 0 },
+  { "p", 3, COND, 0 },
+  { "mi", 4, COND, 0 },
+  { "n", 4, COND, 0 },
+  { "cs", 5, COND, 0 },
+  { "c", 5, COND, 0 },
+  { "lo", 5, COND, 0 },
+  { "cc", 6, COND, 0 },
+  { "nc", 6, COND, 0 },
+  { "hs", 6, COND, 0 },
+  { "vs", 7, COND, 0 },
+  { "v", 7, COND, 0 },
+  { "vc", 8, COND, 0 },
+  { "nv", 8, COND, 0 },
+  { "gt", 9, COND, 0 },
+  { "ge", 10, COND, 0 },
+  { "lt", 11, COND, 0 },
+  { "le", 12, COND, 0 },
+  { "hi", 13, COND, 0 },
+  { "ls", 14, COND, 0 },
+  { "pnz", 15, COND, 0 },
+
+  /* Condition codes 16-31 reserved for extensions.  */
+
+  { "f", 1, FLAG, 0 },
+
+  { "nd", ARC_DELAY_NONE, DELAY, 0 },
+  { "d", ARC_DELAY_NORMAL, DELAY, 0 },
+  { "jd", ARC_DELAY_JUMP, DELAY, 0 },
+
+  { "b", 1, SIZE1, 0 },
+  { "b", 1, SIZE10, 0 },
+  { "b", 1, SIZE22, 0 },
+  { "w", 2, SIZE1, 0 },
+  { "w", 2, SIZE10, 0 },
+  { "w", 2, SIZE22, 0 },
+  { "x", 1, SIGN0, 0 },
+  { "x", 1, SIGN9, 0 },
+  { "a", 1, ADDRESS3, 0 },
+  { "a", 1, ADDRESS12, 0 },
+  { "a", 1, ADDRESS24, 0 },
+
+  { "di", 1, CACHEBYPASS5, 0 },
+  { "di", 1, CACHEBYPASS14, 0 },
+  { "di", 1, CACHEBYPASS26, 0 },
+};
+
+const int arc_suffixes_count =
+  sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
+
+/* Indexed by first letter of opcode.  Points to chain of opcodes with same
+   first letter.  */
+static struct arc_opcode *opcode_map[26 + 1];
+
+/* Indexed by insn code.  Points to chain of opcodes with same insn code.  */
+static struct arc_opcode *icode_map[32];
+
+/* Configuration flags.  */
+
+/* Various ARC_HAVE_XXX bits.  */
+static int cpu_type;
+
+/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value.  */
+
+int
+arc_get_opcode_mach (int bfd_mach, int big_p)
+{
+  static int mach_type_map[] =
+  {
+    ARC_MACH_5,
+    ARC_MACH_6,
+    ARC_MACH_7,
+    ARC_MACH_8
+  };
+  return mach_type_map[bfd_mach - bfd_mach_arc_5] | (big_p ? ARC_MACH_BIG : 0);
+}
+
+/* Initialize any tables that need it.
+   Must be called once at start up (or when first needed).
+
+   FLAGS is a set of bits that say what version of the cpu we have,
+   and in particular at least (one of) ARC_MACH_XXX.  */
+
+void
+arc_opcode_init_tables (int flags)
+{
+  static int init_p = 0;
+
+  cpu_type = flags;
+
+  /* We may be intentionally called more than once (for example gdb will call
+     us each time the user switches cpu).  These tables only need to be init'd
+     once though.  */
+  if (!init_p)
     {
-      if (type == &arc_operands[ext_oper->operand.type]
-	  && value == ext_oper->operand.value)
-	return (&ext_oper->operand);
-      ext_oper = ext_oper->next;
+      int i,n;
+
+      memset (arc_operand_map, 0, sizeof (arc_operand_map));
+      n = sizeof (arc_operands) / sizeof (arc_operands[0]);
+      for (i = 0; i < n; ++i)
+	arc_operand_map[arc_operands[i].fmt] = i;
+
+      memset (opcode_map, 0, sizeof (opcode_map));
+      memset (icode_map, 0, sizeof (icode_map));
+      /* Scan the table backwards so macros appear at the front.  */
+      for (i = arc_opcodes_count - 1; i >= 0; --i)
+	{
+	  int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax);
+	  int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value);
+
+	  arc_opcodes[i].next_asm = opcode_map[opcode_hash];
+	  opcode_map[opcode_hash] = &arc_opcodes[i];
+
+	  arc_opcodes[i].next_dis = icode_map[icode_hash];
+	  icode_map[icode_hash] = &arc_opcodes[i];
+	}
+
+      init_p = 1;
     }
+}
 
-  /* ??? This is a little slow and can be speeded up.  */
+/* Return non-zero if OPCODE is supported on the specified cpu.
+   Cpu selection is made when calling `arc_opcode_init_tables'.  */
 
-  for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v)
-    if (type == &arc_operands[v->type]
-	&& value == v->value)
-      return v;
+int
+arc_opcode_supported (const struct arc_opcode *opcode)
+{
+  if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type)
+    return 1;
   return 0;
 }
 
-static const struct arc_operand_value *
-lookup_register (type, regno)
-     int type;
-     long regno;
+/* Return the first insn in the chain for assembling INSN.  */
+
+const struct arc_opcode *
+arc_opcode_lookup_asm (const char *insn)
+{
+  return opcode_map[ARC_HASH_OPCODE (insn)];
+}
+
+/* Return the first insn in the chain for disassembling INSN.  */
+
+const struct arc_opcode *
+arc_opcode_lookup_dis (unsigned int insn)
+{
+  return icode_map[ARC_HASH_ICODE (insn)];
+}
+
+/* Called by the assembler before parsing an instruction.  */
+
+void
+arc_opcode_init_insert (void)
 {
-  register const struct arc_operand_value *r,*end;
+  int i;
+
+  for(i = 0; i < OPERANDS; i++)
+    ls_operand[i] = OP_NONE;
+
+  flag_p = 0;
+  flagshimm_handled_p = 0;
+  cond_p = 0;
+  addrwb_p = 0;
+  shimm_p = 0;
+  limm_p = 0;
+  jumpflags_p = 0;
+  nullify_p = 0;
+  nullify = 0; /* The default is important.  */
+}
+
+/* Called by the assembler to see if the insn has a limm operand.
+   Also called by the disassembler to see if the insn contains a limm.  */
+
+int
+arc_opcode_limm_p (long *limmp)
+{
+  if (limmp)
+    *limmp = limm;
+  return limm_p;
+}
+
+/* Utility for the extraction functions to return the index into
+   `arc_suffixes'.  */
+
+const struct arc_operand_value *
+arc_opcode_lookup_suffix (const struct arc_operand *type, int value)
+{
+  const struct arc_operand_value *v,*end;
   struct arc_ext_operand_value *ext_oper = arc_ext_operands;
 
   while (ext_oper)
     {
-      if (ext_oper->operand.type == type && ext_oper->operand.value == regno)
+      if (type == &arc_operands[ext_oper->operand.type]
+	  && value == ext_oper->operand.value)
 	return (&ext_oper->operand);
       ext_oper = ext_oper->next;
     }
 
-  if (type == REG)
-    return &arc_reg_names[regno];
-
   /* ??? This is a little slow and can be speeded up.  */
-
-  for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count;
-       r < end; ++r)
-    if (type == r->type	&& regno == r->value)
-      return r;
+  for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v)
+    if (type == &arc_operands[v->type]
+	&& value == v->value)
+      return v;
   return 0;
 }
 
 int
-arc_insn_is_j(insn)
-     arc_insn insn;
+arc_insn_is_j (arc_insn insn)
 {
   return (insn & (I(-1))) == I(0x7);
 }
 
 int
-arc_insn_not_jl(insn)
-     arc_insn insn;
+arc_insn_not_jl (arc_insn insn)
 {
   return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1)))
 	  != (I(0x7) | R(-1,9,1)));
 }
 
 int
-arc_operand_type(int opertype)
+arc_operand_type (int opertype)
 {
   switch (opertype)
     {
     case 0:
-      return(COND);
+      return COND;
       break;
     case 1:
-      return(REG);
+      return REG;
       break;
     case 2:
-      return(AUXREG);
+      return AUXREG;
       break;
     }
   return -1;
 }
 
 struct arc_operand_value *
-get_ext_suffix(s)
-     char *s;
+get_ext_suffix (char *s)
 {
   struct arc_ext_operand_value *suffix = arc_ext_operands;
 
@@ -1817,7 +1755,7 @@ get_ext_suffix(s)
 }
 
 int
-arc_get_noshortcut_flag()
+arc_get_noshortcut_flag (void)
 {
   return ARC_REGISTER_NOSHORT_CUT;
 }
diff --git a/opcodes/avr-dis.c b/opcodes/avr-dis.c
index 6234d9e..1530084 100644
--- a/opcodes/avr-dis.c
+++ b/opcodes/avr-dis.c
@@ -1,21 +1,21 @@
 /* Disassemble AVR instructions.
-   Copyright 1999, 2000, 2002, 2004 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2002, 2004, 2005 Free Software Foundation, Inc.
 
    Contributed by Denis Chertykov <denisc@overta.ru>
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 #include <assert.h>
 #include "sysdep.h"
@@ -28,7 +28,7 @@ struct avr_opcodes_s
   char *name;
   char *constraints;
   char *opcode;
-  int insn_size;		/* in words */
+  int insn_size;		/* In words.  */
   int isa;
   unsigned int bin_opcode;
 };
@@ -42,9 +42,6 @@ const struct avr_opcodes_s avr_opcodes[] =
   {NULL, NULL, NULL, 0, 0, 0}
 };
 
-static int avr_operand (unsigned int, unsigned int, unsigned int, int,
-                        char *, char *, int, int *, bfd_vma *);
-
 static int
 avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constraint,
              char *buf, char *comment, int regs, int *sym, bfd_vma *sym_addr)
@@ -57,9 +54,9 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
       /* Any register operand.  */
     case 'r':
       if (regs)
-	insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* source register */
+	insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* Source register.  */
       else
-	insn = (insn & 0x01f0) >> 4; /* destination register */
+	insn = (insn & 0x01f0) >> 4; /* Destination register.  */
       
       sprintf (buf, "r%d", insn);
       break;
@@ -201,6 +198,7 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
     case 'P':
       {
 	unsigned int x;
+
 	x = (insn & 0xf);
 	x |= (insn >> 5) & 0x30;
 	sprintf (buf, "0x%02x", x);
@@ -231,29 +229,24 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
     return ok;
 }
 
-static unsigned short avrdis_opcode PARAMS ((bfd_vma, disassemble_info *));
-
 static unsigned short
-avrdis_opcode (addr, info)
-     bfd_vma addr;
-     disassemble_info *info;
+avrdis_opcode (bfd_vma addr, disassemble_info *info)
 {
   bfd_byte buffer[2];
   int status;
-  status = info->read_memory_func(addr, buffer, 2, info);
-  if (status != 0)
-    {
-      info->memory_error_func(status, addr, info);
-      return -1;
-    }
-  return bfd_getl16 (buffer);
+
+  status = info->read_memory_func (addr, buffer, 2, info);
+
+  if (status == 0)
+    return bfd_getl16 (buffer);
+
+  info->memory_error_func (status, addr, info);
+  return -1;
 }
 
 
 int
-print_insn_avr(addr, info)
-     bfd_vma addr;
-     disassemble_info *info;
+print_insn_avr (bfd_vma addr, disassemble_info *info)
 {
   unsigned int insn, insn2;
   const struct avr_opcodes_s *opcode;
@@ -274,8 +267,7 @@ print_insn_avr(addr, info)
 
       nopcodes = sizeof (avr_opcodes) / sizeof (struct avr_opcodes_s);
       
-      avr_bin_masks = (unsigned int *)
-	xmalloc (nopcodes * sizeof (unsigned int));
+      avr_bin_masks = xmalloc (nopcodes * sizeof (unsigned int));
 
       for (opcode = avr_opcodes, maskptr = avr_bin_masks;
 	   opcode->name;
@@ -305,10 +297,8 @@ print_insn_avr(addr, info)
   for (opcode = avr_opcodes, maskptr = avr_bin_masks;
        opcode->name;
        opcode++, maskptr++)
-    {
-      if ((insn & *maskptr) == opcode->bin_opcode)
-	break;
-    }
+    if ((insn & *maskptr) == opcode->bin_opcode)
+      break;
   
   /* Special case: disassemble `ldd r,b+0' as `ld r,b', and
      `std b+0,r' as `st b,r' (next entry in the table).  */
diff --git a/opcodes/cgen-asm.in b/opcodes/cgen-asm.in
index fdd3c43..ea7fb3b 100644
--- a/opcodes/cgen-asm.in
+++ b/opcodes/cgen-asm.in
@@ -1,26 +1,27 @@
 /* Assembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-asm.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-asm.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -421,30 +422,3 @@ const CGEN_INSN *
     return NULL;
   }
 }
-
-#if 0 /* This calls back to GAS which we can't do without care.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   This lets GAS parse registers for us.
-   ??? Interesting idea but not currently used.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   FIXME: Not currently used.  */
-
-void
-@arch@_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
-{
-  CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
-  const CGEN_KEYWORD_ENTRY * ke;
-
-  while ((ke = cgen_keyword_search_next (& search)) != NULL)
-    {
-#if 0 /* Unnecessary, should be done in the search routine.  */
-      if (! @arch@_cgen_opval_supported (ke))
-	continue;
-#endif
-      cgen_asm_record_register (cd, ke->name, ke->value);
-    }
-}
-
-#endif /* 0 */
diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in
index 8aea4c0..bc2a7d3 100644
--- a/opcodes/cgen-dis.in
+++ b/opcodes/cgen-dis.in
@@ -1,27 +1,27 @@
 /* Disassembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-dis.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-dis.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
-Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -56,7 +56,7 @@ static int read_insn
   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
    unsigned long *);
 
-/* -- disassembler routines inserted here */
+/* -- disassembler routines inserted here.  */
 
 /* Default print handler.  */
 
@@ -101,7 +101,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 
   /* Print the operand as directed by the attributes.  */
   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
-    ; /* nothing to do */
+    ; /* Nothing to do.  */
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
     (*info->print_address_func) (value, info);
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@@ -183,6 +183,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
+
   if (status != 0)
     {
       (*info->memory_error_func) (status, pc, info);
@@ -287,13 +288,13 @@ print_insn (CGEN_CPU_DESC cd,
 	    length = CGEN_EXTRACT_FN (cd, insn)
 	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 
-	  /* length < 0 -> error */
+	  /* Length < 0 -> error.  */
 	  if (length < 0)
 	    return length;
 	  if (length > 0)
 	    {
 	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
-	      /* length is in bits, result is in bytes */
+	      /* Length is in bits, result is in bytes.  */
 	      return length / 8;
 	    }
 	}
@@ -343,7 +344,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
    Print one instruction from PC on INFO->STREAM.
    Return the size of the instruction (in bytes).  */
 
-typedef struct cpu_desc_list {
+typedef struct cpu_desc_list
+{
   struct cpu_desc_list *next;
   int isa;
   int mach;
@@ -428,7 +430,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
       if (!cd)
 	abort ();
 
-      /* save this away for future reference */
+      /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
       cl->isa = isa;
diff --git a/opcodes/cgen-ibld.in b/opcodes/cgen-ibld.in
index 3072bbd..75506cd 100644
--- a/opcodes/cgen-ibld.in
+++ b/opcodes/cgen-ibld.in
@@ -1,25 +1,26 @@
 /* Instruction building/extraction support for @arch@. -*- C -*-
 
-THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
-- the resultant file is machine generated, cgen-ibld.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+   - the resultant file is machine generated, cgen-ibld.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #include "opintl.h"
 #include "safe-ctype.h"
 
-#undef min
+#undef  min
 #define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
+#undef  max
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 /* Used by the ifield rtx function.  */
@@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
   if (length == 0)
     return NULL;
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
 
 #if CGEN_INT_INSN_P
 /* Cover function to store an insn value into an integral insn.  Must go here
- because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
+   because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
       int shift = insn_length - length;
       /* Written this way to avoid undefined behaviour.  */
       CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
       *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
     }
 }
@@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
 {
   unsigned long x;
   int shift;
-#if 0
-  int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
-#endif
+
   x = cgen_get_insn_value (cd, bufp, word_length);
 
   if (CGEN_INSN_LSB0_P)
@@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
       return 1;
     }
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -539,4 +527,4 @@ extract_insn_normal (CGEN_CPU_DESC cd,
   return CGEN_INSN_BITSIZE (insn);
 }
 
-/* machine generated code added here */
+/* Machine generated code added here.  */
diff --git a/opcodes/cgen-opc.c b/opcodes/cgen-opc.c
index 9ca6ab5..d34aac8 100644
--- a/opcodes/cgen-opc.c
+++ b/opcodes/cgen-opc.c
@@ -157,7 +157,7 @@ cgen_keyword_search_init (CGEN_KEYWORD *kt, const char *spec)
 {
   CGEN_KEYWORD_SEARCH search;
 
-  /* FIXME: Need to specify format of PARAMS.  */
+  /* FIXME: Need to specify format of params.  */
   if (spec != NULL)
     abort ();
 
diff --git a/opcodes/cris-dis.c b/opcodes/cris-dis.c
index 967d699..075cca7 100644
--- a/opcodes/cris-dis.c
+++ b/opcodes/cris-dis.c
@@ -3,21 +3,22 @@
    Contributed by Axis Communications AB, Lund, Sweden.
    Written by Hans-Peter Nilsson.
 
-This file is part of the GNU binutils and GDB, the GNU debugger.
+   This file is part of the GNU binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify it under
-the terms of the GNU General Public License as published by the Free
-Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 2, or (at your option) any later
+   version.
 
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-more details.
+   This program is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+   more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include "dis-asm.h"
 #include "sysdep.h"
@@ -92,56 +93,15 @@ static long no_of_case_offsets = 0;
 /* Candidate for next case_offset.  */
 static long last_immediate = 0;
 
-static int number_of_bits
-  PARAMS ((unsigned int));
-static char *format_hex
-  PARAMS ((unsigned long, char *, struct cris_disasm_data *));
-static char *format_dec
-  PARAMS ((long, char *, int));
-static char *format_reg
-  PARAMS ((struct cris_disasm_data *, int, char *, bfd_boolean));
-static char *format_sup_reg
-  PARAMS ((unsigned int, char *, bfd_boolean));
 static int cris_constraint
-  PARAMS ((const char *, unsigned int, unsigned int,
-	   struct cris_disasm_data *));
-static unsigned bytes_to_skip
-  PARAMS ((unsigned int, const struct cris_opcode *,
-	   enum cris_disass_family));
-static char *print_flags
-  PARAMS ((struct cris_disasm_data *, unsigned int, char *));
-static void print_with_operands
-  PARAMS ((const struct cris_opcode *, unsigned int, unsigned char *,
-	   bfd_vma, disassemble_info *, const struct cris_opcode *,
-	   unsigned int, unsigned char *, bfd_boolean));
-static const struct cris_spec_reg *spec_reg_info
-  PARAMS ((unsigned int, enum cris_disass_family));
-static int print_insn_cris_generic
-  PARAMS ((bfd_vma, disassemble_info *, bfd_boolean));
-static int print_insn_cris_with_register_prefix
-  PARAMS ((bfd_vma, disassemble_info *));
-static int print_insn_cris_without_register_prefix
-  PARAMS ((bfd_vma, disassemble_info *));
-static int print_insn_crisv32_with_register_prefix
-  PARAMS ((bfd_vma, disassemble_info *));
-static int print_insn_crisv32_without_register_prefix
-  PARAMS ((bfd_vma, disassemble_info *));
-static int print_insn_crisv10_v32_with_register_prefix
-  PARAMS ((bfd_vma, disassemble_info *));
-static int print_insn_crisv10_v32_without_register_prefix
-  PARAMS ((bfd_vma, disassemble_info *));
-static bfd_boolean cris_parse_disassembler_options
-  PARAMS ((disassemble_info *, enum cris_disass_family));
-static const struct cris_opcode *get_opcode_entry
-  PARAMS ((unsigned int, unsigned int, struct cris_disasm_data *));
+  (const char *, unsigned, unsigned, struct cris_disasm_data *);
 
 /* Parse disassembler options and store state in info.  FIXME: For the
    time being, we abuse static variables.  */
 
 static bfd_boolean
-cris_parse_disassembler_options (info, distype)
-     disassemble_info *info;
-     enum cris_disass_family distype;
+cris_parse_disassembler_options (disassemble_info *info,
+				 enum cris_disass_family distype)
 {
   struct cris_disasm_data *disdata;
 
@@ -159,13 +119,11 @@ cris_parse_disassembler_options (info, distype)
   return TRUE;
 }
 
-
 static const struct cris_spec_reg *
-spec_reg_info (sreg, distype)
-     unsigned int sreg;
-     enum cris_disass_family distype;
+spec_reg_info (unsigned int sreg, enum cris_disass_family distype)
 {
   int i;
+
   for (i = 0; cris_spec_regs[i].name != NULL; i++)
     {
       if (cris_spec_regs[i].number == sreg)
@@ -196,8 +154,7 @@ spec_reg_info (sreg, distype)
 /* Return the number of bits in the argument.  */
 
 static int
-number_of_bits (val)
-     unsigned int val;
+number_of_bits (unsigned int val)
 {
   int bits;
 
@@ -210,10 +167,9 @@ number_of_bits (val)
 /* Get an entry in the opcode-table.  */
 
 static const struct cris_opcode *
-get_opcode_entry (insn, prefix_insn, disdata)
-     unsigned int insn;
-     unsigned int prefix_insn;
-     struct cris_disasm_data *disdata;
+get_opcode_entry (unsigned int insn,
+		  unsigned int prefix_insn,
+		  struct cris_disasm_data *disdata)
 {
   /* For non-prefixed insns, we keep a table of pointers, indexed by the
      insn code.  Each entry is initialized when found to be NULL.  */
@@ -440,121 +396,21 @@ get_opcode_entry (insn, prefix_insn, disdata)
   return max_matchedp;
 }
 
-/* Format number as hex with a leading "0x" into outbuffer.  */
-
-static char *
-format_hex (number, outbuffer, disdata)
-     unsigned long number;
-     char *outbuffer;
-     struct cris_disasm_data *disdata;
-{
-  /* Truncate negative numbers on >32-bit hosts.  */
-  number &= 0xffffffff;
-
-  sprintf (outbuffer, "0x%lx", number);
-
-  /* Save this value for the "case" support.  */
-  if (TRACE_CASE)
-    last_immediate = number;
-
-  return outbuffer + strlen (outbuffer);
-}
-
-/* Format number as decimal into outbuffer.  Parameter signedp says
-   whether the number should be formatted as signed (!= 0) or
-   unsigned (== 0).  */
-
-static char *
-format_dec (number, outbuffer, signedp)
-     long number;
-     char *outbuffer;
-     int signedp;
-{
-  last_immediate = number;
-  sprintf (outbuffer, signedp ? "%ld" : "%lu", number);
-
-  return outbuffer + strlen (outbuffer);
-}
-
-/* Format the name of the general register regno into outbuffer.  */
-
-static char *
-format_reg (disdata, regno, outbuffer_start, with_reg_prefix)
-     struct cris_disasm_data *disdata;
-     int regno;
-     char *outbuffer_start;
-     bfd_boolean with_reg_prefix;
-{
-  char *outbuffer = outbuffer_start;
-
-  if (with_reg_prefix)
-    *outbuffer++ = REGISTER_PREFIX_CHAR;
-
-  switch (regno)
-    {
-    case 15:
-      /* For v32, there is no context in which we output PC.  */
-      if (disdata->distype == cris_dis_v32)
-	strcpy (outbuffer, "acr");
-      else
-	strcpy (outbuffer, "pc");
-      break;
-
-    case 14:
-      strcpy (outbuffer, "sp");
-      break;
-
-    default:
-      sprintf (outbuffer, "r%d", regno);
-      break;
-    }
-
-  return outbuffer_start + strlen (outbuffer_start);
-}
-
-/* Format the name of a support register into outbuffer.  */
-
-static char *
-format_sup_reg (regno, outbuffer_start, with_reg_prefix)
-     unsigned int regno;
-     char *outbuffer_start;
-     bfd_boolean with_reg_prefix;
-{
-  char *outbuffer = outbuffer_start;
-  int i;
-
-  if (with_reg_prefix)
-    *outbuffer++ = REGISTER_PREFIX_CHAR;
-
-  for (i = 0; cris_support_regs[i].name != NULL; i++)
-    if (cris_support_regs[i].number == regno)
-      {
-	sprintf (outbuffer, "%s", cris_support_regs[i].name);
-	return outbuffer_start + strlen (outbuffer_start);
-      }
-
-  /* There's supposed to be register names covering all numbers, though
-     some may be generic names.  */
-  sprintf (outbuffer, "format_sup_reg-BUG");
-  return outbuffer_start + strlen (outbuffer_start);
-}
-
 /* Return -1 if the constraints of a bitwise-matched instruction say
    that there is no match.  Otherwise return a nonnegative number
    indicating the confidence in the match (higher is better).  */
 
 static int
-cris_constraint (cs, insn, prefix_insn, disdata)
-     const char *cs;
-     unsigned int insn;
-     unsigned int prefix_insn;
-     struct cris_disasm_data *disdata;
+cris_constraint (const char *cs,
+		 unsigned int insn,
+		 unsigned int prefix_insn,
+		 struct cris_disasm_data *disdata)
 {
   int retval = 0;
   int tmp;
   int prefix_ok = 0;
-
   const char *s;
+
   for (s = cs; *s; s++)
     switch (*s)
       {
@@ -697,13 +553,105 @@ cris_constraint (cs, insn, prefix_insn, disdata)
   return retval;
 }
 
+/* Format number as hex with a leading "0x" into outbuffer.  */
+
+static char *
+format_hex (unsigned long number,
+	    char *outbuffer,
+	    struct cris_disasm_data *disdata)
+{
+  /* Truncate negative numbers on >32-bit hosts.  */
+  number &= 0xffffffff;
+
+  sprintf (outbuffer, "0x%lx", number);
+
+  /* Save this value for the "case" support.  */
+  if (TRACE_CASE)
+    last_immediate = number;
+
+  return outbuffer + strlen (outbuffer);
+}
+
+/* Format number as decimal into outbuffer.  Parameter signedp says
+   whether the number should be formatted as signed (!= 0) or
+   unsigned (== 0).  */
+
+static char *
+format_dec (long number, char *outbuffer, int signedp)
+{
+  last_immediate = number;
+  sprintf (outbuffer, signedp ? "%ld" : "%lu", number);
+
+  return outbuffer + strlen (outbuffer);
+}
+
+/* Format the name of the general register regno into outbuffer.  */
+
+static char *
+format_reg (struct cris_disasm_data *disdata,
+	    int regno,
+	    char *outbuffer_start,
+	    bfd_boolean with_reg_prefix)
+{
+  char *outbuffer = outbuffer_start;
+
+  if (with_reg_prefix)
+    *outbuffer++ = REGISTER_PREFIX_CHAR;
+
+  switch (regno)
+    {
+    case 15:
+      /* For v32, there is no context in which we output PC.  */
+      if (disdata->distype == cris_dis_v32)
+	strcpy (outbuffer, "acr");
+      else
+	strcpy (outbuffer, "pc");
+      break;
+
+    case 14:
+      strcpy (outbuffer, "sp");
+      break;
+
+    default:
+      sprintf (outbuffer, "r%d", regno);
+      break;
+    }
+
+  return outbuffer_start + strlen (outbuffer_start);
+}
+
+/* Format the name of a support register into outbuffer.  */
+
+static char *
+format_sup_reg (unsigned int regno,
+		char *outbuffer_start,
+		bfd_boolean with_reg_prefix)
+{
+  char *outbuffer = outbuffer_start;
+  int i;
+
+  if (with_reg_prefix)
+    *outbuffer++ = REGISTER_PREFIX_CHAR;
+
+  for (i = 0; cris_support_regs[i].name != NULL; i++)
+    if (cris_support_regs[i].number == regno)
+      {
+	sprintf (outbuffer, "%s", cris_support_regs[i].name);
+	return outbuffer_start + strlen (outbuffer_start);
+      }
+
+  /* There's supposed to be register names covering all numbers, though
+     some may be generic names.  */
+  sprintf (outbuffer, "format_sup_reg-BUG");
+  return outbuffer_start + strlen (outbuffer_start);
+}
+
 /* Return the length of an instruction.  */
 
 static unsigned
-bytes_to_skip (insn, matchedp, distype)
-     unsigned int insn;
-     const struct cris_opcode *matchedp;
-     enum cris_disass_family distype;
+bytes_to_skip (unsigned int insn,
+	       const struct cris_opcode *matchedp,
+	       enum cris_disass_family distype)
 {
   /* Each insn is a word plus "immediate" operands.  */
   unsigned to_skip = 2;
@@ -750,10 +698,7 @@ bytes_to_skip (insn, matchedp, distype)
 /* Print condition code flags.  */
 
 static char *
-print_flags (disdata, insn, cp)
-     struct cris_disasm_data *disdata;
-     unsigned int insn;
-     char *cp;
+print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp)
 {
   /* Use the v8 (Etrax 100) flag definitions for disassembly.
      The differences with v0 (Etrax 1..4) vs. Svinto are:
@@ -780,20 +725,18 @@ print_flags (disdata, insn, cp)
    supposed to be output as an address mode.  */
 
 static void
-print_with_operands (opcodep, insn, buffer, addr, info, prefix_opcodep,
-		     prefix_insn, prefix_buffer, with_reg_prefix)
-     const struct cris_opcode *opcodep;
-     unsigned int insn;
-     unsigned char *buffer;
-     bfd_vma addr;
-     disassemble_info *info;
-
-     /* If a prefix insn was before this insn (and is supposed to be
-	output as an address), here is a description of it.  */
-     const struct cris_opcode *prefix_opcodep;
-     unsigned int prefix_insn;
-     unsigned char *prefix_buffer;
-     bfd_boolean with_reg_prefix;
+print_with_operands (const struct cris_opcode *opcodep,
+		     unsigned int insn,
+		     unsigned char *buffer,
+		     bfd_vma addr,
+		     disassemble_info *info,
+		     /* If a prefix insn was before this insn (and is supposed
+			to be output as an address), here is a description of
+			it.  */
+		     const struct cris_opcode *prefix_opcodep,
+		     unsigned int prefix_insn,
+		     unsigned char *prefix_buffer,
+		     bfd_boolean with_reg_prefix)
 {
   /* Get a buffer of somewhat reasonable size where we store
      intermediate parts of the insn.  */
@@ -1420,15 +1363,13 @@ print_with_operands (opcodep, insn, buffer, addr, info, prefix_opcodep,
 
       /* It could also be an "add", if there are negative case-values.  */
       else if (strncmp (opcodep->name, "add", 3) == 0)
-	{
-	  /* The first case is the negated operand to the add.  */
-	  case_offset = -last_immediate;
-	}
+	/* The first case is the negated operand to the add.  */
+	case_offset = -last_immediate;
+
       /* A bound insn will tell us the number of cases.  */
       else if (strncmp (opcodep->name, "bound", 5) == 0)
-	{
-	  no_of_case_offsets = last_immediate + 1;
-	}
+	no_of_case_offsets = last_immediate + 1;
+
       /* A jump or jsr or branch breaks the chain of insns for a
 	 case-table, so assume default first-case again.  */
       else if (info->insn_type == dis_jsr
@@ -1444,10 +1385,9 @@ print_with_operands (opcodep, insn, buffer, addr, info, prefix_opcodep,
    WITH_REG_PREFIX.  */
 
 static int
-print_insn_cris_generic (memaddr, info, with_reg_prefix)
-     bfd_vma memaddr;
-     disassemble_info *info;
-     bfd_boolean with_reg_prefix;
+print_insn_cris_generic (bfd_vma memaddr,
+			 disassemble_info *info,
+			 bfd_boolean with_reg_prefix)
 {
   int nbytes;
   unsigned int insn;
@@ -1631,9 +1571,8 @@ print_insn_cris_generic (memaddr, info, with_reg_prefix)
 /* Disassemble, prefixing register names with `$'.  CRIS v0..v10.  */
 
 static int
-print_insn_cris_with_register_prefix (vma, info)
-     bfd_vma vma;
-     disassemble_info *info;
+print_insn_cris_with_register_prefix (bfd_vma vma,
+				      disassemble_info *info)
 {
   if (info->private_data == NULL
       && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
@@ -1644,9 +1583,8 @@ print_insn_cris_with_register_prefix (vma, info)
 /* Disassemble, prefixing register names with `$'.  CRIS v32.  */
 
 static int
-print_insn_crisv32_with_register_prefix (vma, info)
-     bfd_vma vma;
-     disassemble_info *info;
+print_insn_crisv32_with_register_prefix (bfd_vma vma,
+					 disassemble_info *info)
 {
   if (info->private_data == NULL
       && !cris_parse_disassembler_options (info, cris_dis_v32))
@@ -1658,9 +1596,8 @@ print_insn_crisv32_with_register_prefix (vma, info)
    Common v10 and v32 subset.  */
 
 static int
-print_insn_crisv10_v32_with_register_prefix (vma, info)
-     bfd_vma vma;
-     disassemble_info *info;
+print_insn_crisv10_v32_with_register_prefix (bfd_vma vma,
+					     disassemble_info *info)
 {
   if (info->private_data == NULL
       && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
@@ -1671,9 +1608,8 @@ print_insn_crisv10_v32_with_register_prefix (vma, info)
 /* Disassemble, no prefixes on register names.  CRIS v0..v10.  */
 
 static int
-print_insn_cris_without_register_prefix (vma, info)
-     bfd_vma vma;
-     disassemble_info *info;
+print_insn_cris_without_register_prefix (bfd_vma vma,
+					 disassemble_info *info)
 {
   if (info->private_data == NULL
       && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
@@ -1684,9 +1620,8 @@ print_insn_cris_without_register_prefix (vma, info)
 /* Disassemble, no prefixes on register names.  CRIS v32.  */
 
 static int
-print_insn_crisv32_without_register_prefix (vma, info)
-     bfd_vma vma;
-     disassemble_info *info;
+print_insn_crisv32_without_register_prefix (bfd_vma vma,
+					    disassemble_info *info)
 {
   if (info->private_data == NULL
       && !cris_parse_disassembler_options (info, cris_dis_v32))
@@ -1698,9 +1633,8 @@ print_insn_crisv32_without_register_prefix (vma, info)
    Common v10 and v32 subset.  */
 
 static int
-print_insn_crisv10_v32_without_register_prefix (vma, info)
-     bfd_vma vma;
-     disassemble_info *info;
+print_insn_crisv10_v32_without_register_prefix (bfd_vma vma,
+						disassemble_info *info)
 {
   if (info->private_data == NULL
       && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
@@ -1714,8 +1648,7 @@ print_insn_crisv10_v32_without_register_prefix (vma, info)
    functions seen above.  */
 
 disassembler_ftype
-cris_get_disassembler (abfd)
-     bfd *abfd;
+cris_get_disassembler (bfd *abfd)
 {
   /* If there's no bfd in sight, we return what is valid as input in all
      contexts if fed back to the assembler: disassembly *with* register
@@ -1742,9 +1675,7 @@ cris_get_disassembler (abfd)
   return print_insn_cris_without_register_prefix;
 }
 
-/*
- * Local variables:
- * eval: (c-set-style "gnu")
- * indent-tabs-mode: t
- * End:
- */
+/* Local variables:
+   eval: (c-set-style "gnu")
+   indent-tabs-mode: t
+   End:  */
diff --git a/opcodes/d10v-dis.c b/opcodes/d10v-dis.c
index b5f232a..55a3fd6 100644
--- a/opcodes/d10v-dis.c
+++ b/opcodes/d10v-dis.c
@@ -1,19 +1,20 @@
 /* Disassemble D10V instructions.
-   Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 2000, 2001, 2005 Free Software Foundation, Inc.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <stdio.h>
 
@@ -25,57 +26,12 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
    so use this mask to keep the parts we want.  */
 #define PC_MASK	0x0303FFFF
 
-static void dis_2_short PARAMS ((unsigned long insn, bfd_vma memaddr,
-				 struct disassemble_info *info, int order));
-static void dis_long PARAMS ((unsigned long insn, bfd_vma memaddr,
-			      struct disassemble_info *info));
-static void print_operand
-  PARAMS ((struct d10v_operand *, long unsigned int, struct d10v_opcode *,
-	   bfd_vma, struct disassemble_info *));
-
-int
-print_insn_d10v (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
-{
-  int status;
-  bfd_byte buffer[4];
-  unsigned long insn;
-
-  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
-  if (status != 0)
-    {
-      (*info->memory_error_func) (status, memaddr, info);
-      return -1;
-    }
-  insn = bfd_getb32 (buffer);
-
-  status = insn & FM11;
-  switch (status)
-    {
-    case 0:
-      dis_2_short (insn, memaddr, info, 2);
-      break;
-    case FM01:
-      dis_2_short (insn, memaddr, info, 0);
-      break;
-    case FM10:
-      dis_2_short (insn, memaddr, info, 1);
-      break;
-    case FM11:
-      dis_long (insn, memaddr, info);
-      break;
-    }
-  return 4;
-}
-
 static void
-print_operand (oper, insn, op, memaddr, info)
-     struct d10v_operand *oper;
-     unsigned long insn;
-     struct d10v_opcode *op;
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_operand (struct d10v_operand *oper,
+	       unsigned long insn,
+	       struct d10v_opcode *op,
+	       bfd_vma memaddr,
+	       struct disassemble_info *info)
 {
   int num, shift;
 
@@ -117,6 +73,7 @@ print_operand (oper, insn, op, memaddr, info)
     {
       int i;
       int match = 0;
+
       num += (oper->flags
 	      & (OPERAND_GPR | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL));
       if (oper->flags & (OPERAND_ACC0 | OPERAND_ACC1))
@@ -155,6 +112,7 @@ print_operand (oper, insn, op, memaddr, info)
 	{
 	  long max;
 	  int neg = 0;
+
 	  max = (1 << (oper->bits - 1));
 	  if (num & max)
 	    {
@@ -189,10 +147,9 @@ print_operand (oper, insn, op, memaddr, info)
 }
 
 static void
-dis_long (insn, memaddr, info)
-     unsigned long insn;
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+dis_long (unsigned long insn,
+	  bfd_vma memaddr,
+	  struct disassemble_info *info)
 {
   int i;
   struct d10v_opcode *op = (struct d10v_opcode *) d10v_opcodes;
@@ -202,10 +159,12 @@ dis_long (insn, memaddr, info)
 
   while (op->name)
     {
-      if ((op->format & LONG_OPCODE) && ((op->mask & insn) == (unsigned long) op->opcode))
+      if ((op->format & LONG_OPCODE)
+	  && ((op->mask & insn) == (unsigned long) op->opcode))
 	{
 	  match = 1;
 	  (*info->fprintf_func) (info->stream, "%s\t", op->name);
+
 	  for (i = 0; op->operands[i]; i++)
 	    {
 	      oper = (struct d10v_operand *) &d10v_operands[op->operands[i]];
@@ -230,11 +189,10 @@ dis_long (insn, memaddr, info)
 }
 
 static void
-dis_2_short (insn, memaddr, info, order)
-     unsigned long insn;
-     bfd_vma memaddr;
-     struct disassemble_info *info;
-     int order;
+dis_2_short (unsigned long insn,
+	     bfd_vma memaddr,
+	     struct disassemble_info *info,
+	     int order)
 {
   int i, j;
   unsigned int ins[2];
@@ -302,3 +260,37 @@ dis_2_short (insn, memaddr, info, order)
   if (need_paren)
     (*info->fprintf_func) (info->stream, ")");
 }
+
+int
+print_insn_d10v (bfd_vma memaddr, struct disassemble_info *info)
+{
+  int status;
+  bfd_byte buffer[4];
+  unsigned long insn;
+
+  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, memaddr, info);
+      return -1;
+    }
+  insn = bfd_getb32 (buffer);
+
+  status = insn & FM11;
+  switch (status)
+    {
+    case 0:
+      dis_2_short (insn, memaddr, info, 2);
+      break;
+    case FM01:
+      dis_2_short (insn, memaddr, info, 0);
+      break;
+    case FM10:
+      dis_2_short (insn, memaddr, info, 1);
+      break;
+    case FM11:
+      dis_long (insn, memaddr, info);
+      break;
+    }
+  return 4;
+}
diff --git a/opcodes/d30v-dis.c b/opcodes/d30v-dis.c
index d286e7b..c7385d9 100644
--- a/opcodes/d30v-dis.c
+++ b/opcodes/d30v-dis.c
@@ -1,19 +1,20 @@
 /* Disassemble D30V instructions.
-   Copyright 1997, 1998, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1997, 1998, 2000, 2001, 2005 Free Software Foundation, Inc.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "sysdep.h"
@@ -23,100 +24,12 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 #define PC_MASK 0xFFFFFFFF
 
-static int lookup_opcode PARAMS ((struct d30v_insn *insn, long num, int is_long));
-static void print_insn PARAMS ((struct disassemble_info *info, bfd_vma memaddr, long long num,
-				 struct d30v_insn *insn, int is_long, int show_ext));
-static int extract_value PARAMS ((long long num, struct d30v_operand *oper, int is_long));
-
-int
-print_insn_d30v (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
-{
-  int status, result;
-  bfd_byte buffer[12];
-  unsigned long in1, in2;
-  struct d30v_insn insn;
-  long long num;
-
-  insn.form = (struct d30v_format *) NULL;
-
-  info->bytes_per_line = 8;
-  info->bytes_per_chunk = 4;
-  info->display_endian = BFD_ENDIAN_BIG;
-
-  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
-  if (status != 0)
-    {
-      (*info->memory_error_func) (status, memaddr, info);
-      return -1;
-    }
-  in1 = bfd_getb32 (buffer);
-
-  status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
-  if (status != 0)
-    {
-      info->bytes_per_line = 8;
-      if (!(result = lookup_opcode (&insn, in1, 0)))
-	(*info->fprintf_func) (info->stream, ".long\t0x%x", in1);
-      else
-	print_insn (info, memaddr, (long long) in1, &insn, 0, result);
-      return 4;
-    }
-  in2 = bfd_getb32 (buffer);
-
-  if (in1 & in2 & FM01)
-    {
-      /* LONG instruction.  */
-      if (!(result = lookup_opcode (&insn, in1, 1)))
-	{
-	  (*info->fprintf_func) (info->stream, ".long\t0x%x,0x%x", in1, in2);
-	  return 8;
-	}
-      num = (long long) in1 << 32 | in2;
-      print_insn (info, memaddr, num, &insn, 1, result);
-    }
-  else
-    {
-      num = in1;
-      if (!(result = lookup_opcode (&insn, in1, 0)))
-	(*info->fprintf_func) (info->stream, ".long\t0x%x", in1);
-      else
-	print_insn (info, memaddr, num, &insn, 0, result);
-
-      switch (((in1 >> 31) << 1) | (in2 >> 31))
-	{
-	case 0:
-	  (*info->fprintf_func) (info->stream, "\t||\t");
-	  break;
-	case 1:
-	  (*info->fprintf_func) (info->stream, "\t->\t");
-	  break;
-	case 2:
-	  (*info->fprintf_func) (info->stream, "\t<-\t");
-	default:
-	  break;
-	}
-
-      insn.form = (struct d30v_format *) NULL;
-      num = in2;
-      if (!(result = lookup_opcode (&insn, in2, 0)))
-	(*info->fprintf_func) (info->stream, ".long\t0x%x", in2);
-      else
-	print_insn (info, memaddr, num, &insn, 0, result);
-    }
-  return 8;
-}
-
 /* Return 0 if lookup fails,
    1 if found and only one form,
    2 if found and there are short and long forms.  */
 
 static int
-lookup_opcode (insn, num, is_long)
-     struct d30v_insn *insn;
-     long num;
-     int is_long;
+lookup_opcode (struct d30v_insn *insn, long num, int is_long)
 {
   int i = 0, index;
   struct d30v_format *f;
@@ -173,14 +86,39 @@ lookup_opcode (insn, num, is_long)
     return 1;
 }
 
+static int
+extract_value (long long num, struct d30v_operand *oper, int is_long)
+{
+  int val;
+  int shift = 12 - oper->position;
+  int mask = (0xFFFFFFFF >> (32 - oper->bits));
+
+  if (is_long)
+    {
+      if (oper->bits == 32)
+	/* Piece together 32-bit constant.  */
+	val = ((num & 0x3FFFF)
+	       | ((num & 0xFF00000) >> 2)
+	       | ((num & 0x3F00000000LL) >> 6));
+      else
+	val = (num >> (32 + shift)) & mask;
+    }
+  else
+    val = (num >> shift) & mask;
+
+  if (oper->flags & OPERAND_SHIFT)
+    val <<= 3;
+
+  return val;
+}
+
 static void
-print_insn (info, memaddr, num, insn, is_long, show_ext)
-     struct disassemble_info *info;
-     bfd_vma memaddr;
-     long long num;
-     struct d30v_insn *insn;
-     int is_long;
-     int show_ext;
+print_insn (struct disassemble_info *info,
+	    bfd_vma memaddr,
+	    long long num,
+	    struct d30v_insn *insn,
+	    int is_long,
+	    int show_ext)
 {
   int val, opnum, need_comma = 0;
   struct d30v_operand *oper;
@@ -216,6 +154,7 @@ print_insn (info, memaddr, num, insn, is_long, show_ext)
   while ((opnum = insn->form->operands[opind++]) != 0)
     {
       int bits;
+
       oper = (struct d30v_operand *) &d30v_operand_table[opnum];
       bits = oper->bits;
       if (oper->flags & OPERAND_SHIFT)
@@ -269,6 +208,7 @@ print_insn (info, memaddr, num, insn, is_long, show_ext)
 	      struct d30v_operand *oper3 =
 		(struct d30v_operand *) &d30v_operand_table[insn->form->operands[2]];
 	      int id = extract_value (num, oper3, is_long);
+
 	      found_control = 1;
 	      switch (id)
 		{
@@ -357,6 +297,7 @@ print_insn (info, memaddr, num, insn, is_long, show_ext)
 	  if (oper->flags & OPERAND_SIGNED)
 	    {
 	      int max = (1 << (bits - 1));
+
 	      if (val & max)
 		{
 		  val = -val;
@@ -375,33 +316,80 @@ print_insn (info, memaddr, num, insn, is_long, show_ext)
     (*info->fprintf_func) (info->stream, ")");
 }
 
-static int
-extract_value (num, oper, is_long)
-     long long num;
-     struct d30v_operand *oper;
-     int is_long;
+int
+print_insn_d30v (bfd_vma memaddr, struct disassemble_info *info)
 {
-  int val;
-  int shift = 12 - oper->position;
-  int mask = (0xFFFFFFFF >> (32 - oper->bits));
+  int status, result;
+  bfd_byte buffer[12];
+  unsigned long in1, in2;
+  struct d30v_insn insn;
+  long long num;
 
-  if (is_long)
+  insn.form = NULL;
+
+  info->bytes_per_line = 8;
+  info->bytes_per_chunk = 4;
+  info->display_endian = BFD_ENDIAN_BIG;
+
+  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
+  if (status != 0)
     {
-      if (oper->bits == 32)
+      (*info->memory_error_func) (status, memaddr, info);
+      return -1;
+    }
+  in1 = bfd_getb32 (buffer);
+
+  status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
+  if (status != 0)
+    {
+      info->bytes_per_line = 8;
+      if (!(result = lookup_opcode (&insn, in1, 0)))
+	(*info->fprintf_func) (info->stream, ".long\t0x%x", in1);
+      else
+	print_insn (info, memaddr, (long long) in1, &insn, 0, result);
+      return 4;
+    }
+  in2 = bfd_getb32 (buffer);
+
+  if (in1 & in2 & FM01)
+    {
+      /* LONG instruction.  */
+      if (!(result = lookup_opcode (&insn, in1, 1)))
 	{
-	  /* Piece together 32-bit constant.  */
-	  val = ((num & 0x3FFFF)
-		 | ((num & 0xFF00000) >> 2)
-		 | ((num & 0x3F00000000LL) >> 6));
+	  (*info->fprintf_func) (info->stream, ".long\t0x%x,0x%x", in1, in2);
+	  return 8;
 	}
-      else
-	val = (num >> (32 + shift)) & mask;
+      num = (long long) in1 << 32 | in2;
+      print_insn (info, memaddr, num, &insn, 1, result);
     }
   else
-    val = (num >> shift) & mask;
+    {
+      num = in1;
+      if (!(result = lookup_opcode (&insn, in1, 0)))
+	(*info->fprintf_func) (info->stream, ".long\t0x%x", in1);
+      else
+	print_insn (info, memaddr, num, &insn, 0, result);
 
-  if (oper->flags & OPERAND_SHIFT)
-    val <<= 3;
+      switch (((in1 >> 31) << 1) | (in2 >> 31))
+	{
+	case 0:
+	  (*info->fprintf_func) (info->stream, "\t||\t");
+	  break;
+	case 1:
+	  (*info->fprintf_func) (info->stream, "\t->\t");
+	  break;
+	case 2:
+	  (*info->fprintf_func) (info->stream, "\t<-\t");
+	default:
+	  break;
+	}
 
-  return val;
+      insn.form = NULL;
+      num = in2;
+      if (!(result = lookup_opcode (&insn, in2, 0)))
+	(*info->fprintf_func) (info->stream, ".long\t0x%x", in2);
+      else
+	print_insn (info, memaddr, num, &insn, 0, result);
+    }
+  return 8;
 }
diff --git a/opcodes/d30v-opc.c b/opcodes/d30v-opc.c
index 60353fe..ecdb060 100644
--- a/opcodes/d30v-opc.c
+++ b/opcodes/d30v-opc.c
@@ -1,125 +1,126 @@
 /* d30v-opc.c -- D30V opcode list
-   Copyright 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1997, 1998, 1999, 2000, 2005 Free Software Foundation, Inc.
    Written by Martin Hunt, Cygnus Support
 
-This file is part of GDB, GAS, and the GNU binutils.
+   This file is part of GDB, GAS, and the GNU binutils.
 
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-2, or (at your option) any later version.
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
 
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
-the GNU General Public License for more details.
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING.  If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "sysdep.h"
 #include "opcode/d30v.h"
 
-/* This table is sorted. */
-/* If you add anything, it MUST be in alphabetical order */
-/* The first field is the name the assembler uses when looking */
-/* up orcodes.  The second field is the name the disassembler will use. */
-/* This allows the assembler to assemble references to r63 (for example) */
-/* or "sp".  The disassembler will always use the preferred form (sp) */
+/* This table is sorted.
+   If you add anything, it MUST be in alphabetical order.
+   The first field is the name the assembler uses when looking
+   up orcodes.  The second field is the name the disassembler will use.
+   This allows the assembler to assemble references to r63 (for example)
+   or "sp".  The disassembler will always use the preferred form (sp).  */
 const struct pd_reg pre_defined_registers[] =
 {
-  { "a0", NULL, OPERAND_ACC+0 },
-  { "a1", NULL, OPERAND_ACC+1 },
-  { "bpc", NULL, OPERAND_CONTROL+3 },
-  { "bpsw", NULL, OPERAND_CONTROL+1 },
-  { "c", "c", OPERAND_FLAG+7 },
+  { "a0", NULL, OPERAND_ACC + 0 },
+  { "a1", NULL, OPERAND_ACC + 1 },
+  { "bpc", NULL, OPERAND_CONTROL + 3 },
+  { "bpsw", NULL, OPERAND_CONTROL + 1 },
+  { "c", "c", OPERAND_FLAG + 7 },
   { "cr0", "psw", OPERAND_CONTROL },
-  { "cr1", "bpsw", OPERAND_CONTROL+1 },
-  { "cr10", "mod_s", OPERAND_CONTROL+10 },
-  { "cr11", "mod_e", OPERAND_CONTROL+11 },
-  { "cr12", NULL, OPERAND_CONTROL+12 },
-  { "cr13", NULL, OPERAND_CONTROL+13 },
-  { "cr14", "iba", OPERAND_CONTROL+14 },
-  { "cr15", "eit_vb", OPERAND_CONTROL+15 },
-  { "cr16", "int_s", OPERAND_CONTROL+16 },
-  { "cr17", "int_m", OPERAND_CONTROL+17 },
-  { "cr18", NULL, OPERAND_CONTROL+18 },
-  { "cr19", NULL, OPERAND_CONTROL+19 },
-  { "cr2", "pc", OPERAND_CONTROL+2 },
-  { "cr20", NULL, OPERAND_CONTROL+20 },
-  { "cr21", NULL, OPERAND_CONTROL+21 },
-  { "cr22", NULL, OPERAND_CONTROL+22 },
-  { "cr23", NULL, OPERAND_CONTROL+23 },
-  { "cr24", NULL, OPERAND_CONTROL+24 },
-  { "cr25", NULL, OPERAND_CONTROL+25 },
-  { "cr26", NULL, OPERAND_CONTROL+26 },
-  { "cr27", NULL, OPERAND_CONTROL+27 },
-  { "cr28", NULL, OPERAND_CONTROL+28 },
-  { "cr29", NULL, OPERAND_CONTROL+29 },
-  { "cr3", "bpc", OPERAND_CONTROL+3 },
-  { "cr30", NULL, OPERAND_CONTROL+30 },
-  { "cr31", NULL, OPERAND_CONTROL+31 },
-  { "cr32", NULL, OPERAND_CONTROL+32 },
-  { "cr33", NULL, OPERAND_CONTROL+33 },
-  { "cr34", NULL, OPERAND_CONTROL+34 },
-  { "cr35", NULL, OPERAND_CONTROL+35 },
-  { "cr36", NULL, OPERAND_CONTROL+36 },
-  { "cr37", NULL, OPERAND_CONTROL+37 },
-  { "cr38", NULL, OPERAND_CONTROL+38 },
-  { "cr39", NULL, OPERAND_CONTROL+39 },
-  { "cr4", "dpsw", OPERAND_CONTROL+4 },
-  { "cr40", NULL, OPERAND_CONTROL+40 },
-  { "cr41", NULL, OPERAND_CONTROL+41 },
-  { "cr42", NULL, OPERAND_CONTROL+42 },
-  { "cr43", NULL, OPERAND_CONTROL+43 },
-  { "cr44", NULL, OPERAND_CONTROL+44 },
-  { "cr45", NULL, OPERAND_CONTROL+45 },
-  { "cr46", NULL, OPERAND_CONTROL+46 },
-  { "cr47", NULL, OPERAND_CONTROL+47 },
-  { "cr48", NULL, OPERAND_CONTROL+48 },
-  { "cr49", NULL, OPERAND_CONTROL+49 },
-  { "cr5","dpc", OPERAND_CONTROL+5 },
-  { "cr50", NULL, OPERAND_CONTROL+50 },
-  { "cr51", NULL, OPERAND_CONTROL+51 },
-  { "cr52", NULL, OPERAND_CONTROL+52 },
-  { "cr53", NULL, OPERAND_CONTROL+53 },
-  { "cr54", NULL, OPERAND_CONTROL+54 },
-  { "cr55", NULL, OPERAND_CONTROL+55 },
-  { "cr56", NULL, OPERAND_CONTROL+56 },
-  { "cr57", NULL, OPERAND_CONTROL+57 },
-  { "cr58", NULL, OPERAND_CONTROL+58 },
-  { "cr59", NULL, OPERAND_CONTROL+59 },
-  { "cr6", NULL, OPERAND_CONTROL+6 },
-  { "cr60", NULL, OPERAND_CONTROL+60 },
-  { "cr61", NULL, OPERAND_CONTROL+61 },
-  { "cr62", NULL, OPERAND_CONTROL+62 },
-  { "cr63", NULL, OPERAND_CONTROL+63 },
-  { "cr7", "rpt_c", OPERAND_CONTROL+7 },
-  { "cr8", "rpt_s", OPERAND_CONTROL+8 },
-  { "cr9", "rpt_e", OPERAND_CONTROL+9 },
-  { "dpc", NULL, OPERAND_CONTROL+5 },
-  { "dpsw", NULL, OPERAND_CONTROL+4 },
-  { "eit_vb", NULL, OPERAND_CONTROL+15 },
-  { "f0", NULL, OPERAND_FLAG+0 },
-  { "f1", NULL, OPERAND_FLAG+1 },
-  { "f2", NULL, OPERAND_FLAG+2 },
-  { "f3", NULL, OPERAND_FLAG+3 },
-  { "f4", "s", OPERAND_FLAG+4 },
-  { "f5", "v", OPERAND_FLAG+5 },
-  { "f6", "va", OPERAND_FLAG+6 },
-  { "f7", "c", OPERAND_FLAG+7 },
-  { "iba", NULL, OPERAND_CONTROL+14 },
-  { "int_m", NULL, OPERAND_CONTROL+17 },
-  { "int_s", NULL, OPERAND_CONTROL+16 },
+  { "cr1", "bpsw", OPERAND_CONTROL + 1 },
+  { "cr10", "mod_s", OPERAND_CONTROL + 10 },
+  { "cr11", "mod_e", OPERAND_CONTROL + 11 },
+  { "cr12", NULL, OPERAND_CONTROL + 12 },
+  { "cr13", NULL, OPERAND_CONTROL + 13 },
+  { "cr14", "iba", OPERAND_CONTROL + 14 },
+  { "cr15", "eit_vb", OPERAND_CONTROL + 15 },
+  { "cr16", "int_s", OPERAND_CONTROL + 16 },
+  { "cr17", "int_m", OPERAND_CONTROL + 17 },
+  { "cr18", NULL, OPERAND_CONTROL + 18 },
+  { "cr19", NULL, OPERAND_CONTROL + 19 },
+  { "cr2", "pc", OPERAND_CONTROL + 2 },
+  { "cr20", NULL, OPERAND_CONTROL + 20 },
+  { "cr21", NULL, OPERAND_CONTROL + 21 },
+  { "cr22", NULL, OPERAND_CONTROL + 22 },
+  { "cr23", NULL, OPERAND_CONTROL + 23 },
+  { "cr24", NULL, OPERAND_CONTROL + 24 },
+  { "cr25", NULL, OPERAND_CONTROL + 25 },
+  { "cr26", NULL, OPERAND_CONTROL + 26 },
+  { "cr27", NULL, OPERAND_CONTROL + 27 },
+  { "cr28", NULL, OPERAND_CONTROL + 28 },
+  { "cr29", NULL, OPERAND_CONTROL + 29 },
+  { "cr3", "bpc", OPERAND_CONTROL + 3 },
+  { "cr30", NULL, OPERAND_CONTROL + 30 },
+  { "cr31", NULL, OPERAND_CONTROL + 31 },
+  { "cr32", NULL, OPERAND_CONTROL + 32 },
+  { "cr33", NULL, OPERAND_CONTROL + 33 },
+  { "cr34", NULL, OPERAND_CONTROL + 34 },
+  { "cr35", NULL, OPERAND_CONTROL + 35 },
+  { "cr36", NULL, OPERAND_CONTROL + 36 },
+  { "cr37", NULL, OPERAND_CONTROL + 37 },
+  { "cr38", NULL, OPERAND_CONTROL + 38 },
+  { "cr39", NULL, OPERAND_CONTROL + 39 },
+  { "cr4", "dpsw", OPERAND_CONTROL + 4 },
+  { "cr40", NULL, OPERAND_CONTROL + 40 },
+  { "cr41", NULL, OPERAND_CONTROL + 41 },
+  { "cr42", NULL, OPERAND_CONTROL + 42 },
+  { "cr43", NULL, OPERAND_CONTROL + 43 },
+  { "cr44", NULL, OPERAND_CONTROL + 44 },
+  { "cr45", NULL, OPERAND_CONTROL + 45 },
+  { "cr46", NULL, OPERAND_CONTROL + 46 },
+  { "cr47", NULL, OPERAND_CONTROL + 47 },
+  { "cr48", NULL, OPERAND_CONTROL + 48 },
+  { "cr49", NULL, OPERAND_CONTROL + 49 },
+  { "cr5","dpc", OPERAND_CONTROL + 5 },
+  { "cr50", NULL, OPERAND_CONTROL + 50 },
+  { "cr51", NULL, OPERAND_CONTROL + 51 },
+  { "cr52", NULL, OPERAND_CONTROL + 52 },
+  { "cr53", NULL, OPERAND_CONTROL + 53 },
+  { "cr54", NULL, OPERAND_CONTROL + 54 },
+  { "cr55", NULL, OPERAND_CONTROL + 55 },
+  { "cr56", NULL, OPERAND_CONTROL + 56 },
+  { "cr57", NULL, OPERAND_CONTROL + 57 },
+  { "cr58", NULL, OPERAND_CONTROL + 58 },
+  { "cr59", NULL, OPERAND_CONTROL + 59 },
+  { "cr6", NULL, OPERAND_CONTROL + 6 },
+  { "cr60", NULL, OPERAND_CONTROL + 60 },
+  { "cr61", NULL, OPERAND_CONTROL + 61 },
+  { "cr62", NULL, OPERAND_CONTROL + 62 },
+  { "cr63", NULL, OPERAND_CONTROL + 63 },
+  { "cr7", "rpt_c", OPERAND_CONTROL + 7 },
+  { "cr8", "rpt_s", OPERAND_CONTROL + 8 },
+  { "cr9", "rpt_e", OPERAND_CONTROL + 9 },
+  { "dpc", NULL, OPERAND_CONTROL + 5 },
+  { "dpsw", NULL, OPERAND_CONTROL + 4 },
+  { "eit_vb", NULL, OPERAND_CONTROL + 15 },
+  { "f0", NULL, OPERAND_FLAG + 0 },
+  { "f1", NULL, OPERAND_FLAG + 1 },
+  { "f2", NULL, OPERAND_FLAG + 2 },
+  { "f3", NULL, OPERAND_FLAG + 3 },
+  { "f4", "s", OPERAND_FLAG + 4 },
+  { "f5", "v", OPERAND_FLAG + 5 },
+  { "f6", "va", OPERAND_FLAG + 6 },
+  { "f7", "c", OPERAND_FLAG + 7 },
+  { "iba", NULL, OPERAND_CONTROL + 14 },
+  { "int_m", NULL, OPERAND_CONTROL + 17 },
+  { "int_s", NULL, OPERAND_CONTROL + 16 },
   { "link", "r62", 62 },
-  { "mod_e", NULL, OPERAND_CONTROL+11 },
-  { "mod_s", NULL, OPERAND_CONTROL+10 },
-  { "pc", NULL, OPERAND_CONTROL+2 },
+  { "mod_e", NULL, OPERAND_CONTROL + 11 },
+  { "mod_s", NULL, OPERAND_CONTROL + 10 },
+  { "pc", NULL, OPERAND_CONTROL + 2 },
   { "psw", NULL, OPERAND_CONTROL },
-  { "pswh", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+2 },
-  { "pswl", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+1 },
+  { "pswh", NULL, OPERAND_CONTROL + MAX_CONTROL_REG + 2 },
+  { "pswl", NULL, OPERAND_CONTROL + MAX_CONTROL_REG + 1 },
   { "r0", NULL, 0 },
   { "r1", NULL, 1 },
   { "r10", NULL, 10 },
@@ -184,24 +185,26 @@ const struct pd_reg pre_defined_registers[] =
   { "r7", NULL, 7 },
   { "r8", NULL, 8 },
   { "r9", NULL, 9 },
-  { "rpt_c", NULL, OPERAND_CONTROL+7 },
-  { "rpt_e", NULL, OPERAND_CONTROL+9 },
-  { "rpt_s", NULL, OPERAND_CONTROL+8 },
-  { "s", NULL, OPERAND_FLAG+4 },
+  { "rpt_c", NULL, OPERAND_CONTROL + 7 },
+  { "rpt_e", NULL, OPERAND_CONTROL + 9 },
+  { "rpt_s", NULL, OPERAND_CONTROL + 8 },
+  { "s", NULL, OPERAND_FLAG + 4 },
   { "sp", NULL, 63 },
-  { "v", NULL, OPERAND_FLAG+5 },
-  { "va", NULL, OPERAND_FLAG+6 },
+  { "v", NULL, OPERAND_FLAG + 5 },
+  { "va", NULL, OPERAND_FLAG + 6 },
 };
 
 int 
-reg_name_cnt()
+reg_name_cnt (void)
 {
-  return (sizeof(pre_defined_registers) / sizeof(struct pd_reg));
+  return sizeof (pre_defined_registers) / sizeof (struct pd_reg);
 }
 
-/* OPCODE TABLE */
-/* The format of this table is defined in opcode/d30v.h */
-const struct d30v_opcode d30v_opcode_table[] = {
+/* OPCODE TABLE.
+   The format of this table is defined in opcode/d30v.h.  */
+
+const struct d30v_opcode d30v_opcode_table[] =
+{
   { "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 },
   { "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
   { "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
@@ -335,52 +338,53 @@ const struct d30v_opcode d30v_opcode_table[] = {
 };
 
 
-/* now define the operand types */
-/* format is length, bits, position, flags */
+/* Now define the operand types.
+   Format is length, bits, position, flags.  */
+
 const struct d30v_operand d30v_operand_table[] =
 {
 #define UNUSED	(0)
   { 0, 0, 0, 0 },
 #define Ra	(UNUSED + 1)
-  { 6, 6, 0, OPERAND_REG|OPERAND_DEST },
+  { 6, 6, 0, OPERAND_REG | OPERAND_DEST },
 #define Ra2	(Ra + 1)
-  { 6, 6, 0, OPERAND_REG|OPERAND_DEST|OPERAND_2REG },
+  { 6, 6, 0, OPERAND_REG | OPERAND_DEST | OPERAND_2REG },
 #define Ra3	(Ra2 + 1)
   { 6, 6, 0, OPERAND_REG },
 #define Rb	(Ra3 + 1)
   { 6, 6, 6, OPERAND_REG },
 #define Rb2	(Rb + 1)
-  { 6, 6, 6, OPERAND_REG|OPERAND_DEST },
+  { 6, 6, 6, OPERAND_REG | OPERAND_DEST },
 #define Rc	(Rb2 + 1)
   { 6, 6, 12, OPERAND_REG },
 #define Aa	(Rc + 1)
-  { 6, 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST },
+  { 6, 1, 0, OPERAND_ACC | OPERAND_REG | OPERAND_DEST },
 #define Ab	(Aa + 1)
-  { 6, 1, 6, OPERAND_ACC|OPERAND_REG },
+  { 6, 1, 6, OPERAND_ACC | OPERAND_REG },
 #define IMM5	(Ab + 1)
   { 6, 5, 12, OPERAND_NUM },
 #define IMM5U (IMM5 + 1)
-  { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, /* not used */
+  { 6, 5, 12, OPERAND_NUM | OPERAND_SIGNED }, /* Not used.  */
 #define IMM5S3        (IMM5U + 1)
-  { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, /* not used */
+  { 6, 5, 12, OPERAND_NUM | OPERAND_SIGNED }, /* Not used.  */
 #define IMM6  (IMM5S3 + 1)
-  { 6, 6, 12, OPERAND_NUM|OPERAND_SIGNED },
+  { 6, 6, 12, OPERAND_NUM | OPERAND_SIGNED },
 #define IMM6U (IMM6 + 1)
   { 6, 6, 0, OPERAND_NUM },
 #define IMM6U2        (IMM6U + 1)
   { 6, 6, 12, OPERAND_NUM },
 #define REL6S3        (IMM6U2 + 1)
-  { 6, 6, 0, OPERAND_NUM|OPERAND_SHIFT|OPERAND_PCREL },
+  { 6, 6, 0, OPERAND_NUM | OPERAND_SHIFT | OPERAND_PCREL },
 #define REL12S3       (REL6S3 + 1)
-  { 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT|OPERAND_PCREL },
+  { 12, 12, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT | OPERAND_PCREL },
 #define IMM12S3       (REL12S3 + 1)
-  { 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
+  { 12, 12, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT },
 #define REL18S3       (IMM12S3 + 1)
-  { 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT|OPERAND_PCREL },
+  { 18, 18, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT | OPERAND_PCREL },
 #define IMM18S3       (REL18S3 + 1)
-  { 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
+  { 18, 18, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT },
 #define REL32 (IMM18S3 + 1)
-  { 32, 32, 0, OPERAND_NUM|OPERAND_PCREL },
+  { 32, 32, 0, OPERAND_NUM | OPERAND_PCREL },
 #define IMM32 (REL32 + 1)
   { 32, 32, 0, OPERAND_NUM },
 #define Fa	(IMM32 + 1)
@@ -393,25 +397,26 @@ const struct d30v_operand d30v_operand_table[] =
   { 0, 0, 0, OPERAND_ATSIGN},
 #define ATPAR	(ATSIGN + 1)	/* "@(" */
   { 0, 0, 0, OPERAND_ATPAR},
-#define PLUS	(ATPAR + 1)	/* postincrement */
+#define PLUS	(ATPAR + 1)	/* Postincrement.  */
   { 0, 0, 0, OPERAND_PLUS},
-#define MINUS	(PLUS + 1)	/* postdecrement */
+#define MINUS	(PLUS + 1)	/* Postdecrement.  */
   { 0, 0, 0, OPERAND_MINUS},
-#define ATMINUS	(MINUS + 1)	/* predecrement */
+#define ATMINUS	(MINUS + 1)	/* Predecrement.  */
   { 0, 0, 0, OPERAND_ATMINUS},
-#define Ca	(ATMINUS + 1)	/* control register */
-  { 6, 6, 0, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST},
-#define Cb	(Ca + 1)	/* control register */
-  { 6, 6, 6, OPERAND_REG|OPERAND_CONTROL},
-#define CC	(Cb + 1)	/* condition code (CMPcc and CMPUcc) */
+#define Ca	(ATMINUS + 1)	/* Control register.  */
+  { 6, 6, 0, OPERAND_REG | OPERAND_CONTROL | OPERAND_DEST},
+#define Cb	(Ca + 1)	/* Control register.  */
+  { 6, 6, 6, OPERAND_REG | OPERAND_CONTROL},
+#define CC	(Cb + 1)	/* Condition code (CMPcc and CMPUcc).  */
   { 3, 3, -3, OPERAND_NAME},
-#define Fa2	(CC + 1)	/* flag register (CMPcc and CMPUcc) */
-  { 3, 3, 0, OPERAND_REG|OPERAND_FLAG|OPERAND_DEST},
-#define Fake	(Fa2 + 1)	/* place holder for "id" field in mvfsys and mvtsys */
+#define Fa2	(CC + 1)	/* Flag register (CMPcc and CMPUcc).  */
+  { 3, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST},
+#define Fake	(Fa2 + 1)	/* Place holder for "id" field in mvfsys and mvtsys.  */
   { 6, 2, 12, OPERAND_SPECIAL},
 };
 
-/* now we need to define the instruction formats */
+/* Now we need to define the instruction formats.  */
+
 const struct d30v_format d30v_format_table[] =
 {
   { 0, 0, { 0 } },
diff --git a/opcodes/dis-buf.c b/opcodes/dis-buf.c
index b87aeda..c2589ba 100644
--- a/opcodes/dis-buf.c
+++ b/opcodes/dis-buf.c
@@ -2,19 +2,20 @@
    Copyright 1993, 1994, 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2005
    Free Software Foundation, Inc.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include "sysdep.h"
 #include "dis-asm.h"
@@ -24,11 +25,10 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 /* Get LENGTH bytes from info's buffer, at target address memaddr.
    Transfer them to myaddr.  */
 int
-buffer_read_memory (memaddr, myaddr, length, info)
-     bfd_vma memaddr;
-     bfd_byte *myaddr;
-     unsigned int length;
-     struct disassemble_info *info;
+buffer_read_memory (bfd_vma memaddr,
+		    bfd_byte *myaddr,
+		    unsigned int length,
+		    struct disassemble_info *info)
 {
   unsigned int opb = info->octets_per_byte;
   unsigned int end_addr_offset = length / opb;
@@ -46,11 +46,11 @@ buffer_read_memory (memaddr, myaddr, length, info)
 
 /* Print an error message.  We can assume that this is in response to
    an error return from buffer_read_memory.  */
+
 void
-perror_memory (status, memaddr, info)
-     int status;
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+perror_memory (int status,
+	       bfd_vma memaddr,
+	       struct disassemble_info *info)
 {
   if (status != EIO)
     /* Can't happen.  */
@@ -75,9 +75,7 @@ perror_memory (status, memaddr, info)
    addresses).  */
 
 void
-generic_print_address (addr, info)
-     bfd_vma addr;
-     struct disassemble_info *info;
+generic_print_address (bfd_vma addr, struct disassemble_info *info)
 {
   char buf[30];
 
@@ -85,39 +83,11 @@ generic_print_address (addr, info)
   (*info->fprintf_func) (info->stream, "0x%s", buf);
 }
 
-#if 0
-/* Just concatenate the address as hex.  This is included for
-   completeness even though both GDB and objdump provide their own (to
-   print symbolic addresses).  */
-
-void generic_strcat_address PARAMS ((bfd_vma, char *, int));
-
-void
-generic_strcat_address (addr, buf, len)
-     bfd_vma addr;
-     char *buf;
-     int len;
-{
-  if (buf != (char *)NULL && len > 0)
-    {
-      char tmpBuf[30];
-
-      sprintf_vma (tmpBuf, addr);
-      if ((strlen (buf) + strlen (tmpBuf)) <= (unsigned int) len)
-	strcat (buf, tmpBuf);
-      else
-	strncat (buf, tmpBuf, (len - strlen(buf)));
-    }
-  return;
-}
-#endif
-
 /* Just return true.  */
 
 int
-generic_symbol_at_address (addr, info)
-     bfd_vma addr ATTRIBUTE_UNUSED;
-     struct disassemble_info *info ATTRIBUTE_UNUSED;
+generic_symbol_at_address (bfd_vma addr ATTRIBUTE_UNUSED,
+			   struct disassemble_info *info ATTRIBUTE_UNUSED)
 {
   return 1;
 }
diff --git a/opcodes/dlx-dis.c b/opcodes/dlx-dis.c
index eee6132..9e9a83d 100644
--- a/opcodes/dlx-dis.c
+++ b/opcodes/dlx-dis.c
@@ -1,5 +1,5 @@
 /* Instruction printing code for the DLX Microprocessor
-   Copyright 2002 Free Software Foundation, Inc.
+   Copyright 2002, 2005 Free Software Foundation, Inc.
    Contributed by Kuang Hwa Lin.  Written by Kuang Hwa Lin, 03/2002.
 
    This program is free software; you can redistribute it and/or modify
@@ -14,7 +14,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include "sysdep.h"
 #include "dis-asm.h"
@@ -36,79 +37,55 @@
 unsigned char opc, rs1, rs2, rd;
 unsigned long imm26, imm16, func, current_insn_addr;
 
-static unsigned char dlx_get_opcode PARAMS ((unsigned long));
-static unsigned char dlx_get_rs1    PARAMS ((unsigned long));
-static unsigned char dlx_get_rs2    PARAMS ((unsigned long));
-static unsigned char dlx_get_rdR    PARAMS ((unsigned long));
-static unsigned long dlx_get_func   PARAMS ((unsigned long)); 
-static unsigned long dlx_get_imm16  PARAMS ((unsigned long));
-static unsigned long dlx_get_imm26  PARAMS ((unsigned long));
-static void     operand_deliminator PARAMS ((struct disassemble_info *, char *));
-static unsigned char dlx_r_type     PARAMS ((struct disassemble_info *));
-static unsigned char dlx_load_type  PARAMS ((struct disassemble_info *));
-static unsigned char dlx_store_type PARAMS ((struct disassemble_info *));
-static unsigned char dlx_aluI_type  PARAMS ((struct disassemble_info *));
-static unsigned char dlx_br_type    PARAMS ((struct disassemble_info *));
-static unsigned char dlx_jmp_type   PARAMS ((struct disassemble_info *));
-static unsigned char dlx_jr_type    PARAMS ((struct disassemble_info *));
-
 /* Print one instruction from MEMADDR on INFO->STREAM.
    Return the size of the instruction (always 4 on dlx).  */
 
 static unsigned char
-dlx_get_opcode (opcode)
-     unsigned long opcode;
+dlx_get_opcode (unsigned long opcode)
 {
   return (unsigned char) ((opcode >> 26) & 0x3F);
 }
 
 static unsigned char
-dlx_get_rs1 (opcode)
-     unsigned long opcode;
+dlx_get_rs1 (unsigned long opcode)
 {
   return (unsigned char) ((opcode >> 21) & 0x1F);
 }
 
 static unsigned char
-dlx_get_rs2 (opcode)
-     unsigned long opcode;
+dlx_get_rs2 (unsigned long opcode)
 {
   return (unsigned char) ((opcode >> 16) & 0x1F);
 }
 
 static unsigned char
-dlx_get_rdR (opcode)
-     unsigned long opcode;
+dlx_get_rdR (unsigned long opcode)
 {
   return (unsigned char) ((opcode >> 11) & 0x1F);
 }
 
 static unsigned long
-dlx_get_func (opcode)
-     unsigned long opcode;
+dlx_get_func (unsigned long opcode)
 {
   return (unsigned char) (opcode & 0x7FF);
 }
 
 static unsigned long
-dlx_get_imm16 (opcode)
-     unsigned long opcode;
+dlx_get_imm16 (unsigned long opcode)
 {
   return (unsigned long) (opcode & 0xFFFF);
 }
 
 static unsigned long
-dlx_get_imm26 (opcode)
-     unsigned long opcode;
+dlx_get_imm26 (unsigned long opcode)
 {
   return (unsigned long) (opcode & 0x03FFFFFF);
 }
 
 /* Fill the opcode to the max length.  */
+
 static void
-operand_deliminator (info, ptr)
-     struct disassemble_info *info;
-     char *ptr;
+operand_deliminator (struct disassemble_info *info, char *ptr)
 {
   int difft = 8 - (int) strlen (ptr);
 
@@ -120,9 +97,9 @@ operand_deliminator (info, ptr)
 }
 
 /* Process the R-type opcode.  */
+
 static unsigned char
-dlx_r_type (info)
-     struct disassemble_info *info;
+dlx_r_type (struct disassemble_info *info)
 {
   unsigned char r_opc[] = { OPC(ALUOP) }; /* Fix ME */
   int r_opc_num = (sizeof r_opc) / (sizeof (char));
@@ -132,7 +109,7 @@ dlx_r_type (info)
     char *name;
   }
   dlx_r_opcode[] =
-    {
+  {
     { NOPF,     "nop"    },  /* NOP                          */
     { ADDF,     "add"    },  /* Add                          */
     { ADDUF,    "addu"   },  /* Add Unsigned                 */
@@ -174,7 +151,7 @@ dlx_r_type (info)
 	continue;
       else
 	break;
-  }
+    }
 
   if (idx == r_opc_num)
     return NIL;
@@ -202,8 +179,7 @@ dlx_r_type (info)
 /* Process the memory read opcode.  */
 
 static unsigned char
-dlx_load_type (info)
-     struct disassemble_info* info;
+dlx_load_type (struct disassemble_info* info)
 {
   struct _load_opcode
   {
@@ -211,17 +187,17 @@ dlx_load_type (info)
     char *name;
   }
   dlx_load_opcode[] =
-    {
-      { OPC(LHIOP),   "lhi" },  /* Load HI to register.           */
-      { OPC(LBOP),     "lb" },  /* load byte sign extended.       */
-      { OPC(LBUOP),   "lbu" },  /* load byte unsigned.            */
-      { OPC(LSBUOP),"ldstbu"},  /* load store byte unsigned.      */
-      { OPC(LHOP),     "lh" },  /* load halfword sign extended.   */
-      { OPC(LHUOP),   "lhu" },  /* load halfword unsigned.        */
-      { OPC(LSHUOP),"ldsthu"},  /* load store halfword unsigned.  */
-      { OPC(LWOP),     "lw" },  /* load word.                     */
-      { OPC(LSWOP), "ldstw" }   /* load store word.               */
-    };
+  {
+    { OPC(LHIOP),   "lhi" },  /* Load HI to register.           */
+    { OPC(LBOP),     "lb" },  /* load byte sign extended.       */
+    { OPC(LBUOP),   "lbu" },  /* load byte unsigned.            */
+    { OPC(LSBUOP),"ldstbu"},  /* load store byte unsigned.      */
+    { OPC(LHOP),     "lh" },  /* load halfword sign extended.   */
+    { OPC(LHUOP),   "lhu" },  /* load halfword unsigned.        */
+    { OPC(LSHUOP),"ldsthu"},  /* load store halfword unsigned.  */
+    { OPC(LWOP),     "lw" },  /* load word.                     */
+    { OPC(LSWOP), "ldstw" }   /* load store word.               */
+  };
   int dlx_load_opcode_num =
     (sizeof dlx_load_opcode) / (sizeof dlx_load_opcode[0]);
   int idx;
@@ -253,8 +229,7 @@ dlx_load_type (info)
 /* Process the memory store opcode.  */
 
 static unsigned char
-dlx_store_type (info)
-     struct disassemble_info* info;
+dlx_store_type (struct disassemble_info* info)
 {
   struct _store_opcode
   {
@@ -262,11 +237,11 @@ dlx_store_type (info)
     char *name;
   }
   dlx_store_opcode[] =
-    {
-      { OPC(SBOP),     "sb" },  /* Store byte.      */
-      { OPC(SHOP),     "sh" },  /* Store halfword.  */
-      { OPC(SWOP),     "sw" },  /* Store word.      */
-    };
+  {
+    { OPC(SBOP),     "sb" },  /* Store byte.      */
+    { OPC(SHOP),     "sh" },  /* Store halfword.  */
+    { OPC(SWOP),     "sw" },  /* Store word.      */
+  };
   int dlx_store_opcode_num =
     (sizeof dlx_store_opcode) / (sizeof dlx_store_opcode[0]);
   int idx;
@@ -287,8 +262,7 @@ dlx_store_type (info)
 /* Process the Arithmetic and Logical I-TYPE opcode.  */
 
 static unsigned char
-dlx_aluI_type (info)
-     struct disassemble_info* info;
+dlx_aluI_type (struct disassemble_info* info)
 {
   struct _aluI_opcode
   {
@@ -296,34 +270,34 @@ dlx_aluI_type (info)
     char *name;
   }
   dlx_aluI_opcode[] =
-    {
-      { OPC(ADDIOP),   "addi"  },  /* Store byte.      */
-      { OPC(ADDUIOP),  "addui" },  /* Store halfword.  */
-      { OPC(SUBIOP),   "subi"  },  /* Store word.      */
-      { OPC(SUBUIOP),  "subui" },  /* Store word.      */
-      { OPC(ANDIOP),   "andi"  },  /* Store word.      */
-      { OPC(ORIOP),    "ori"   },  /* Store word.      */
-      { OPC(XORIOP),   "xori"  },  /* Store word.      */
-      { OPC(SLLIOP),   "slli"  },  /* Store word.      */
-      { OPC(SRAIOP),   "srai"  },  /* Store word.      */
-      { OPC(SRLIOP),   "srli"  },  /* Store word.      */
-      { OPC(SEQIOP),   "seqi"  },  /* Store word.      */
-      { OPC(SNEIOP),   "snei"  },  /* Store word.      */
-      { OPC(SLTIOP),   "slti"  },  /* Store word.      */
-      { OPC(SGTIOP),   "sgti"  },  /* Store word.      */
-      { OPC(SLEIOP),   "slei"  },  /* Store word.      */
-      { OPC(SGEIOP),   "sgei"  },  /* Store word.      */
-      { OPC(SEQUIOP),  "sequi" },  /* Store word.      */
-      { OPC(SNEUIOP),  "sneui" },  /* Store word.      */
-      { OPC(SLTUIOP),  "sltui" },  /* Store word.      */
-      { OPC(SGTUIOP),  "sgtui" },  /* Store word.      */
-      { OPC(SLEUIOP),  "sleui" },  /* Store word.      */
-      { OPC(SGEUIOP),  "sgeui" },  /* Store word.      */
+  {
+    { OPC(ADDIOP),   "addi"  },  /* Store byte.      */
+    { OPC(ADDUIOP),  "addui" },  /* Store halfword.  */
+    { OPC(SUBIOP),   "subi"  },  /* Store word.      */
+    { OPC(SUBUIOP),  "subui" },  /* Store word.      */
+    { OPC(ANDIOP),   "andi"  },  /* Store word.      */
+    { OPC(ORIOP),    "ori"   },  /* Store word.      */
+    { OPC(XORIOP),   "xori"  },  /* Store word.      */
+    { OPC(SLLIOP),   "slli"  },  /* Store word.      */
+    { OPC(SRAIOP),   "srai"  },  /* Store word.      */
+    { OPC(SRLIOP),   "srli"  },  /* Store word.      */
+    { OPC(SEQIOP),   "seqi"  },  /* Store word.      */
+    { OPC(SNEIOP),   "snei"  },  /* Store word.      */
+    { OPC(SLTIOP),   "slti"  },  /* Store word.      */
+    { OPC(SGTIOP),   "sgti"  },  /* Store word.      */
+    { OPC(SLEIOP),   "slei"  },  /* Store word.      */
+    { OPC(SGEIOP),   "sgei"  },  /* Store word.      */
+    { OPC(SEQUIOP),  "sequi" },  /* Store word.      */
+    { OPC(SNEUIOP),  "sneui" },  /* Store word.      */
+    { OPC(SLTUIOP),  "sltui" },  /* Store word.      */
+    { OPC(SGTUIOP),  "sgtui" },  /* Store word.      */
+    { OPC(SLEUIOP),  "sleui" },  /* Store word.      */
+    { OPC(SGEUIOP),  "sgeui" },  /* Store word.      */
 #if 0						       
-      { OPC(MVTSOP),   "mvts"  },  /* Store word.      */
-      { OPC(MVFSOP),   "mvfs"  },  /* Store word.      */
+    { OPC(MVTSOP),   "mvts"  },  /* Store word.      */
+    { OPC(MVFSOP),   "mvfs"  },  /* Store word.      */
 #endif
-    };
+  };
   int dlx_aluI_opcode_num =
     (sizeof dlx_aluI_opcode) / (sizeof dlx_aluI_opcode[0]);
   int idx;
@@ -346,8 +320,7 @@ dlx_aluI_type (info)
 /* Process the branch instruction.  */
 
 static unsigned char
-dlx_br_type (info)
-     struct disassemble_info* info;
+dlx_br_type (struct disassemble_info* info)
 {
   struct _br_opcode
   {
@@ -355,10 +328,10 @@ dlx_br_type (info)
     char *name;
   }
   dlx_br_opcode[] =
-    {
-      { OPC(BEQOP), "beqz" }, /* Store byte.  */
-      { OPC(BNEOP), "bnez" }  /* Store halfword.  */
-    };
+  {
+    { OPC(BEQOP), "beqz" }, /* Store byte.  */
+    { OPC(BNEOP), "bnez" }  /* Store halfword.  */
+  };
   int dlx_br_opcode_num =
     (sizeof dlx_br_opcode) / (sizeof dlx_br_opcode[0]);
   int idx;
@@ -372,8 +345,8 @@ dlx_br_type (info)
 	imm16 += (current_insn_addr + 4);
 	(*info->fprintf_func) (info->stream, "%s", dlx_br_opcode[idx].name);
 	operand_deliminator (info, dlx_br_opcode[idx].name);
-	(*info->fprintf_func) (info->stream, "r%d,", (int)rs1);
-	(*info->fprintf_func) (info->stream, "0x%08x", (int)imm16);
+	(*info->fprintf_func) (info->stream, "r%d,", (int) rs1);
+	(*info->fprintf_func) (info->stream, "0x%08x", (int) imm16);
 
 	return (unsigned char) IBR_TYPE;
       }
@@ -384,8 +357,7 @@ dlx_br_type (info)
 /* Process the jump instruction.  */
 
 static unsigned char
-dlx_jmp_type (info)
-     struct disassemble_info* info;
+dlx_jmp_type (struct disassemble_info* info)
 {
   struct _jmp_opcode
   {
@@ -393,13 +365,13 @@ dlx_jmp_type (info)
     char *name;
   }
   dlx_jmp_opcode[] =
-    {
-      { OPC(JOP),         "j" },  /* Store byte.      */
-      { OPC(JALOP),     "jal" },  /* Store halfword.  */
-      { OPC(BREAKOP), "break" },  /* Store halfword.  */
-      { OPC(TRAPOP),   "trap" },  /* Store halfword.  */
-      { OPC(RFEOP),     "rfe" }   /* Store halfword.  */
-    };
+  {
+    { OPC(JOP),         "j" },  /* Store byte.      */
+    { OPC(JALOP),     "jal" },  /* Store halfword.  */
+    { OPC(BREAKOP), "break" },  /* Store halfword.  */
+    { OPC(TRAPOP),   "trap" },  /* Store halfword.  */
+    { OPC(RFEOP),     "rfe" }   /* Store halfword.  */
+  };
   int dlx_jmp_opcode_num =
     (sizeof dlx_jmp_opcode) / (sizeof dlx_jmp_opcode[0]);
   int idx;
@@ -425,15 +397,15 @@ dlx_jmp_type (info)
 /* Process the jump register instruction.  */
 
 static unsigned char
-dlx_jr_type (info)
-     struct disassemble_info* info;
+dlx_jr_type (struct disassemble_info* info)
 {
   struct _jr_opcode
   {
     unsigned long opcode;
     char *name;
   }
-  dlx_jr_opcode[] = {
+  dlx_jr_opcode[] =
+  {
     { OPC(JROP),   "jr"    },  /* Store byte.  */
     { OPC(JALROP), "jalr"  }   /* Store halfword.  */
   };
@@ -453,29 +425,27 @@ dlx_jr_type (info)
   return (unsigned char) NIL;
 }
 
-typedef unsigned char (* dlx_insn) PARAMS ((struct disassemble_info *));
+typedef unsigned char (* dlx_insn) (struct disassemble_info *);
 
 /* This is the main DLX insn handling routine.  */
 
 int
-print_insn_dlx (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info* info;
+print_insn_dlx (bfd_vma memaddr, struct disassemble_info* info)
 {
   bfd_byte buffer[4];
   int insn_idx;
   unsigned long insn_word;
   unsigned char rtn_code;
   unsigned long dlx_insn_type[] =
-    {
-      (unsigned long) dlx_r_type,
-      (unsigned long) dlx_load_type,
-      (unsigned long) dlx_store_type,
-      (unsigned long) dlx_aluI_type,
-      (unsigned long) dlx_br_type,
-      (unsigned long) dlx_jmp_type,
-      (unsigned long) dlx_jr_type,
-      (unsigned long) NULL
+  {
+    (unsigned long) dlx_r_type,
+    (unsigned long) dlx_load_type,
+    (unsigned long) dlx_store_type,
+    (unsigned long) dlx_aluI_type,
+    (unsigned long) dlx_br_type,
+    (unsigned long) dlx_jmp_type,
+    (unsigned long) dlx_jr_type,
+    (unsigned long) NULL
   };
   int dlx_insn_type_num = ((sizeof dlx_insn_type) / (sizeof (unsigned long))) - 1;
   int status =
diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c
index 1b7ed65..82381e8 100644
--- a/opcodes/fr30-asm.c
+++ b/opcodes/fr30-asm.c
@@ -1,26 +1,27 @@
 /* Assembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-asm.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-asm.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -50,26 +51,13 @@ static const char * parse_insn_normal
 /* -- asm.c */
 /* Handle register lists for LDMx and STMx.  */
 
-static int parse_register_number
-  PARAMS ((const char **));
-static const char * parse_register_list
-  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *, int, int));
-static const char * parse_low_register_list_ld
-  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_hi_register_list_ld
-  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_low_register_list_st
-  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_hi_register_list_st
-  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-
 static int
-parse_register_number (strp)
-     const char **strp;
+parse_register_number (const char **strp)
 {
   int regno;
+
   if (**strp < '0' || **strp > '9')
-    return -1; /* error.  */
+    return -1; /* Error.  */
   regno = **strp - '0';
   ++*strp;
 
@@ -83,30 +71,29 @@ parse_register_number (strp)
 }
 
 static const char *
-parse_register_list (cd, strp, opindex, valuep, high_low, load_store)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     const char **strp;
-     int opindex ATTRIBUTE_UNUSED;
-     unsigned long *valuep;
-     int high_low;   /* 0 == high, 1 == low */
-     int load_store; /* 0 == load, 1 == store */
+parse_register_list (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		     const char **strp,
+		     int opindex ATTRIBUTE_UNUSED,
+		     unsigned long *valuep,
+		     int high_low,   /* 0 == high, 1 == low.  */
+		     int load_store) /* 0 == load, 1 == store.  */
 {
-  int regno;
-
   *valuep = 0;
   while (**strp && **strp != ')')
     {
+      int regno;
+
       if (**strp != 'R' && **strp != 'r')
 	break;
       ++*strp;
 
       regno = parse_register_number (strp);
       if (regno == -1)
-	return "Register number is not valid";
+	return _("Register number is not valid");
       if (regno > 7 && !high_low)
-	return "Register must be between r0 and r7";
+	return _("Register must be between r0 and r7");
       if (regno < 8 && high_low)
-	return "Register must be between r8 and r15";
+	return _("Register must be between r8 and r15");
 
       if (high_low)
 	regno -= 8;
@@ -125,55 +112,55 @@ parse_register_list (cd, strp, opindex, valuep, high_low, load_store)
     }
 
   if (!*strp || **strp != ')')
-    return "Register list is not valid";
+    return _("Register list is not valid");
 
   return NULL;
 }
 
 static const char *
-parse_low_register_list_ld (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_low_register_list_ld (CGEN_CPU_DESC cd,
+			    const char **strp,
+			    int opindex,
+			    unsigned long *valuep)
 {
-  return parse_register_list (cd, strp, opindex, valuep, 0/*low*/, 0/*load*/);
+  return parse_register_list (cd, strp, opindex, valuep,
+			      0 /* Low.  */, 0 /* Load.  */);
 }
 
 static const char *
-parse_hi_register_list_ld (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_hi_register_list_ld (CGEN_CPU_DESC cd,
+			   const char **strp,
+			   int opindex,
+			   unsigned long *valuep)
 {
-  return parse_register_list (cd, strp, opindex, valuep, 1/*high*/, 0/*load*/);
+  return parse_register_list (cd, strp, opindex, valuep,
+			      1 /* High.  */, 0 /* Load.  */);
 }
 
 static const char *
-parse_low_register_list_st (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_low_register_list_st (CGEN_CPU_DESC cd,
+			    const char **strp,
+			    int opindex,
+			    unsigned long *valuep)
 {
-  return parse_register_list (cd, strp, opindex, valuep, 0/*low*/, 1/*store*/);
+  return parse_register_list (cd, strp, opindex, valuep,
+			      0 /* Low.  */, 1 /* Store.  */);
 }
 
 static const char *
-parse_hi_register_list_st (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_hi_register_list_st (CGEN_CPU_DESC cd,
+			   const char **strp,
+			   int opindex,
+			   unsigned long *valuep)
 {
-  return parse_register_list (cd, strp, opindex, valuep, 1/*high*/, 1/*store*/);
+  return parse_register_list (cd, strp, opindex, valuep,
+			      1 /* High.  */, 1 /* Store.  */);
 }
 
 /* -- */
 
 const char * fr30_cgen_parse_operand
-  PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
 
 /* Main entry point for operand parsing.
 
@@ -189,11 +176,10 @@ const char * fr30_cgen_parse_operand
    the handlers.  */
 
 const char *
-fr30_cgen_parse_operand (cd, opindex, strp, fields)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     const char ** strp;
-     CGEN_FIELDS * fields;
+fr30_cgen_parse_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   const char ** strp,
+			   CGEN_FIELDS * fields)
 {
   const char * errmsg = NULL;
   /* Used by scalar operands that still need to be parsed.  */
@@ -333,8 +319,7 @@ cgen_parse_fn * const fr30_cgen_parse_handlers[] =
 };
 
 void
-fr30_cgen_init_asm (cd)
-     CGEN_CPU_DESC cd;
+fr30_cgen_init_asm (CGEN_CPU_DESC cd)
 {
   fr30_cgen_init_opcode_table (cd);
   fr30_cgen_init_ibld_table (cd);
@@ -717,30 +702,3 @@ fr30_cgen_assemble_insn (CGEN_CPU_DESC cd,
     return NULL;
   }
 }
-
-#if 0 /* This calls back to GAS which we can't do without care.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   This lets GAS parse registers for us.
-   ??? Interesting idea but not currently used.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   FIXME: Not currently used.  */
-
-void
-fr30_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
-{
-  CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
-  const CGEN_KEYWORD_ENTRY * ke;
-
-  while ((ke = cgen_keyword_search_next (& search)) != NULL)
-    {
-#if 0 /* Unnecessary, should be done in the search routine.  */
-      if (! fr30_cgen_opval_supported (ke))
-	continue;
-#endif
-      cgen_asm_record_register (cd, ke->name, ke->value);
-    }
-}
-
-#endif /* 0 */
diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c
index 2b0d6b7..768fce6 100644
--- a/opcodes/fr30-desc.c
+++ b/opcodes/fr30-desc.c
@@ -1429,27 +1429,23 @@ static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
 #undef A
 
 /* Initialize anything needed to be done once, before any cpu_open call.  */
-static void init_tables PARAMS ((void));
 
 static void
-init_tables ()
+init_tables (void)
 {
 }
 
-static const CGEN_MACH * lookup_mach_via_bfd_name
-  PARAMS ((const CGEN_MACH *, const char *));
-static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
-static void fr30_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
+static void build_hw_table      (CGEN_CPU_TABLE *);
+static void build_ifield_table  (CGEN_CPU_TABLE *);
+static void build_operand_table (CGEN_CPU_TABLE *);
+static void build_insn_table    (CGEN_CPU_TABLE *);
+static void fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *);
 
 /* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name.  */
 
 static const CGEN_MACH *
-lookup_mach_via_bfd_name (table, name)
-     const CGEN_MACH *table;
-     const char *name;
+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
 {
   while (table->name)
     {
@@ -1463,8 +1459,7 @@ lookup_mach_via_bfd_name (table, name)
 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_hw_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_hw_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -1490,8 +1485,7 @@ build_hw_table (cd)
 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_ifield_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_ifield_table (CGEN_CPU_TABLE *cd)
 {
   cd->ifld_table = & fr30_cgen_ifld_table[0];
 }
@@ -1499,8 +1493,7 @@ build_ifield_table (cd)
 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_operand_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_operand_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -1508,8 +1501,7 @@ build_operand_table (cd)
   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
      However each entry is indexed by it's enum so there can be holes in
      the table.  */
-  const CGEN_OPERAND **selected =
-    (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
 
   cd->operand_table.init_entries = init;
   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@@ -1532,12 +1524,11 @@ build_operand_table (cd)
    operand elements to be in the table [which they mightn't be].  */
 
 static void
-build_insn_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_insn_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   const CGEN_IBASE *ib = & fr30_cgen_insn_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
 
   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
   for (i = 0; i < MAX_INSNS; ++i)
@@ -1550,8 +1541,7 @@ build_insn_table (cd)
 /* Subroutine of fr30_cgen_cpu_open to rebuild the tables.  */
 
 static void
-fr30_cgen_rebuild_tables (cd)
-     CGEN_CPU_TABLE *cd;
+fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
   unsigned int isas = cd->isas;
@@ -1563,7 +1553,7 @@ fr30_cgen_rebuild_tables (cd)
 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
   cd->default_insn_bitsize = UNSET;
   cd->base_insn_bitsize = UNSET;
-  cd->min_insn_bitsize = 65535; /* some ridiculously big number */
+  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
     if (((1 << i) & isas) != 0)
@@ -1575,7 +1565,7 @@ fr30_cgen_rebuild_tables (cd)
 	if (cd->default_insn_bitsize == UNSET)
 	  cd->default_insn_bitsize = isa->default_insn_bitsize;
 	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -1584,7 +1574,7 @@ fr30_cgen_rebuild_tables (cd)
 	if (cd->base_insn_bitsize == UNSET)
 	  cd->base_insn_bitsize = isa->base_insn_bitsize;
 	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -1696,12 +1686,12 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     }
   va_end (ap);
 
-  /* mach unspecified means "all" */
+  /* Mach unspecified means "all".  */
   if (machs == 0)
     machs = (1 << MAX_MACHS) - 1;
-  /* base mach is always selected */
+  /* Base mach is always selected.  */
   machs |= 1;
-  /* isa unspecified means "all" */
+  /* ISA unspecified means "all".  */
   if (isas == 0)
     isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
@@ -1734,9 +1724,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
    MACH_NAME is the bfd name of the mach.  */
 
 CGEN_CPU_DESC
-fr30_cgen_cpu_open_1 (mach_name, endian)
-     const char *mach_name;
-     enum cgen_endian endian;
+fr30_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
 {
   return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
 			       CGEN_CPU_OPEN_ENDIAN, endian,
@@ -1749,8 +1737,7 @@ fr30_cgen_cpu_open_1 (mach_name, endian)
    place as some simulator ports use this but they don't use libopcodes.  */
 
 void
-fr30_cgen_cpu_close (cd)
-     CGEN_CPU_DESC cd;
+fr30_cgen_cpu_close (CGEN_CPU_DESC cd)
 {
   unsigned int i;
   const CGEN_INSN *insns;
@@ -1759,23 +1746,17 @@ fr30_cgen_cpu_close (cd)
     {
       insns = cd->macro_insn_table.init_entries;
       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX ((insns)))
-	    regfree (CGEN_INSN_RX (insns));
-	}
+	if (CGEN_INSN_RX ((insns)))
+	  regfree (CGEN_INSN_RX (insns));
     }
 
   if (cd->insn_table.init_entries)
     {
       insns = cd->insn_table.init_entries;
       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX (insns))
-	    regfree (CGEN_INSN_RX (insns));
-	}
-    }
-
-  
+	if (CGEN_INSN_RX (insns))
+	  regfree (CGEN_INSN_RX (insns));
+    }  
 
   if (cd->macro_insn_table.init_entries)
     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c
index 39a5638..f756a26 100644
--- a/opcodes/fr30-dis.c
+++ b/opcodes/fr30-dis.c
@@ -1,27 +1,27 @@
 /* Disassembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-dis.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-dis.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
-Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -56,33 +56,19 @@ static int read_insn
   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
    unsigned long *);
 
-/* -- disassembler routines inserted here */
+/* -- disassembler routines inserted here.  */
 
 /* -- dis.c */
-static void print_register_list
-  PARAMS ((PTR, long, long, int));
-static void print_hi_register_list_ld
-  PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
-static void print_low_register_list_ld
-  PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
-static void print_hi_register_list_st
-  PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
-static void print_low_register_list_st
-  PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
-static void print_m4
-  PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
-
 static void
-print_register_list (dis_info, value, offset, load_store)
-     PTR dis_info;
-     long value;
-     long offset;
-     int load_store; /* 0 == load, 1 == store */
+print_register_list (void * dis_info,
+		     long value,
+		     long offset,
+		     int load_store) /* 0 == load, 1 == store.  */
 {
   disassemble_info *info = dis_info;
   int mask;
   int index = 0;
-  char* comma = "";
+  char * comma = "";
 
   if (load_store)
     mask = 0x80;
@@ -111,70 +97,65 @@ print_register_list (dis_info, value, offset, load_store)
 }
 
 static void
-print_hi_register_list_ld (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_hi_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			   void * dis_info,
+			   long value,
+			   unsigned int attrs ATTRIBUTE_UNUSED,
+			   bfd_vma pc ATTRIBUTE_UNUSED,
+			   int length ATTRIBUTE_UNUSED)
 {
-  print_register_list (dis_info, value, 8, 0/*load*/);
+  print_register_list (dis_info, value, 8, 0 /* Load.  */);
 }
 
 static void
-print_low_register_list_ld (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_low_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			    void * dis_info,
+			    long value,
+			    unsigned int attrs ATTRIBUTE_UNUSED,
+			    bfd_vma pc ATTRIBUTE_UNUSED,
+			    int length ATTRIBUTE_UNUSED)
 {
-  print_register_list (dis_info, value, 0, 0/*load*/);
+  print_register_list (dis_info, value, 0, 0 /* Load.  */);
 }
 
 static void
-print_hi_register_list_st (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_hi_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			   void * dis_info,
+			   long value,
+			   unsigned int attrs ATTRIBUTE_UNUSED,
+			   bfd_vma pc ATTRIBUTE_UNUSED,
+			   int length ATTRIBUTE_UNUSED)
 {
-  print_register_list (dis_info, value, 8, 1/*store*/);
+  print_register_list (dis_info, value, 8, 1 /* Store.  */);
 }
 
 static void
-print_low_register_list_st (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_low_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			    void * dis_info,
+			    long value,
+			    unsigned int attrs ATTRIBUTE_UNUSED,
+			    bfd_vma pc ATTRIBUTE_UNUSED,
+			    int length ATTRIBUTE_UNUSED)
 {
-  print_register_list (dis_info, value, 0, 1/*store*/);
+  print_register_list (dis_info, value, 0, 1 /* Store.  */);
 }
 
 static void
-print_m4 (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_m4 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	  void * dis_info,
+	  long value,
+	  unsigned int attrs ATTRIBUTE_UNUSED,
+	  bfd_vma pc ATTRIBUTE_UNUSED,
+	  int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
+
   (*info->fprintf_func) (info->stream, "%ld", value);
 }
 /* -- */
 
 void fr30_cgen_print_operand
-  PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
-           void const *, bfd_vma, int));
+  (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
 
 /* Main entry point for printing operands.
    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@@ -192,16 +173,15 @@ void fr30_cgen_print_operand
    the handlers.  */
 
 void
-fr30_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     PTR xinfo;
-     CGEN_FIELDS *fields;
-     void const *attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     int length;
+fr30_cgen_print_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   void * xinfo,
+			   CGEN_FIELDS *fields,
+			   void const *attrs ATTRIBUTE_UNUSED,
+			   bfd_vma pc,
+			   int length)
 {
- disassemble_info *info = (disassemble_info *) xinfo;
+  disassemble_info *info = (disassemble_info *) xinfo;
 
   switch (opindex)
     {
@@ -329,8 +309,7 @@ cgen_print_fn * const fr30_cgen_print_handlers[] =
 
 
 void
-fr30_cgen_init_dis (cd)
-     CGEN_CPU_DESC cd;
+fr30_cgen_init_dis (CGEN_CPU_DESC cd)
 {
   fr30_cgen_init_opcode_table (cd);
   fr30_cgen_init_ibld_table (cd);
@@ -382,7 +361,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 
   /* Print the operand as directed by the attributes.  */
   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
-    ; /* nothing to do */
+    ; /* Nothing to do.  */
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
     (*info->print_address_func) (value, info);
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@@ -464,6 +443,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
+
   if (status != 0)
     {
       (*info->memory_error_func) (status, pc, info);
@@ -568,13 +548,13 @@ print_insn (CGEN_CPU_DESC cd,
 	    length = CGEN_EXTRACT_FN (cd, insn)
 	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 
-	  /* length < 0 -> error */
+	  /* Length < 0 -> error.  */
 	  if (length < 0)
 	    return length;
 	  if (length > 0)
 	    {
 	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
-	      /* length is in bits, result is in bytes */
+	      /* Length is in bits, result is in bytes.  */
 	      return length / 8;
 	    }
 	}
@@ -624,7 +604,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
    Print one instruction from PC on INFO->STREAM.
    Return the size of the instruction (in bytes).  */
 
-typedef struct cpu_desc_list {
+typedef struct cpu_desc_list
+{
   struct cpu_desc_list *next;
   int isa;
   int mach;
@@ -709,7 +690,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info)
       if (!cd)
 	abort ();
 
-      /* save this away for future reference */
+      /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
       cl->isa = isa;
diff --git a/opcodes/fr30-ibld.c b/opcodes/fr30-ibld.c
index 60f76a1..48dad67 100644
--- a/opcodes/fr30-ibld.c
+++ b/opcodes/fr30-ibld.c
@@ -1,25 +1,26 @@
 /* Instruction building/extraction support for fr30. -*- C -*-
 
-THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
-- the resultant file is machine generated, cgen-ibld.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+   - the resultant file is machine generated, cgen-ibld.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #include "opintl.h"
 #include "safe-ctype.h"
 
-#undef min
+#undef  min
 #define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
+#undef  max
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 /* Used by the ifield rtx function.  */
@@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
   if (length == 0)
     return NULL;
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
 
 #if CGEN_INT_INSN_P
 /* Cover function to store an insn value into an integral insn.  Must go here
- because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
+   because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
       int shift = insn_length - length;
       /* Written this way to avoid undefined behaviour.  */
       CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
       *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
     }
 }
@@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
 {
   unsigned long x;
   int shift;
-#if 0
-  int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
-#endif
+
   x = cgen_get_insn_value (cd, bufp, word_length);
 
   if (CGEN_INSN_LSB0_P)
@@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
       return 1;
     }
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
   return CGEN_INSN_BITSIZE (insn);
 }
 
-/* machine generated code added here */
+/* Machine generated code added here.  */
 
 const char * fr30_cgen_insert_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 
 /* Main entry point for operand insertion.
 
@@ -559,12 +547,11 @@ const char * fr30_cgen_insert_operand
    resolved during parsing.  */
 
 const char *
-fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+fr30_cgen_insert_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     CGEN_INSN_BYTES_PTR buffer,
+			     bfd_vma pc ATTRIBUTE_UNUSED)
 {
   const char * errmsg = NULL;
   unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@@ -738,8 +725,7 @@ fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc)
 }
 
 int fr30_cgen_extract_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-           CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 
 /* Main entry point for operand extraction.
    The result is <= 0 for error, >0 for success.
@@ -757,13 +743,12 @@ int fr30_cgen_extract_operand
    the handlers.  */
 
 int
-fr30_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS * fields;
-     bfd_vma pc;
+fr30_cgen_extract_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_EXTRACT_INFO *ex_info,
+			     CGEN_INSN_INT insn_value,
+			     CGEN_FIELDS * fields,
+			     bfd_vma pc)
 {
   /* Assume success (for those operands that are nops).  */
   int length = 1;
@@ -954,10 +939,8 @@ cgen_extract_fn * const fr30_cgen_extract_handlers[] =
   extract_insn_normal,
 };
 
-int fr30_cgen_get_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
-bfd_vma fr30_cgen_get_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+int fr30_cgen_get_int_operand     (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+bfd_vma fr30_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
 
 /* Getting values from cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they return.
@@ -965,10 +948,9 @@ bfd_vma fr30_cgen_get_vma_operand
    not appropriate.  */
 
 int
-fr30_cgen_get_int_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+fr30_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   int value;
 
@@ -1094,10 +1076,9 @@ fr30_cgen_get_int_operand (cd, opindex, fields)
 }
 
 bfd_vma
-fr30_cgen_get_vma_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+fr30_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   bfd_vma value;
 
@@ -1222,10 +1203,8 @@ fr30_cgen_get_vma_operand (cd, opindex, fields)
   return value;
 }
 
-void fr30_cgen_set_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
-void fr30_cgen_set_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+void fr30_cgen_set_int_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
+void fr30_cgen_set_vma_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
 
 /* Stuffing values in cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they accept.
@@ -1233,11 +1212,10 @@ void fr30_cgen_set_vma_operand
    not appropriate.  */
 
 void
-fr30_cgen_set_int_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     int value;
+fr30_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     int value)
 {
   switch (opindex)
     {
@@ -1355,11 +1333,10 @@ fr30_cgen_set_int_operand (cd, opindex, fields, value)
 }
 
 void
-fr30_cgen_set_vma_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     bfd_vma value;
+fr30_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     bfd_vma value)
 {
   switch (opindex)
     {
@@ -1479,8 +1456,7 @@ fr30_cgen_set_vma_operand (cd, opindex, fields, value)
 /* Function to call before using the instruction builder tables.  */
 
 void
-fr30_cgen_init_ibld_table (cd)
-     CGEN_CPU_DESC cd;
+fr30_cgen_init_ibld_table (CGEN_CPU_DESC cd)
 {
   cd->insert_handlers = & fr30_cgen_insert_handlers[0];
   cd->extract_handlers = & fr30_cgen_extract_handlers[0];
diff --git a/opcodes/fr30-opc.c b/opcodes/fr30-opc.c
index aa6b41f..0eefb46 100644
--- a/opcodes/fr30-opc.c
+++ b/opcodes/fr30-opc.c
@@ -33,10 +33,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* The hash functions are recorded here to help keep assembler code out of
    the disassembler and vice versa.  */
 
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static int asm_hash_insn_p        (const CGEN_INSN *);
+static unsigned int asm_hash_insn (const char *);
+static int dis_hash_insn_p        (const CGEN_INSN *);
+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
 
 /* Instruction formats.  */
 
@@ -1340,14 +1340,10 @@ dis_hash_insn (buf, value)
   return CGEN_DIS_HASH (buf, value);
 }
 
-static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
-
 /* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
 
 static void
-set_fields_bitsize (fields, size)
-     CGEN_FIELDS *fields;
-     int size;
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
 {
   CGEN_FIELDS_BITSIZE (fields) = size;
 }
@@ -1356,15 +1352,15 @@ set_fields_bitsize (fields, size)
    This plugs the opcode entries and macro instructions into the cpu table.  */
 
 void
-fr30_cgen_init_opcode_table (cd)
-     CGEN_CPU_DESC cd;
+fr30_cgen_init_opcode_table (CGEN_CPU_DESC cd)
 {
   int i;
   int num_macros = (sizeof (fr30_cgen_macro_insn_table) /
 		    sizeof (fr30_cgen_macro_insn_table[0]));
   const CGEN_IBASE *ib = & fr30_cgen_macro_insn_table[0];
   const CGEN_OPCODE *oc = & fr30_cgen_macro_insn_opcode_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
+
   memset (insns, 0, num_macros * sizeof (CGEN_INSN));
   for (i = 0; i < num_macros; ++i)
     {
diff --git a/opcodes/fr30-opc.h b/opcodes/fr30-opc.h
index 39cc61f..645b3cc 100644
--- a/opcodes/fr30-opc.h
+++ b/opcodes/fr30-opc.h
@@ -28,9 +28,9 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* -- opc.h */
 
 /* ??? This can be improved upon.  */
-#undef CGEN_DIS_HASH_SIZE
+#undef  CGEN_DIS_HASH_SIZE
 #define CGEN_DIS_HASH_SIZE 16
-#undef CGEN_DIS_HASH
+#undef  CGEN_DIS_HASH
 #define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 4)
 
 /* -- */
diff --git a/opcodes/frv-asm.c b/opcodes/frv-asm.c
index 12f6adf..7792d9d 100644
--- a/opcodes/frv-asm.c
+++ b/opcodes/frv-asm.c
@@ -1,26 +1,27 @@
 /* Assembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-asm.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-asm.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -48,31 +49,6 @@ static const char * parse_insn_normal
 /* -- assembler routines inserted here.  */
 
 /* -- asm.c */
-static const char * parse_ulo16
-  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_uslo16
-  PARAMS ((CGEN_CPU_DESC, const char **, int, signed long *));
-static const char * parse_uhi16
-  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static long parse_register_number
-  PARAMS ((const char **));
-static const char * parse_spr
-  PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *));
-static const char * parse_d12
-  PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
-static const char * parse_s12
-  PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
-static const char * parse_u12
-  PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
-static const char * parse_even_register
-  PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *));
-static const char * parse_A0
-  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_A1
-  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_A
-  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *, unsigned long));
-
 inline static const char *
 parse_symbolic_address (CGEN_CPU_DESC cd,
 			const char **strp,
@@ -214,11 +190,10 @@ parse_ld_annotation (CGEN_CPU_DESC cd,
 }
 
 static const char *
-parse_ulo16 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_ulo16 (CGEN_CPU_DESC cd,
+	     const char **strp,
+	     int opindex,
+	     unsigned long *valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
@@ -230,7 +205,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
 	{
 	  *strp += 4;
 	  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16,
-				       &result_type, &value);
+				       & result_type, & value);
 	  if (**strp != ')')
 	    return "missing `)'";
 	  ++*strp;
@@ -245,7 +220,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
 	  *strp += 9;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GPRELLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -257,7 +232,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
 	  *strp += 7;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -269,7 +244,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
 	  *strp += 15;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_FUNCDESC_GOTLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -281,7 +256,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
 	  *strp += 10;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTOFFLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -293,7 +268,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
 	  *strp += 18;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_FUNCDESC_GOTOFFLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -305,7 +280,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
 	  *strp += 14;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTTLSDESCLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -317,7 +292,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
 	  *strp += 11;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_TLSMOFFLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -329,7 +304,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
 	  *strp += 13;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTTLSOFFLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -341,11 +316,10 @@ parse_ulo16 (cd, strp, opindex, valuep)
 }
 
 static const char *
-parse_uslo16 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     signed long *valuep;
+parse_uslo16 (CGEN_CPU_DESC cd,
+	      const char **strp,
+	      int opindex,
+	      signed long *valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
@@ -357,7 +331,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
 	{
 	  *strp += 4;
 	  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16,
-				       &result_type, &value);
+				       & result_type, & value);
 	  if (**strp != ')')
 	    return "missing `)'";
 	  ++*strp;
@@ -372,7 +346,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
 	  *strp += 9;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GPRELLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -384,7 +358,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
 	  *strp += 7;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -396,7 +370,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
 	  *strp += 15;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_FUNCDESC_GOTLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -408,7 +382,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
 	  *strp += 10;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTOFFLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -420,7 +394,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
 	  *strp += 18;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_FUNCDESC_GOTOFFLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -432,7 +406,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
 	  *strp += 14;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTTLSDESCLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -444,7 +418,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
 	  *strp += 11;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_TLSMOFFLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -456,7 +430,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
 	  *strp += 13;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTTLSOFFLO,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -468,11 +442,10 @@ parse_uslo16 (cd, strp, opindex, valuep)
 }
 
 static const char *
-parse_uhi16 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_uhi16 (CGEN_CPU_DESC cd,
+	     const char **strp,
+	     int opindex,
+	     unsigned long *valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
@@ -484,7 +457,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
 	{
 	  *strp += 4;
 	  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_HI16,
-				       &result_type, &value);
+				       & result_type, & value);
 	  if (**strp != ')')
 	    return "missing `)'";
 	  ++*strp;
@@ -506,7 +479,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
 	  *strp += 9;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GPRELHI,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -518,7 +491,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
 	  *strp += 7;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTHI,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -530,7 +503,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
 	  *strp += 15;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_FUNCDESC_GOTHI,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -542,7 +515,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
 	  *strp += 10;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTOFFHI,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -554,7 +527,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
 	  *strp += 18;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_FUNCDESC_GOTOFFHI,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -578,7 +551,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
 	  *strp += 11;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_TLSMOFFHI,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -590,7 +563,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
 	  *strp += 13;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTTLSOFFHI,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -602,10 +575,10 @@ parse_uhi16 (cd, strp, opindex, valuep)
 }
 
 static long
-parse_register_number (strp)
-     const char **strp;
+parse_register_number (const char **strp)
 {
   int regno;
+
   if (**strp < '0' || **strp > '9')
     return -1; /* error */
 
@@ -617,11 +590,10 @@ parse_register_number (strp)
 }
 
 static const char *
-parse_spr (cd, strp, table, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     CGEN_KEYWORD * table;
-     long *valuep;
+parse_spr (CGEN_CPU_DESC cd,
+	   const char **strp,
+	   CGEN_KEYWORD * table,
+	   long *valuep)
 {
   const char *save_strp;
   long regno;
@@ -632,10 +604,10 @@ parse_spr (cd, strp, table, valuep)
       *strp += 4;
       regno = parse_register_number (strp);
       if (**strp != ']')
-        return "missing `]'";
+        return _("missing `]'");
       ++*strp;
       if (! spr_valid (regno))
-	return "Special purpose register number is out of range";
+	return _("Special purpose register number is out of range");
       *valuep = regno;
       return NULL;
     }
@@ -645,7 +617,7 @@ parse_spr (cd, strp, table, valuep)
   if (regno != -1)
     {
       if (! spr_valid (regno))
-	return "Special purpose register number is out of range";
+	return _("Special purpose register number is out of range");
       *valuep = regno;
       return NULL;
     }
@@ -655,11 +627,10 @@ parse_spr (cd, strp, table, valuep)
 }
 
 static const char *
-parse_d12 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     long *valuep;
+parse_d12 (CGEN_CPU_DESC cd,
+	   const char **strp,
+	   int opindex,
+	   long *valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
@@ -673,7 +644,7 @@ parse_d12 (cd, strp, opindex, valuep)
           *strp += 9;
           errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GPREL12,
-					   &result_type, &value);
+					   & result_type, & value);
           if (**strp != ')')
             return "missing `)'";
           ++*strp;
@@ -685,7 +656,7 @@ parse_d12 (cd, strp, opindex, valuep)
 	  *strp += 7;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOT12,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -697,7 +668,7 @@ parse_d12 (cd, strp, opindex, valuep)
 	  *strp += 15;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_FUNCDESC_GOT12,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -709,7 +680,7 @@ parse_d12 (cd, strp, opindex, valuep)
 	  *strp += 10;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTOFF12,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -721,7 +692,7 @@ parse_d12 (cd, strp, opindex, valuep)
 	  *strp += 18;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_FUNCDESC_GOTOFF12,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -733,7 +704,7 @@ parse_d12 (cd, strp, opindex, valuep)
 	  *strp += 14;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTTLSDESC12,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -745,7 +716,7 @@ parse_d12 (cd, strp, opindex, valuep)
 	  *strp += 11;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_TLSMOFF12,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -757,7 +728,7 @@ parse_d12 (cd, strp, opindex, valuep)
 	  *strp += 13;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTTLSOFF12,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -769,11 +740,10 @@ parse_d12 (cd, strp, opindex, valuep)
 }
 
 static const char *
-parse_s12 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     long *valuep;
+parse_s12 (CGEN_CPU_DESC cd,
+	   const char **strp,
+	   int opindex,
+	   long *valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
@@ -787,7 +757,7 @@ parse_s12 (cd, strp, opindex, valuep)
 	  *strp += 9;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GPREL12,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing `)'";
 	  ++*strp;
@@ -799,7 +769,7 @@ parse_s12 (cd, strp, opindex, valuep)
 	  *strp += 7;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOT12,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -811,7 +781,7 @@ parse_s12 (cd, strp, opindex, valuep)
 	  *strp += 15;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_FUNCDESC_GOT12,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -823,7 +793,7 @@ parse_s12 (cd, strp, opindex, valuep)
 	  *strp += 10;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTOFF12,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -835,7 +805,7 @@ parse_s12 (cd, strp, opindex, valuep)
 	  *strp += 18;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_FUNCDESC_GOTOFF12,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -847,7 +817,7 @@ parse_s12 (cd, strp, opindex, valuep)
 	  *strp += 14;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTTLSDESC12,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -859,7 +829,7 @@ parse_s12 (cd, strp, opindex, valuep)
 	  *strp += 11;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_TLSMOFF12,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -871,7 +841,7 @@ parse_s12 (cd, strp, opindex, valuep)
 	  *strp += 13;
 	  errmsg = parse_symbolic_address (cd, strp, opindex,
 					   BFD_RELOC_FRV_GOTTLSOFF12,
-					   &result_type, &value);
+					   & result_type, & value);
 	  if (**strp != ')')
 	    return "missing ')'";
 	  ++*strp;
@@ -886,11 +856,10 @@ parse_s12 (cd, strp, opindex, valuep)
 }
 
 static const char *
-parse_u12 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     long *valuep;
+parse_u12 (CGEN_CPU_DESC cd,
+	   const char **strp,
+	   int opindex,
+	   long *valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
@@ -903,7 +872,7 @@ parse_u12 (cd, strp, opindex, valuep)
       *strp += 9;
       errmsg = parse_symbolic_address (cd, strp, opindex,
 				       BFD_RELOC_FRV_GPRELU12,
-				       &result_type, &value);
+				       & result_type, & value);
       if (**strp != ')')
         return "missing `)'";
       ++*strp;
@@ -919,12 +888,11 @@ parse_u12 (cd, strp, opindex, valuep)
 }
 
 static const char *
-parse_A (cd, strp, opindex, valuep, A)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
-     unsigned long A;
+parse_A (CGEN_CPU_DESC cd,
+	 const char **strp,
+	 int opindex,
+	 unsigned long *valuep,
+	 unsigned long A)
 {
   const char *errmsg;
  
@@ -936,37 +904,34 @@ parse_A (cd, strp, opindex, valuep, A)
     return errmsg;
 
   if (*valuep != A)
-    return "Value of A operand must be 0 or 1";
+    return _("Value of A operand must be 0 or 1");
 
   return NULL;
 }
 
 static const char *
-parse_A0 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_A0 (CGEN_CPU_DESC cd,
+	  const char **strp,
+	  int opindex,
+	  unsigned long *valuep)
 {
   return parse_A (cd, strp, opindex, valuep, 0);
 }
 
 static const char *
-parse_A1 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_A1 (CGEN_CPU_DESC cd,
+	  const char **strp,
+	  int opindex,
+	  unsigned long *valuep)
 {
   return parse_A (cd, strp, opindex, valuep, 1);
 }
 
 static const char *
-parse_even_register (cd, strP, tableP, valueP)
-     CGEN_CPU_DESC  cd;
-     const char **  strP;
-     CGEN_KEYWORD * tableP;
-     long *         valueP;
+parse_even_register (CGEN_CPU_DESC  cd,
+		     const char **  strP,
+		     CGEN_KEYWORD * tableP,
+		     long *         valueP)
 {
   const char * errmsg;
   const char * saved_star_strP = * strP;
@@ -1003,7 +968,7 @@ parse_call_label (CGEN_CPU_DESC cd,
 					   BFD_RELOC_FRV_GETTLSOFF,
 					   resultp, &value);
 	  if (**strp != ')')
-	    return "missing `)'";
+	    return _("missing `)'");
 	  ++*strp;
 	  *valuep = value;
 	  return errmsg;
@@ -1016,7 +981,7 @@ parse_call_label (CGEN_CPU_DESC cd,
 /* -- */
 
 const char * frv_cgen_parse_operand
-  PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
 
 /* Main entry point for operand parsing.
 
@@ -1032,11 +997,10 @@ const char * frv_cgen_parse_operand
    the handlers.  */
 
 const char *
-frv_cgen_parse_operand (cd, opindex, strp, fields)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     const char ** strp;
-     CGEN_FIELDS * fields;
+frv_cgen_parse_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   const char ** strp,
+			   CGEN_FIELDS * fields)
 {
   const char * errmsg = NULL;
   /* Used by scalar operands that still need to be parsed.  */
@@ -1308,8 +1272,7 @@ cgen_parse_fn * const frv_cgen_parse_handlers[] =
 };
 
 void
-frv_cgen_init_asm (cd)
-     CGEN_CPU_DESC cd;
+frv_cgen_init_asm (CGEN_CPU_DESC cd)
 {
   frv_cgen_init_opcode_table (cd);
   frv_cgen_init_ibld_table (cd);
@@ -1692,30 +1655,3 @@ frv_cgen_assemble_insn (CGEN_CPU_DESC cd,
     return NULL;
   }
 }
-
-#if 0 /* This calls back to GAS which we can't do without care.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   This lets GAS parse registers for us.
-   ??? Interesting idea but not currently used.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   FIXME: Not currently used.  */
-
-void
-frv_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
-{
-  CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
-  const CGEN_KEYWORD_ENTRY * ke;
-
-  while ((ke = cgen_keyword_search_next (& search)) != NULL)
-    {
-#if 0 /* Unnecessary, should be done in the search routine.  */
-      if (! frv_cgen_opval_supported (ke))
-	continue;
-#endif
-      cgen_asm_record_register (cd, ke->name, ke->value);
-    }
-}
-
-#endif /* 0 */
diff --git a/opcodes/frv-desc.c b/opcodes/frv-desc.c
index 971d598..bff97d8 100644
--- a/opcodes/frv-desc.c
+++ b/opcodes/frv-desc.c
@@ -6142,27 +6142,23 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
 #undef A
 
 /* Initialize anything needed to be done once, before any cpu_open call.  */
-static void init_tables PARAMS ((void));
 
 static void
-init_tables ()
+init_tables (void)
 {
 }
 
-static const CGEN_MACH * lookup_mach_via_bfd_name
-  PARAMS ((const CGEN_MACH *, const char *));
-static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
-static void frv_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
+static void build_hw_table      (CGEN_CPU_TABLE *);
+static void build_ifield_table  (CGEN_CPU_TABLE *);
+static void build_operand_table (CGEN_CPU_TABLE *);
+static void build_insn_table    (CGEN_CPU_TABLE *);
+static void frv_cgen_rebuild_tables (CGEN_CPU_TABLE *);
 
 /* Subroutine of frv_cgen_cpu_open to look up a mach via its bfd name.  */
 
 static const CGEN_MACH *
-lookup_mach_via_bfd_name (table, name)
-     const CGEN_MACH *table;
-     const char *name;
+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
 {
   while (table->name)
     {
@@ -6176,8 +6172,7 @@ lookup_mach_via_bfd_name (table, name)
 /* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_hw_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_hw_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -6203,8 +6198,7 @@ build_hw_table (cd)
 /* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_ifield_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_ifield_table (CGEN_CPU_TABLE *cd)
 {
   cd->ifld_table = & frv_cgen_ifld_table[0];
 }
@@ -6212,8 +6206,7 @@ build_ifield_table (cd)
 /* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_operand_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_operand_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -6221,8 +6214,7 @@ build_operand_table (cd)
   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
      However each entry is indexed by it's enum so there can be holes in
      the table.  */
-  const CGEN_OPERAND **selected =
-    (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
 
   cd->operand_table.init_entries = init;
   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@@ -6245,12 +6237,11 @@ build_operand_table (cd)
    operand elements to be in the table [which they mightn't be].  */
 
 static void
-build_insn_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_insn_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   const CGEN_IBASE *ib = & frv_cgen_insn_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
 
   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
   for (i = 0; i < MAX_INSNS; ++i)
@@ -6263,8 +6254,7 @@ build_insn_table (cd)
 /* Subroutine of frv_cgen_cpu_open to rebuild the tables.  */
 
 static void
-frv_cgen_rebuild_tables (cd)
-     CGEN_CPU_TABLE *cd;
+frv_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
   unsigned int isas = cd->isas;
@@ -6276,7 +6266,7 @@ frv_cgen_rebuild_tables (cd)
 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
   cd->default_insn_bitsize = UNSET;
   cd->base_insn_bitsize = UNSET;
-  cd->min_insn_bitsize = 65535; /* some ridiculously big number */
+  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
     if (((1 << i) & isas) != 0)
@@ -6288,7 +6278,7 @@ frv_cgen_rebuild_tables (cd)
 	if (cd->default_insn_bitsize == UNSET)
 	  cd->default_insn_bitsize = isa->default_insn_bitsize;
 	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -6297,7 +6287,7 @@ frv_cgen_rebuild_tables (cd)
 	if (cd->base_insn_bitsize == UNSET)
 	  cd->base_insn_bitsize = isa->base_insn_bitsize;
 	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -6409,12 +6399,12 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     }
   va_end (ap);
 
-  /* mach unspecified means "all" */
+  /* Mach unspecified means "all".  */
   if (machs == 0)
     machs = (1 << MAX_MACHS) - 1;
-  /* base mach is always selected */
+  /* Base mach is always selected.  */
   machs |= 1;
-  /* isa unspecified means "all" */
+  /* ISA unspecified means "all".  */
   if (isas == 0)
     isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
@@ -6447,9 +6437,7 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
    MACH_NAME is the bfd name of the mach.  */
 
 CGEN_CPU_DESC
-frv_cgen_cpu_open_1 (mach_name, endian)
-     const char *mach_name;
-     enum cgen_endian endian;
+frv_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
 {
   return frv_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
 			       CGEN_CPU_OPEN_ENDIAN, endian,
@@ -6462,8 +6450,7 @@ frv_cgen_cpu_open_1 (mach_name, endian)
    place as some simulator ports use this but they don't use libopcodes.  */
 
 void
-frv_cgen_cpu_close (cd)
-     CGEN_CPU_DESC cd;
+frv_cgen_cpu_close (CGEN_CPU_DESC cd)
 {
   unsigned int i;
   const CGEN_INSN *insns;
@@ -6472,23 +6459,17 @@ frv_cgen_cpu_close (cd)
     {
       insns = cd->macro_insn_table.init_entries;
       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX ((insns)))
-	    regfree (CGEN_INSN_RX (insns));
-	}
+	if (CGEN_INSN_RX ((insns)))
+	  regfree (CGEN_INSN_RX (insns));
     }
 
   if (cd->insn_table.init_entries)
     {
       insns = cd->insn_table.init_entries;
       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX (insns))
-	    regfree (CGEN_INSN_RX (insns));
-	}
-    }
-
-  
+	if (CGEN_INSN_RX (insns))
+	  regfree (CGEN_INSN_RX (insns));
+    }  
 
   if (cd->macro_insn_table.init_entries)
     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
diff --git a/opcodes/frv-dis.c b/opcodes/frv-dis.c
index cdf0ba6..a82fe2b 100644
--- a/opcodes/frv-dis.c
+++ b/opcodes/frv-dis.c
@@ -1,27 +1,27 @@
 /* Disassembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-dis.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-dis.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
-Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -56,36 +56,28 @@ static int read_insn
   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
    unsigned long *);
 
-/* -- disassembler routines inserted here */
+/* -- disassembler routines inserted here.  */
 
 /* -- dis.c */
-static void print_spr
-  PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned));
-static void print_hi
-  PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
-static void print_lo
-  PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
-
 static void
 print_at (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
-	  PTR dis_info,
+	  void * dis_info,
 	  long reloc_ann ATTRIBUTE_UNUSED,
 	  long value ATTRIBUTE_UNUSED,
 	  bfd_vma pc ATTRIBUTE_UNUSED,
-	  int length ATTRIBUTE_UNUSED
-	  )
+	  int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
+
   (*info->fprintf_func) (info->stream, "@");
 }  
 
 static void
-print_spr (cd, dis_info, names, regno, attrs)
-     CGEN_CPU_DESC cd;
-     PTR dis_info;
-     CGEN_KEYWORD *names;
-     long regno;
-     unsigned int attrs;
+print_spr (CGEN_CPU_DESC cd,
+	   void * dis_info,
+	   CGEN_KEYWORD *names,
+	   long regno,
+	   unsigned int attrs)
 {
   /* Use the register index format for any unnamed registers.  */
   if (cgen_keyword_lookup_value (names, regno) == NULL)
@@ -98,29 +90,25 @@ print_spr (cd, dis_info, names, regno, attrs)
 }
 
 static void
-print_hi (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_hi (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	  void * dis_info,
+	  long value,
+	  unsigned int attrs ATTRIBUTE_UNUSED,
+	  bfd_vma pc ATTRIBUTE_UNUSED,
+	  int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
-  if (value)
-    (*info->fprintf_func) (info->stream, "0x%lx", value);
-  else
-    (*info->fprintf_func) (info->stream, "hi(0x%lx)", value);
+
+  (*info->fprintf_func) (info->stream, value ? "0x%lx" : "hi(0x%lx)", value);
 }
 
 static void
-print_lo (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_lo (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	  void * dis_info,
+	  long value,
+	  unsigned int attrs ATTRIBUTE_UNUSED,
+	  bfd_vma pc ATTRIBUTE_UNUSED,
+	  int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
   if (value)
@@ -132,8 +120,7 @@ print_lo (cd, dis_info, value, attrs, pc, length)
 /* -- */
 
 void frv_cgen_print_operand
-  PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
-           void const *, bfd_vma, int));
+  (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
 
 /* Main entry point for printing operands.
    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@@ -151,16 +138,15 @@ void frv_cgen_print_operand
    the handlers.  */
 
 void
-frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     PTR xinfo;
-     CGEN_FIELDS *fields;
-     void const *attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     int length;
+frv_cgen_print_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   void * xinfo,
+			   CGEN_FIELDS *fields,
+			   void const *attrs ATTRIBUTE_UNUSED,
+			   bfd_vma pc,
+			   int length)
 {
- disassemble_info *info = (disassemble_info *) xinfo;
+  disassemble_info *info = (disassemble_info *) xinfo;
 
   switch (opindex)
     {
@@ -420,8 +406,7 @@ cgen_print_fn * const frv_cgen_print_handlers[] =
 
 
 void
-frv_cgen_init_dis (cd)
-     CGEN_CPU_DESC cd;
+frv_cgen_init_dis (CGEN_CPU_DESC cd)
 {
   frv_cgen_init_opcode_table (cd);
   frv_cgen_init_ibld_table (cd);
@@ -473,7 +458,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 
   /* Print the operand as directed by the attributes.  */
   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
-    ; /* nothing to do */
+    ; /* Nothing to do.  */
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
     (*info->print_address_func) (value, info);
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@@ -555,6 +540,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
+
   if (status != 0)
     {
       (*info->memory_error_func) (status, pc, info);
@@ -659,13 +645,13 @@ print_insn (CGEN_CPU_DESC cd,
 	    length = CGEN_EXTRACT_FN (cd, insn)
 	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 
-	  /* length < 0 -> error */
+	  /* Length < 0 -> error.  */
 	  if (length < 0)
 	    return length;
 	  if (length > 0)
 	    {
 	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
-	      /* length is in bits, result is in bytes */
+	      /* Length is in bits, result is in bytes.  */
 	      return length / 8;
 	    }
 	}
@@ -715,7 +701,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
    Print one instruction from PC on INFO->STREAM.
    Return the size of the instruction (in bytes).  */
 
-typedef struct cpu_desc_list {
+typedef struct cpu_desc_list
+{
   struct cpu_desc_list *next;
   int isa;
   int mach;
@@ -800,7 +787,7 @@ print_insn_frv (bfd_vma pc, disassemble_info *info)
       if (!cd)
 	abort ();
 
-      /* save this away for future reference */
+      /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
       cl->isa = isa;
diff --git a/opcodes/frv-ibld.c b/opcodes/frv-ibld.c
index 2ecedd4..9fe2531 100644
--- a/opcodes/frv-ibld.c
+++ b/opcodes/frv-ibld.c
@@ -1,25 +1,26 @@
 /* Instruction building/extraction support for frv. -*- C -*-
 
-THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
-- the resultant file is machine generated, cgen-ibld.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+   - the resultant file is machine generated, cgen-ibld.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #include "opintl.h"
 #include "safe-ctype.h"
 
-#undef min
+#undef  min
 #define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
+#undef  max
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 /* Used by the ifield rtx function.  */
@@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
   if (length == 0)
     return NULL;
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
 
 #if CGEN_INT_INSN_P
 /* Cover function to store an insn value into an integral insn.  Must go here
- because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
+   because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
       int shift = insn_length - length;
       /* Written this way to avoid undefined behaviour.  */
       CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
       *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
     }
 }
@@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
 {
   unsigned long x;
   int shift;
-#if 0
-  int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
-#endif
+
   x = cgen_get_insn_value (cd, bufp, word_length);
 
   if (CGEN_INSN_LSB0_P)
@@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
       return 1;
     }
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
   return CGEN_INSN_BITSIZE (insn);
 }
 
-/* machine generated code added here */
+/* Machine generated code added here.  */
 
 const char * frv_cgen_insert_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 
 /* Main entry point for operand insertion.
 
@@ -559,12 +547,11 @@ const char * frv_cgen_insert_operand
    resolved during parsing.  */
 
 const char *
-frv_cgen_insert_operand (cd, opindex, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+frv_cgen_insert_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     CGEN_INSN_BYTES_PTR buffer,
+			     bfd_vma pc ATTRIBUTE_UNUSED)
 {
   const char * errmsg = NULL;
   unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@@ -864,8 +851,7 @@ frv_cgen_insert_operand (cd, opindex, fields, buffer, pc)
 }
 
 int frv_cgen_extract_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-           CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 
 /* Main entry point for operand extraction.
    The result is <= 0 for error, >0 for success.
@@ -883,13 +869,12 @@ int frv_cgen_extract_operand
    the handlers.  */
 
 int
-frv_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS * fields;
-     bfd_vma pc;
+frv_cgen_extract_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_EXTRACT_INFO *ex_info,
+			     CGEN_INSN_INT insn_value,
+			     CGEN_FIELDS * fields,
+			     bfd_vma pc)
 {
   /* Assume success (for those operands that are nops).  */
   int length = 1;
@@ -1192,10 +1177,8 @@ cgen_extract_fn * const frv_cgen_extract_handlers[] =
   extract_insn_normal,
 };
 
-int frv_cgen_get_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
-bfd_vma frv_cgen_get_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+int frv_cgen_get_int_operand     (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+bfd_vma frv_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
 
 /* Getting values from cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they return.
@@ -1203,10 +1186,9 @@ bfd_vma frv_cgen_get_vma_operand
    not appropriate.  */
 
 int
-frv_cgen_get_int_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+frv_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   int value;
 
@@ -1464,10 +1446,9 @@ frv_cgen_get_int_operand (cd, opindex, fields)
 }
 
 bfd_vma
-frv_cgen_get_vma_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+frv_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   bfd_vma value;
 
@@ -1724,10 +1705,8 @@ frv_cgen_get_vma_operand (cd, opindex, fields)
   return value;
 }
 
-void frv_cgen_set_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
-void frv_cgen_set_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+void frv_cgen_set_int_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
+void frv_cgen_set_vma_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
 
 /* Stuffing values in cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they accept.
@@ -1735,11 +1714,10 @@ void frv_cgen_set_vma_operand
    not appropriate.  */
 
 void
-frv_cgen_set_int_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     int value;
+frv_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     int value)
 {
   switch (opindex)
     {
@@ -1993,11 +1971,10 @@ frv_cgen_set_int_operand (cd, opindex, fields, value)
 }
 
 void
-frv_cgen_set_vma_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     bfd_vma value;
+frv_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     bfd_vma value)
 {
   switch (opindex)
     {
@@ -2253,8 +2230,7 @@ frv_cgen_set_vma_operand (cd, opindex, fields, value)
 /* Function to call before using the instruction builder tables.  */
 
 void
-frv_cgen_init_ibld_table (cd)
-     CGEN_CPU_DESC cd;
+frv_cgen_init_ibld_table (CGEN_CPU_DESC cd)
 {
   cd->insert_handlers = & frv_cgen_insert_handlers[0];
   cd->extract_handlers = & frv_cgen_extract_handlers[0];
diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c
index d88cd7d..293ae61 100644
--- a/opcodes/frv-opc.c
+++ b/opcodes/frv-opc.c
@@ -34,132 +34,120 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #include "elf/frv.h"
 #include <stdio.h>
 
-static int match_unit
-  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, CGEN_ATTR_VALUE_TYPE));
-static int match_vliw
-  PARAMS ((VLIW_COMBO *, VLIW_COMBO *, int));
-static VLIW_COMBO * add_next_to_vliw
-  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
-static int find_major_in_vliw
-  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
-static int fr400_check_insn_major_constraints
-  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
-static int fr450_check_insn_major_constraints
-  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
-static int fr500_check_insn_major_constraints
-  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
-static int fr550_check_insn_major_constraints
-  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, const CGEN_INSN *));
-static int check_insn_major_constraints
-  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, const CGEN_INSN *));
+/* Returns TRUE if {MAJOR,MACH} is a major branch of the FRV
+   development tree.  */
 
-int
+bfd_boolean
 frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
 {
   switch (mach)
     {
     case bfd_mach_fr400:
       if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6)
-	return 1; /* is a branch */
+	return TRUE;
       break;
     case bfd_mach_fr450:
       if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6)
-	return 1; /* is a branch */
+	return TRUE;
       break;
     default:
       if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6)
-	return 1; /* is a branch */
+	return TRUE;
       break;
     }
 
-  return 0; /* not a branch */
+  return FALSE;
 }
 
-int
+/* Returns TRUE if {MAJOR,MACH} supports floating point insns.  */
+
+bfd_boolean
 frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
 {
   switch (mach)
     {
     case bfd_mach_fr400:
     case bfd_mach_fr450:
-      return 0; /* No float insns */
+      return FALSE;
     default:
       if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8)
-	return 1; /* is a float insn */
+	return TRUE;
       break;
     }
 
-  return 0; /* not a branch */
+  return FALSE;
 }
 
-int
+/* Returns TRUE if {MAJOR,MACH} supports media insns.  */
+
+bfd_boolean
 frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
 {
   switch (mach)
     {
     case bfd_mach_fr400:
       if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2)
-	return 1; /* is a media insn */
+	return TRUE;
       break;
     case bfd_mach_fr450:
       if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6)
-	return 1; /* is a media insn */
+	return TRUE;
       break;
     default:
       if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8)
-	return 1; /* is a media insn */
+	return TRUE;
       break;
     }
 
-  return 0; /* not a branch */
+  return FALSE;
 }
 
-int
+bfd_boolean
 frv_is_branch_insn (const CGEN_INSN *insn)
 {
   if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
 			   bfd_mach_fr400))
-    return 1;
+    return TRUE;
   if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
 			   bfd_mach_fr450))
-    return 1;
+    return TRUE;
   if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
 			   bfd_mach_fr500))
-    return 1;
+    return TRUE;
 
-  return 0;
+  return FALSE;
 }
 
-int
+bfd_boolean
 frv_is_float_insn (const CGEN_INSN *insn)
 {
   if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
 			  bfd_mach_fr400))
-    return 1;
+    return TRUE;
   if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
 			  bfd_mach_fr450))
-    return 1;
+    return TRUE;
   if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
 			  bfd_mach_fr500))
-    return 1;
+    return TRUE;
 
-  return 0;
+  return FALSE;
 }
 
-int
+bfd_boolean
 frv_is_media_insn (const CGEN_INSN *insn)
 {
   if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
 			  bfd_mach_fr400))
-    return 1;
+    return TRUE;
   if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
 			  bfd_mach_fr450))
-    return 1;
+    return TRUE;
   if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
 			  bfd_mach_fr500))
-    return 1;
+    return TRUE;
 
-  return 0;
+  return FALSE;
 }
 
 /* This table represents the allowable packing for vliw insns for the fr400.
@@ -397,10 +385,10 @@ frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags)
     }
 }
 
-/* Return 1 if unit1 is a match for unit2.
+/* Return TRUE if unit1 is a match for unit2.
    Unit1 comes from the insn's UNIT attribute. unit2 comes from one of the
    *_allowed_vliw tables above.  */
-static int
+static bfd_boolean
 match_unit (FRV_VLIW *vliw,
 	    CGEN_ATTR_VALUE_TYPE unit1, CGEN_ATTR_VALUE_TYPE unit2)
 {
@@ -408,9 +396,9 @@ match_unit (FRV_VLIW *vliw,
   unit1 = vliw->unit_mapping[unit1];
 
   if (unit1 == unit2)
-    return 1;
+    return TRUE;
   if (unit1 < unit2)
-    return 0;
+    return FALSE;
 
   switch (unit1)
     {
@@ -420,36 +408,34 @@ match_unit (FRV_VLIW *vliw,
       /* The 01 versions of these units are within 2 enums of the 0 or 1
 	 versions.  */
       if (unit1 - unit2 <= 2)
-	return 1;
+	return TRUE;
       break;
     case UNIT_IALL:
     case UNIT_FMALL:
       /* The ALL versions of these units are within 5 enums of the 0, 1, 2 or 3
 	 versions.  */
       if (unit1 - unit2 <= 5)
-	return 1;
+	return TRUE;
       break;
     default:
       break;
     }
 
-  return 0;
+  return FALSE;
 }
 
-/* Return 1 if the vliws match, 0 otherwise.  */
+/* Return TRUE if the vliws match, FALSE otherwise.  */
 
-static int
+static bfd_boolean
 match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size)
 {
   int i;
 
   for (i = 0; i < vliw_size; ++i)
-    {
-      if ((*vliw1)[i] != (*vliw2)[i])
-	return 0;
-    }
+    if ((*vliw1)[i] != (*vliw2)[i])
+      return FALSE;
 
-  return 1;
+  return TRUE;
 }
 
 /* Find the next vliw vliw in the table that can accomodate the new insn.
@@ -466,7 +452,7 @@ add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
     {
       fprintf (stderr, "frv-opc.c line %d: bad vliw->next_slot value.\n",
 	       __LINE__);
-      abort (); /* Should never happen */
+      abort (); /* Should never happen.  */
     }
 
   /* The table is sorted by units allowed within slots, so vliws with
@@ -483,28 +469,26 @@ add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
   return NULL;
 }
 
-/* Look for the given major insn type in the given vliw. Return 1 if found,
-   return 0 otherwise.  */
+/* Look for the given major insn type in the given vliw.
+   Returns TRUE if found, FALSE otherwise.  */
 
-static int
+static bfd_boolean
 find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
 {
   int i;
 
   for (i = 0; i < vliw->next_slot; ++i)
     if (vliw->major[i] == major)
-      return 1;
+      return TRUE;
 
-  return 0;
+  return FALSE;
 }
 
 /* Check for constraints between the insns in the vliw due to major insn
    types.  */
 
-static int
-fr400_check_insn_major_constraints (
-  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
-)
+static bfd_boolean
+fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
 {
   /* In the cpu file, all media insns are represented as being allowed in
      both media units. This makes it easier since this is the case for fr500.
@@ -516,17 +500,15 @@ fr400_check_insn_major_constraints (
       return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1)
 	&&   ! find_major_in_vliw (vliw, FR400_MAJOR_M_2);
     case FR400_MAJOR_M_1:
-      return !find_major_in_vliw (vliw, FR400_MAJOR_M_2);
+      return ! find_major_in_vliw (vliw, FR400_MAJOR_M_2);
     default:
       break;
     }
-  return 1;
+  return TRUE;
 }
 
-static int
-fr450_check_insn_major_constraints (
-  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
-)
+static bfd_boolean
+fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
 {
   CGEN_ATTR_VALUE_TYPE other_major;
 
@@ -536,7 +518,7 @@ fr450_check_insn_major_constraints (
   /* (M4, M5) and (M4, M6) are allowed.  */
   if (other_major == FR450_MAJOR_M_4)
     if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6)
-      return 1;
+      return TRUE;
 
   /* Otherwise, instructions in even-numbered media categories cannot be
      executed in parallel with other media instructions.  */
@@ -556,38 +538,37 @@ fr450_check_insn_major_constraints (
 	       || other_major == FR450_MAJOR_M_6);
 
     default:
-      return 1;
+      return TRUE;
     }
 }
 
-static int
-find_unit_in_vliw (
-  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit
-)
+static bfd_boolean
+find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
 {
   int i;
+
   for (i = 0; i < vliw->next_slot; ++i)
     if (CGEN_INSN_ATTR_VALUE (vliw->insn[i], CGEN_INSN_UNIT) == unit)
-      return 1;
+      return TRUE;
 
-  return 0; /* not found */
+  return FALSE; /* Not found.  */
 }
 
-static int
-find_major_in_slot (
-  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, CGEN_ATTR_VALUE_TYPE slot
-)
+static bfd_boolean
+find_major_in_slot (FRV_VLIW *vliw,
+		    CGEN_ATTR_VALUE_TYPE major,
+		    CGEN_ATTR_VALUE_TYPE slot)
 {
   int i;
 
   for (i = 0; i < vliw->next_slot; ++i)
     if (vliw->major[i] == major && (*vliw->current_vliw)[i] == slot)
-      return 1;
+      return TRUE;
 
-  return 0;
+  return FALSE;
 }
 
-static int
+static bfd_boolean
 fr550_find_media_in_vliw (FRV_VLIW *vliw)
 {
   int i;
@@ -603,13 +584,13 @@ fr550_find_media_in_vliw (FRV_VLIW *vliw)
 	  || CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_1)
 	continue;
 
-      return 1; /* found one */
+      return TRUE; /* Found one.  */
     }
 
-  return 0;
+  return FALSE;
 }
 
-static int
+static bfd_boolean
 fr550_find_float_in_vliw (FRV_VLIW *vliw)
 {
   int i;
@@ -623,16 +604,16 @@ fr550_find_float_in_vliw (FRV_VLIW *vliw)
       if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_FNOP)
 	continue;
 
-      return 1; /* found one */
+      return TRUE; /* Found one.  */
     }
 
-  return 0;
+  return FALSE;
 }
 
-static int
-fr550_check_insn_major_constraints (
-  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, const CGEN_INSN *insn
-)
+static bfd_boolean
+fr550_check_insn_major_constraints (FRV_VLIW *vliw,
+				    CGEN_ATTR_VALUE_TYPE major,
+				    const CGEN_INSN *insn)
 {
   CGEN_ATTR_VALUE_TYPE unit;
   CGEN_ATTR_VALUE_TYPE slot = (*vliw->current_vliw)[vliw->next_slot];
@@ -646,8 +627,8 @@ fr550_check_insn_major_constraints (
       break;
     case UNIT_FM2:
     case UNIT_FM3:
-      /* Floating point insns other than FNOP in slot f2 or f3 cannot coexist with
-	 media insns.  */
+      /* Floating point insns other than FNOP in slot f2 or f3 cannot coexist
+	 with media insns.  */
       if (major >= FR550_MAJOR_F_1 && major <= FR550_MAJOR_F_4
 	  && CGEN_INSN_NUM (insn) != FRV_INSN_FNOP)
 	return ! fr550_find_media_in_vliw (vliw);
@@ -657,30 +638,31 @@ fr550_check_insn_major_constraints (
 	  && CGEN_INSN_NUM (insn) != FRV_INSN_MNOP)
 	return ! fr550_find_float_in_vliw (vliw);
       /* F-2 in slot f2 or f3 cannot coexist with F-2 or F-4 in slot f1 or f2
-	 respectively.
-       */
+	 respectively.  */
       if (major == FR550_MAJOR_F_2)
-	return ! find_major_in_slot (vliw, FR550_MAJOR_F_2, slot - (UNIT_FM2 - UNIT_FM0))
-	  &&   ! find_major_in_slot (vliw, FR550_MAJOR_F_4, slot - (UNIT_FM2 - UNIT_FM0));
+	return ! find_major_in_slot (vliw, FR550_MAJOR_F_2,
+				     slot - (UNIT_FM2 - UNIT_FM0))
+	  &&   ! find_major_in_slot (vliw, FR550_MAJOR_F_4,
+				     slot - (UNIT_FM2 - UNIT_FM0));
       /* M-2 or M-5 in slot m2 or m3 cannot coexist with M-2 in slot m1 or m2
 	 respectively.  */
       if (major == FR550_MAJOR_M_2 || major == FR550_MAJOR_M_5)
-	return ! find_major_in_slot (vliw, FR550_MAJOR_M_2, slot - (UNIT_FM2 - UNIT_FM0));
+	return ! find_major_in_slot (vliw, FR550_MAJOR_M_2,
+				     slot - (UNIT_FM2 - UNIT_FM0));
       /* M-4 in slot m2 or m3 cannot coexist with M-4 in slot m1 or m2
 	 respectively.  */
       if (major == FR550_MAJOR_M_4)
-	return ! find_major_in_slot (vliw, FR550_MAJOR_M_4, slot - (UNIT_FM2 - UNIT_FM0));
+	return ! find_major_in_slot (vliw, FR550_MAJOR_M_4,
+				     slot - (UNIT_FM2 - UNIT_FM0));
       break;
     default:
       break;
     }
-  return 1; /* all ok */
+  return TRUE; /* All OK.  */
 }
 
-static int
-fr500_check_insn_major_constraints (
-  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
-)
+static bfd_boolean
+fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
 {
   /* TODO: A table might be faster for some of the more complex instances
      here.  */
@@ -699,7 +681,7 @@ fr500_check_insn_major_constraints (
     case FR500_MAJOR_F_4:
     case FR500_MAJOR_F_8:
     case FR500_MAJOR_M_8:
-      return 1; /* OK */
+      return TRUE; /* OK */
     case FR500_MAJOR_I_2:
       /* Cannot coexist with I-3 insn.  */
       return ! find_major_in_vliw (vliw, FR500_MAJOR_I_3);
@@ -783,35 +765,33 @@ fr500_check_insn_major_constraints (
       abort ();
       break;
     }
-  return 1;
+  return TRUE;
 }
 
-static int
-check_insn_major_constraints (
-  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, const CGEN_INSN *insn
-)
+static bfd_boolean
+check_insn_major_constraints (FRV_VLIW *vliw,
+			      CGEN_ATTR_VALUE_TYPE major,
+			      const CGEN_INSN *insn)
 {
-  int rc;
   switch (vliw->mach)
     {
     case bfd_mach_fr400:
-      rc = fr400_check_insn_major_constraints (vliw, major);
-      break;
+      return fr400_check_insn_major_constraints (vliw, major);
+
     case bfd_mach_fr450:
-      rc = fr450_check_insn_major_constraints (vliw, major);
-      break;
+      return fr450_check_insn_major_constraints (vliw, major);
+
     case bfd_mach_fr550:
-      rc = fr550_check_insn_major_constraints (vliw, major, insn);
-      break;
+      return fr550_check_insn_major_constraints (vliw, major, insn);
+
     default:
-      rc = fr500_check_insn_major_constraints (vliw, major);
-      break;
+      return fr500_check_insn_major_constraints (vliw, major);
     }
-  return rc;
 }
 
-/* Add in insn to the VLIW vliw if possible. Return 0 if successful,
-   non-zero otherwise.  */
+/* Add in insn to the VLIW vliw if possible.
+   Return 0 if successful, non-zero otherwise.  */
+
 int
 frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
 {
@@ -832,7 +812,7 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
     {
       fprintf (stderr, "frv-opc.c line %d: bad insn unit.\n",
 	       __LINE__);
-      abort (); /* no UNIT specified for this insn in frv.cpu  */
+      abort (); /* No UNIT specified for this insn in frv.cpu.  */
     }
 
   switch (vliw->mach)
@@ -888,22 +868,21 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
   return 1;
 }
 
-int
-spr_valid (regno)
-     long regno;
+bfd_boolean
+spr_valid (long regno)
 {
-  if (regno < 0)     return 0;
-  if (regno <= 4095) return 1;
-  return 0;
+  if (regno < 0)     return FALSE;
+  if (regno <= 4095) return TRUE;
+  return FALSE;
 }
 /* -- */
 /* The hash functions are recorded here to help keep assembler code out of
    the disassembler and vice versa.  */
 
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static int asm_hash_insn_p        (const CGEN_INSN *);
+static unsigned int asm_hash_insn (const char *);
+static int dis_hash_insn_p        (const CGEN_INSN *);
+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
 
 /* Instruction formats.  */
 
@@ -6223,14 +6202,10 @@ dis_hash_insn (buf, value)
   return CGEN_DIS_HASH (buf, value);
 }
 
-static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
-
 /* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
 
 static void
-set_fields_bitsize (fields, size)
-     CGEN_FIELDS *fields;
-     int size;
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
 {
   CGEN_FIELDS_BITSIZE (fields) = size;
 }
@@ -6239,15 +6214,15 @@ set_fields_bitsize (fields, size)
    This plugs the opcode entries and macro instructions into the cpu table.  */
 
 void
-frv_cgen_init_opcode_table (cd)
-     CGEN_CPU_DESC cd;
+frv_cgen_init_opcode_table (CGEN_CPU_DESC cd)
 {
   int i;
   int num_macros = (sizeof (frv_cgen_macro_insn_table) /
 		    sizeof (frv_cgen_macro_insn_table[0]));
   const CGEN_IBASE *ib = & frv_cgen_macro_insn_table[0];
   const CGEN_OPCODE *oc = & frv_cgen_macro_insn_opcode_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
+
   memset (insns, 0, num_macros * sizeof (CGEN_INSN));
   for (i = 0; i < num_macros; ++i)
     {
diff --git a/opcodes/frv-opc.h b/opcodes/frv-opc.h
index e16c4fe..50e1041 100644
--- a/opcodes/frv-opc.h
+++ b/opcodes/frv-opc.h
@@ -38,29 +38,30 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* Vliw support.  */
 #define FRV_VLIW_SIZE 8 /* fr550 has largest vliw size of 8.  */
 #define PAD_VLIW_COMBO ,UNIT_NIL,UNIT_NIL,UNIT_NIL,UNIT_NIL
+
 typedef CGEN_ATTR_VALUE_TYPE VLIW_COMBO[FRV_VLIW_SIZE];
 
 typedef struct
 {
-  int                   next_slot;
-  int                   constraint_violation;
-  unsigned long         mach;
-  unsigned long         elf_flags;
-  CGEN_ATTR_VALUE_TYPE *unit_mapping;
-  VLIW_COMBO           *current_vliw;
-  CGEN_ATTR_VALUE_TYPE  major[FRV_VLIW_SIZE];
-  const CGEN_INSN*      insn[FRV_VLIW_SIZE];
+  int                    next_slot;
+  int                    constraint_violation;
+  unsigned long          mach;
+  unsigned long          elf_flags;
+  CGEN_ATTR_VALUE_TYPE * unit_mapping;
+  VLIW_COMBO *           current_vliw;
+  CGEN_ATTR_VALUE_TYPE   major[FRV_VLIW_SIZE];
+  const CGEN_INSN *      insn[FRV_VLIW_SIZE];
 } FRV_VLIW;
 
-int frv_is_branch_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long));
-int frv_is_float_major  PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long));
-int frv_is_media_major  PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long));
-int frv_is_branch_insn  PARAMS ((const CGEN_INSN *));
-int frv_is_float_insn   PARAMS ((const CGEN_INSN *));
-int frv_is_media_insn   PARAMS ((const CGEN_INSN *));
-void frv_vliw_reset     PARAMS ((FRV_VLIW *, unsigned long mach, unsigned long elf_flags));
-int frv_vliw_add_insn   PARAMS ((FRV_VLIW *, const CGEN_INSN *));
-int spr_valid           PARAMS ((long));
+int frv_is_branch_major (CGEN_ATTR_VALUE_TYPE, unsigned long);
+int frv_is_float_major  (CGEN_ATTR_VALUE_TYPE, unsigned long);
+int frv_is_media_major  (CGEN_ATTR_VALUE_TYPE, unsigned long);
+int frv_is_branch_insn  (const CGEN_INSN *);
+int frv_is_float_insn   (const CGEN_INSN *);
+int frv_is_media_insn   (const CGEN_INSN *);
+void frv_vliw_reset     (FRV_VLIW *, unsigned long, unsigned long);
+int frv_vliw_add_insn   (FRV_VLIW *, const CGEN_INSN *);
+int spr_valid           (long);
 /* -- */
 /* Enum declaration for frv instruction types.  */
 typedef enum cgen_insn_type {
diff --git a/opcodes/h8300-dis.c b/opcodes/h8300-dis.c
index 8b33d86..9c77e91 100644
--- a/opcodes/h8300-dis.c
+++ b/opcodes/h8300-dis.c
@@ -1,5 +1,5 @@
 /* Disassemble h8300 instructions.
-   Copyright 1993, 1994, 1996, 1998, 2000, 2001, 2002, 2003, 2004
+   Copyright 1993, 1994, 1996, 1998, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
@@ -14,7 +14,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #define DEFINE_TABLE
 
@@ -33,23 +34,11 @@ struct h8_instruction
 
 struct h8_instruction *h8_instructions;
 
-static void bfd_h8_disassemble_init PARAMS ((void));
-static void print_one_arg PARAMS ((disassemble_info *, bfd_vma, op_type,
-				   int, int, int, int, const char **, int));
-static unsigned int bfd_h8_disassemble PARAMS ((bfd_vma, 
-						disassemble_info *, 
-						int));
-static void extract_immediate PARAMS ((FILE *, 
-				       op_type, int, 
-				       unsigned char *,
-				       int *, int *,
-				       const struct h8_opcode *));
-
 /* Run through the opcodes and sort them into order to make them easy
    to disassemble.  */
 
 static void
-bfd_h8_disassemble_init ()
+bfd_h8_disassemble_init (void)
 {
   unsigned int i;
   unsigned int nopcodes;
@@ -58,8 +47,7 @@ bfd_h8_disassemble_init ()
 
   nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode);
 
-  h8_instructions = (struct h8_instruction *)
-    xmalloc (nopcodes * sizeof (struct h8_instruction));
+  h8_instructions = xmalloc (nopcodes * sizeof (struct h8_instruction));
 
   for (p = h8_opcodes, pi = h8_instructions; p->name; p++, pi++)
     {
@@ -97,13 +85,13 @@ bfd_h8_disassemble_init ()
 }
 
 static void
-extract_immediate (stream, looking_for, thisnib, data, cst, len, q)
-     FILE *stream;
-     op_type looking_for;
-     int thisnib;
-     unsigned char *data;
-     int *cst, *len;
-     const struct h8_opcode *q;
+extract_immediate (FILE *stream,
+		   op_type looking_for,
+		   int thisnib,
+		   unsigned char *data,
+		   int *cst,
+		   int *len,
+		   const struct h8_opcode *q)
 {
   switch (looking_for & SIZE)
     {
@@ -114,35 +102,37 @@ extract_immediate (stream, looking_for, thisnib, data, cst, len, q)
       /* DISP2 special treatment.  */
       if ((looking_for & MODE) == DISP)
 	{
-	  if (OP_KIND (q->how) == O_MOVAB ||
-	      OP_KIND (q->how) == O_MOVAW ||
-	      OP_KIND (q->how) == O_MOVAL)
+	  if (OP_KIND (q->how) == O_MOVAB
+	      || OP_KIND (q->how) == O_MOVAW
+	      || OP_KIND (q->how) == O_MOVAL)
 	    {
 	      /* Handling for mova insn.  */
-	      switch (q->args.nib[0] & MODE) {
-	      case INDEXB:
-	      default:
-		break;
-	      case INDEXW:
-		*cst *= 2;
-		break;
-	      case INDEXL:
-		*cst *= 4;
-		break;
-	      }
+	      switch (q->args.nib[0] & MODE)
+		{
+		case INDEXB:
+		default:
+		  break;
+		case INDEXW:
+		  *cst *= 2;
+		  break;
+		case INDEXL:
+		  *cst *= 4;
+		  break;
+		}
 	    }
 	  else
 	    {
 	      /* Handling for non-mova insn.  */
-	      switch (OP_SIZE (q->how)) {
-	      default: break;
-	      case SW:
-		*cst *= 2;
-		break;
-	      case SL:
-		*cst *= 4;
-		break;
-	      }
+	      switch (OP_SIZE (q->how))
+		{
+		default: break;
+		case SW:
+		  *cst *= 2;
+		  break;
+		case SL:
+		  *cst *= 4;
+		  break;
+		}
 	    }
 	}
       break;
@@ -156,7 +146,7 @@ extract_immediate (stream, looking_for, thisnib, data, cst, len, q)
       *cst = (data[0] << 8) + data [1];
 #if 0
       if ((looking_for & SIZE) == L_16)
-	*cst = (short) *cst;	/* sign extend */
+	*cst = (short) *cst;	/* Sign extend.  */
 #endif
       break;
     case L_32:
@@ -192,31 +182,25 @@ static const char *cregnames[] =
 };
 
 static void
-print_one_arg (info, addr, x, cst, cstlen, rdisp_n, rn, pregnames, len)
-     disassemble_info *info;
-     bfd_vma addr;
-     op_type x;
-     int cst, cstlen, rdisp_n, rn;
-     const char **pregnames;
-     int len;
+print_one_arg (disassemble_info *info,
+	       bfd_vma addr,
+	       op_type x,
+	       int cst,
+	       int cstlen,
+	       int rdisp_n,
+	       int rn,
+	       const char **pregnames,
+	       int len)
 {
-  void *stream = info->stream;
+  void * stream = info->stream;
   fprintf_ftype outfn = info->fprintf_func;
 
-  if ((x & SIZE) == L_3 ||
-      (x & SIZE) == L_3NZ)
-    {
-      outfn (stream, "#0x%x", (unsigned) cst);
-    }
+  if ((x & SIZE) == L_3 || (x & SIZE) == L_3NZ)
+    outfn (stream, "#0x%x", (unsigned) cst);
   else if ((x & MODE) == IMM)
-    {
-      outfn (stream, "#0x%x", (unsigned) cst);
-    }
-  else if ((x & MODE) == DBIT  ||
-	   (x & MODE) == KBIT)
-    {
-      outfn (stream, "#%d", (unsigned) cst);
-    }
+    outfn (stream, "#0x%x", (unsigned) cst);
+  else if ((x & MODE) == DBIT || (x & MODE) == KBIT)
+    outfn (stream, "#%d", (unsigned) cst);
   else if ((x & MODE) == CONST_2)
     outfn (stream, "#2");
   else if ((x & MODE) == CONST_4)
@@ -262,33 +246,26 @@ print_one_arg (info, addr, x, cst, cstlen, rdisp_n, rn, pregnames, len)
 	}
     }
   else if ((x & MODE) == POSTINC)
-    {
-      outfn (stream, "@%s+", pregnames[rn]);
-    }
+    outfn (stream, "@%s+", pregnames[rn]);
+
   else if ((x & MODE) == POSTDEC)
-    {
-      outfn (stream, "@%s-", pregnames[rn]);
-    }
+    outfn (stream, "@%s-", pregnames[rn]);
+
   else if ((x & MODE) == PREINC)
-    {
-      outfn (stream, "@+%s", pregnames[rn]);
-    }
+    outfn (stream, "@+%s", pregnames[rn]);
+
   else if ((x & MODE) == PREDEC)
-    {
-      outfn (stream, "@-%s", pregnames[rn]);
-    }
+    outfn (stream, "@-%s", pregnames[rn]);
+
   else if ((x & MODE) == IND)
-    {
-      outfn (stream, "@%s", pregnames[rn]);
-    }
+    outfn (stream, "@%s", pregnames[rn]);
+
   else if ((x & MODE) == ABS || (x & ABSJMP))
-    {
-      outfn (stream, "@0x%x:%d", (unsigned) cst, cstlen);
-    }
+    outfn (stream, "@0x%x:%d", (unsigned) cst, cstlen);
+
   else if ((x & MODE) == MEMIND)
-    {
-      outfn (stream, "@@%d (0x%x)", cst, cst);
-    }
+    outfn (stream, "@@%d (0x%x)", cst, cst);
+
   else if ((x & MODE) == VECIND)
     {
       /* FIXME Multiplier should be 2 or 4, depending on processor mode,
@@ -316,53 +293,40 @@ print_one_arg (info, addr, x, cst, cstlen, rdisp_n, rn, pregnames, len)
 	}
     }
   else if ((x & MODE) == DISP)
-    {
-      outfn (stream, "@(0x%x:%d,%s)", cst, cstlen, 
-	       pregnames[rdisp_n]);
-    }
+    outfn (stream, "@(0x%x:%d,%s)", cst, cstlen, pregnames[rdisp_n]);
+
   else if ((x & MODE) == INDEXB)
-    {
-      /* Always take low half of reg.  */
-      outfn (stream, "@(0x%x:%d,%s.b)", cst, cstlen, 
-	     regnames[rdisp_n < 8 ? rdisp_n + 8 : rdisp_n]);
-    }
+    /* Always take low half of reg.  */
+    outfn (stream, "@(0x%x:%d,%s.b)", cst, cstlen, 
+	   regnames[rdisp_n < 8 ? rdisp_n + 8 : rdisp_n]);
+
   else if ((x & MODE) == INDEXW)
-    {
-      /* Always take low half of reg.  */
-      outfn (stream, "@(0x%x:%d,%s.w)", cst, cstlen, 
-	       wregnames[rdisp_n < 8 ? rdisp_n : rdisp_n - 8]);
-    }
+    /* Always take low half of reg.  */
+    outfn (stream, "@(0x%x:%d,%s.w)", cst, cstlen, 
+	   wregnames[rdisp_n < 8 ? rdisp_n : rdisp_n - 8]);
+
   else if ((x & MODE) == INDEXL)
-    {
-      outfn (stream, "@(0x%x:%d,%s.l)", cst, cstlen, 
-	       lregnames[rdisp_n]);
-    }
+    outfn (stream, "@(0x%x:%d,%s.l)", cst, cstlen, lregnames[rdisp_n]);
+
   else if (x & CTRL)
-    {
-      outfn (stream, cregnames[rn]);
-    }
+    outfn (stream, cregnames[rn]);
+
   else if ((x & MODE) == CCR)
-    {
-      outfn (stream, "ccr");
-    }
+    outfn (stream, "ccr");
+
   else if ((x & MODE) == EXR)
-    {
-      outfn (stream, "exr");
-    }
+    outfn (stream, "exr");
+
   else if ((x & MODE) == MACREG)
-    {
-      outfn (stream, "mac%c", cst ? 'l' : 'h');
-    }
+    outfn (stream, "mac%c", cst ? 'l' : 'h');
+
   else
     /* xgettext:c-format */
     outfn (stream, _("Hmmmm 0x%x"), x);
 }
 
 static unsigned int
-bfd_h8_disassemble (addr, info, mach)
-     bfd_vma addr;
-     disassemble_info *info;
-     int mach;
+bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
 {
   /* Find the first entry in the table for this opcode.  */
   int regno[3] = { 0, 0, 0 };
@@ -501,12 +465,12 @@ bfd_h8_disassemble (addr, info, mach)
 
 		  cst[opnr] = (thisnib & 0x8) ? 2 : 1;
 		}
-	      else if ((looking_for & MODE) == DISP  ||
-		       (looking_for & MODE) == ABS   ||
-		       (looking_for & MODE) == PCREL ||
-		       (looking_for & MODE) == INDEXB ||
-		       (looking_for & MODE) == INDEXW ||
-		       (looking_for & MODE) == INDEXL)
+	      else if ((looking_for & MODE) == DISP
+		       || (looking_for & MODE) == ABS
+		       || (looking_for & MODE) == PCREL
+		       || (looking_for & MODE) == INDEXB
+		       || (looking_for & MODE) == INDEXW
+		       || (looking_for & MODE) == INDEXL)
 		{
 		  extract_immediate (stream, looking_for, thisnib, 
 				     data + len / 2, cst + opnr, 
@@ -515,36 +479,36 @@ bfd_h8_disassemble (addr, info, mach)
 		  if (q->how == O (O_BRAS, SB))
 		    cst[opnr] -= 1;
 		}
-	      else if ((looking_for & MODE) == REG     ||
-		       (looking_for & MODE) == LOWREG  ||
-		       (looking_for & MODE) == IND     ||
-		       (looking_for & MODE) == PREINC  ||
-		       (looking_for & MODE) == POSTINC ||
-		       (looking_for & MODE) == PREDEC  ||
-		       (looking_for & MODE) == POSTDEC)
+	      else if ((looking_for & MODE) == REG
+		       || (looking_for & MODE) == LOWREG
+		       || (looking_for & MODE) == IND
+		       || (looking_for & MODE) == PREINC
+		       || (looking_for & MODE) == POSTINC
+		       || (looking_for & MODE) == PREDEC
+		       || (looking_for & MODE) == POSTDEC)
 		{
 		  regno[opnr] = thisnib;
 		}
-	      else if (looking_for & CTRL)	/* Control Register */
+	      else if (looking_for & CTRL)	/* Control Register.  */
 		{
 		  thisnib &= 7;
-		  if (((looking_for & MODE) == CCR  && (thisnib != C_CCR))  ||
-		      ((looking_for & MODE) == EXR  && (thisnib != C_EXR))  ||
-		      ((looking_for & MODE) == MACH && (thisnib != C_MACH)) ||
-		      ((looking_for & MODE) == MACL && (thisnib != C_MACL)) ||
-		      ((looking_for & MODE) == VBR  && (thisnib != C_VBR))  ||
-		      ((looking_for & MODE) == SBR  && (thisnib != C_SBR)))
+		  if (((looking_for & MODE) == CCR  && (thisnib != C_CCR))
+		      || ((looking_for & MODE) == EXR  && (thisnib != C_EXR))
+		      || ((looking_for & MODE) == MACH && (thisnib != C_MACH))
+		      || ((looking_for & MODE) == MACL && (thisnib != C_MACL))
+		      || ((looking_for & MODE) == VBR  && (thisnib != C_VBR))
+		      || ((looking_for & MODE) == SBR  && (thisnib != C_SBR)))
 		    goto fail;
-		  if (((looking_for & MODE) == CCR_EXR && 
-		       (thisnib != C_CCR && thisnib != C_EXR)) ||
-		      ((looking_for & MODE) == VBR_SBR && 
-		       (thisnib != C_VBR && thisnib != C_SBR)) ||
-		      ((looking_for & MODE) == MACREG && 
-		       (thisnib != C_MACH && thisnib != C_MACL)))
+		  if (((looking_for & MODE) == CCR_EXR
+		       && (thisnib != C_CCR && thisnib != C_EXR))
+		      || ((looking_for & MODE) == VBR_SBR
+			  && (thisnib != C_VBR && thisnib != C_SBR))
+		      || ((looking_for & MODE) == MACREG
+			  && (thisnib != C_MACH && thisnib != C_MACL)))
 		    goto fail;
-		  if (((looking_for & MODE) == CC_EX_VB_SB && 
-		       (thisnib != C_CCR && thisnib != C_EXR &&
-			thisnib != C_VBR && thisnib != C_SBR)))
+		  if (((looking_for & MODE) == CC_EX_VB_SB
+		       && (thisnib != C_CCR && thisnib != C_EXR
+			   && thisnib != C_VBR && thisnib != C_SBR)))
 		    goto fail;
 
 		  regno[opnr] = thisnib;
@@ -559,8 +523,8 @@ bfd_h8_disassemble (addr, info, mach)
 		  cst[opnr] = thisnib;
 		  cstlen[opnr] = 4;
 		}
-	      else if ((looking_for & SIZE) == L_16 ||
-		       (looking_for & SIZE) == L_16U)
+	      else if ((looking_for & SIZE) == L_16
+		       || (looking_for & SIZE) == L_16U)
 		{
 		  cst[opnr] = (data[len / 2]) * 256 + data[(len + 2) / 2];
 		  cstlen[opnr] = 16;
@@ -622,8 +586,8 @@ bfd_h8_disassemble (addr, info, mach)
 		  cstlen[opnr] = 8;
 		  cst[opnr] = data[len / 2];
 		}
-	      else if ((looking_for & SIZE) == L_3 ||
-		       (looking_for & SIZE) == L_3NZ)
+	      else if ((looking_for & SIZE) == L_3
+		       || (looking_for & SIZE) == L_3NZ)
 		{
 		  cst[opnr] = thisnib & 0x7;
 		  if (cst[opnr] == 0 && (looking_for & SIZE) == L_3NZ)
@@ -670,10 +634,8 @@ bfd_h8_disassemble (addr, info, mach)
 		      if (regno[0] == 0)
 			outfn (stream, "er%d", regno[1]);
 		      else
-			{
-			  outfn (stream, "er%d-er%d", regno[1] - regno[0],
-				 regno[1]);
-			}
+			outfn (stream, "er%d-er%d", regno[1] - regno[0],
+			       regno[1]);
 		      return qi->length;
 		    }
 		  if (strncmp (q->name, "mova", 4) == 0)
@@ -709,9 +671,9 @@ bfd_h8_disassemble (addr, info, mach)
 		    int nargs;
 
 		    /* Special case handling for the adds and subs instructions
-		       since in H8 mode thay can only take the r0-r7 registers but
-		       in other (higher) modes they can take the er0-er7 registers
-		       as well.  */
+		       since in H8 mode thay can only take the r0-r7 registers
+		       but in other (higher) modes they can take the er0-er7
+		       registers as well.  */
 		    if (strcmp (qi->opcode->name, "adds") == 0
 			|| strcmp (qi->opcode->name, "subs") == 0)
 		      {
@@ -720,7 +682,7 @@ bfd_h8_disassemble (addr, info, mach)
 		      }
 
 		    for (nargs = 0; 
-			 nargs < 3 && args[nargs] != (op_type) E; 
+			 nargs < 3 && args[nargs] != (op_type) E;
 			 nargs++)
 		      {
 			int x = args[nargs];
@@ -758,25 +720,19 @@ bfd_h8_disassemble (addr, info, mach)
 }
 
 int
-print_insn_h8300 (addr, info)
-     bfd_vma addr;
-     disassemble_info *info;
+print_insn_h8300 (bfd_vma addr, disassemble_info *info)
 {
   return bfd_h8_disassemble (addr, info, 0);
 }
 
 int
-print_insn_h8300h (addr, info)
-     bfd_vma addr;
-     disassemble_info *info;
+print_insn_h8300h (bfd_vma addr, disassemble_info *info)
 {
   return bfd_h8_disassemble (addr, info, 1);
 }
 
 int
-print_insn_h8300s (addr, info)
-     bfd_vma addr;
-     disassemble_info *info;
+print_insn_h8300s (bfd_vma addr, disassemble_info *info)
 {
   return bfd_h8_disassemble (addr, info, 2);
 }
diff --git a/opcodes/h8500-dis.c b/opcodes/h8500-dis.c
index 90839b0..bc56f51 100644
--- a/opcodes/h8500-dis.c
+++ b/opcodes/h8500-dis.c
@@ -1,5 +1,6 @@
 /* Disassemble h8500 instructions.
-   Copyright 1993, 1998, 2000, 2001, 2002, 2004 Free Software Foundation, Inc.
+   Copyright 1993, 1998, 2000, 2001, 2002, 2004, 2005
+   Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -13,7 +14,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <stdio.h>
 
@@ -30,8 +32,6 @@
 
 #include <setjmp.h>
 
-static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *));
-
 struct private
 {
   /* Points to first byte not fetched.  */
@@ -49,9 +49,7 @@ struct private
    ? 1 : fetch_data ((info), (addr)))
 
 static int
-fetch_data (info, addr)
-     struct disassemble_info *info;
-     bfd_byte *addr;
+fetch_data (struct disassemble_info *info, bfd_byte *addr)
 {
   int status;
   struct private *priv = (struct private *) info->private_data;
@@ -74,14 +72,11 @@ fetch_data (info, addr)
 static char *crname[] = { "sr", "ccr", "*", "br", "ep", "dp", "*", "tp" };
 
 int
-print_insn_h8500 (addr, info)
-     bfd_vma addr;
-     disassemble_info *info;
+print_insn_h8500 (bfd_vma addr, disassemble_info *info)
 {
   const h8500_opcode_info *opcode;
   void *stream = info->stream;
   fprintf_ftype func = info->fprintf_func;
-
   struct private priv;
   bfd_byte *buffer = priv.the_buffer;
 
@@ -92,21 +87,6 @@ print_insn_h8500 (addr, info)
     /* Error return.  */
     return -1;
 
-  if (0)
-    {
-      static int one;
-
-      if (!one)
-	{
-	  one = 1;
-	  for (opcode = h8500_table; opcode->name; opcode++)
-	    {
-	      if ((opcode->bytes[0].contents & 0x8) == 0)
-		printf ("%s\n", opcode->name);
-	    }
-	}
-    }
-
   /* Run down the table to find the one which matches.  */
   for (opcode = h8500_table; opcode->name; opcode++)
     {
@@ -127,9 +107,8 @@ print_insn_h8500 (addr, info)
 	  FETCH_DATA (info, buffer + byte + 1);
 	  if ((buffer[byte] & opcode->bytes[byte].mask)
 	      != (opcode->bytes[byte].contents))
-	    {
-	      goto next;
-	    }
+	    goto next;
+
 	  else
 	    {
 	      /* Extract any info parts.  */
@@ -299,6 +278,7 @@ print_insn_h8500 (addr, info)
 	      {
 		int i;
 		int nc = 0;
+
 		func (stream, "(");
 		for (i = 0; i < 8; i++)
 		  {
diff --git a/opcodes/hppa-dis.c b/opcodes/hppa-dis.c
index 5dfe973..56f355e 100644
--- a/opcodes/hppa-dis.c
+++ b/opcodes/hppa-dis.c
@@ -1,23 +1,24 @@
 /* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c.
-   Copyright 1989, 1990, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2003
-   Free Software Foundation, Inc.
+   Copyright 1989, 1990, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2003,
+   2005 Free Software Foundation, Inc.
 
    Contributed by the Center for Software Science at the
    University of Utah (pa-gdb-bugs@cs.utah.edu).
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include "sysdep.h"
 #include "dis-asm.h"
@@ -27,32 +28,36 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 /* Integer register names, indexed by the numbers which appear in the
    opcodes.  */
 static const char *const reg_names[] =
- {"flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
+{
+  "flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
   "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
   "r20", "r21", "r22", "r23", "r24", "r25", "r26", "dp", "ret0", "ret1",
-  "sp", "r31"};
+  "sp", "r31"
+};
 
 /* Floating point register names, indexed by the numbers which appear in the
    opcodes.  */
 static const char *const fp_reg_names[] =
- {"fpsr", "fpe2", "fpe4", "fpe6",
+{
+  "fpsr", "fpe2", "fpe4", "fpe6",
   "fr4", "fr5", "fr6", "fr7", "fr8",
   "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
   "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
-  "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31"};
+  "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31"
+};
 
 typedef unsigned int CORE_ADDR;
 
 /* Get at various relevent fields of an instruction word.  */
 
-#define MASK_5 0x1f
+#define MASK_5  0x1f
 #define MASK_10 0x3ff
 #define MASK_11 0x7ff
 #define MASK_14 0x3fff
 #define MASK_16 0xffff
 #define MASK_21 0x1fffff
 
-/* These macros get bit fields using HP's numbering (MSB = 0) */
+/* These macros get bit fields using HP's numbering (MSB = 0).  */
 
 #define GET_FIELD(X, FROM, TO) \
   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
@@ -63,7 +68,8 @@ typedef unsigned int CORE_ADDR;
 /* Some of these have been converted to 2-d arrays because they
    consume less storage this way.  If the maintenance becomes a
    problem, convert them back to const 1-d pointer arrays.  */
-static const char *const control_reg[] = {
+static const char *const control_reg[] =
+{
   "rctr", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
   "pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4",
   "iva", "eiem", "itmr", "pcsq", "pcoq", "iir", "isr",
@@ -71,55 +77,69 @@ static const char *const control_reg[] = {
   "tr4", "tr5", "tr6", "tr7"
 };
 
-static const char *const compare_cond_names[] = {
+static const char *const compare_cond_names[] =
+{
   "", ",=", ",<", ",<=", ",<<", ",<<=", ",sv", ",od",
   ",tr", ",<>", ",>=", ",>", ",>>=", ",>>", ",nsv", ",ev"
 };
-static const char *const compare_cond_64_names[] = {
+static const char *const compare_cond_64_names[] =
+{
   "", ",*=", ",*<", ",*<=", ",*<<", ",*<<=", ",*sv", ",*od",
   ",*tr", ",*<>", ",*>=", ",*>", ",*>>=", ",*>>", ",*nsv", ",*ev"
 };
-static const char *const cmpib_cond_64_names[] = {
+static const char *const cmpib_cond_64_names[] =
+{
   ",*<<", ",*=", ",*<", ",*<=", ",*>>=", ",*<>", ",*>=", ",*>"
 };
-static const char *const add_cond_names[] = {
+static const char *const add_cond_names[] =
+{
   "", ",=", ",<", ",<=", ",nuv", ",znv", ",sv", ",od",
   ",tr", ",<>", ",>=", ",>", ",uv", ",vnz", ",nsv", ",ev"
 };
-static const char *const add_cond_64_names[] = {
+static const char *const add_cond_64_names[] =
+{
   "", ",*=", ",*<", ",*<=", ",*nuv", ",*znv", ",*sv", ",*od",
   ",*tr", ",*<>", ",*>=", ",*>", ",*uv", ",*vnz", ",*nsv", ",*ev"
 };
-static const char *const wide_add_cond_names[] = {
+static const char *const wide_add_cond_names[] =
+{
   "", ",=", ",<", ",<=", ",nuv", ",*=", ",*<", ",*<=",
   ",tr", ",<>", ",>=", ",>", ",uv", ",*<>", ",*>=", ",*>"
 };
-static const char *const logical_cond_names[] = {
+static const char *const logical_cond_names[] =
+{
   "", ",=", ",<", ",<=", 0, 0, 0, ",od",
   ",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev"};
-static const char *const logical_cond_64_names[] = {
+static const char *const logical_cond_64_names[] =
+{
   "", ",*=", ",*<", ",*<=", 0, 0, 0, ",*od",
   ",*tr", ",*<>", ",*>=", ",*>", 0, 0, 0, ",*ev"};
-static const char *const unit_cond_names[] = {
+static const char *const unit_cond_names[] =
+{
   "", ",swz", ",sbz", ",shz", ",sdc", ",swc", ",sbc", ",shc",
   ",tr", ",nwz", ",nbz", ",nhz", ",ndc", ",nwc", ",nbc", ",nhc"
 };
-static const char *const unit_cond_64_names[] = {
+static const char *const unit_cond_64_names[] =
+{
   "", ",*swz", ",*sbz", ",*shz", ",*sdc", ",*swc", ",*sbc", ",*shc",
   ",*tr", ",*nwz", ",*nbz", ",*nhz", ",*ndc", ",*nwc", ",*nbc", ",*nhc"
 };
-static const char *const shift_cond_names[] = {
+static const char *const shift_cond_names[] =
+{
   "", ",=", ",<", ",od", ",tr", ",<>", ",>=", ",ev"
 };
-static const char *const shift_cond_64_names[] = {
+static const char *const shift_cond_64_names[] =
+{
   "", ",*=", ",*<", ",*od", ",*tr", ",*<>", ",*>=", ",*ev"
 };
-static const char *const bb_cond_64_names[] = {
+static const char *const bb_cond_64_names[] =
+{
   ",*<", ",*>="
 };
 static const char *const index_compl_names[] = {"", ",m", ",s", ",sm"};
 static const char *const short_ldst_compl_names[] = {"", ",ma", "", ",mb"};
-static const char *const short_bytes_compl_names[] = {
+static const char *const short_bytes_compl_names[] =
+{
   "", ",b,m", ",e", ",e,m"
 };
 static const char *const float_format_names[] = {",sgl", ",dbl", "", ",quad"};
@@ -146,51 +166,25 @@ static const char *const add_compl_names[] = { 0, "", ",l", ",tsv" };
 #define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \
 			(GET_FIELD ((insn), 19, 19) ? 8 : 0))
 
-static void fput_reg PARAMS ((unsigned int, disassemble_info *));
-static void fput_fp_reg PARAMS ((unsigned int, disassemble_info *));
-static void fput_fp_reg_r PARAMS ((unsigned int, disassemble_info *));
-static void fput_creg PARAMS ((unsigned int, disassemble_info *));
-static void fput_const PARAMS ((unsigned int, disassemble_info *));
-static int extract_3 PARAMS ((unsigned int));
-static int extract_5_load PARAMS ((unsigned int));
-static int extract_5_store PARAMS ((unsigned int));
-static unsigned extract_5r_store PARAMS ((unsigned int));
-static unsigned extract_5R_store PARAMS ((unsigned int));
-static unsigned extract_10U_store PARAMS ((unsigned int));
-static unsigned extract_5Q_store PARAMS ((unsigned int));
-static int extract_11 PARAMS ((unsigned int));
-static int extract_14 PARAMS ((unsigned int));
-static int extract_16 PARAMS ((unsigned int));
-static int extract_21 PARAMS ((unsigned int));
-static int extract_12 PARAMS ((unsigned int));
-static int extract_17 PARAMS ((unsigned int));
-static int extract_22 PARAMS ((unsigned int));
-
 /* Utility function to print registers.  Put these first, so gcc's function
    inlining can do its stuff.  */
 
 #define fputs_filtered(STR,F)	(*info->fprintf_func) (info->stream, "%s", STR)
 
 static void
-fput_reg (reg, info)
-     unsigned reg;
-     disassemble_info *info;
+fput_reg (unsigned reg, disassemble_info *info)
 {
   (*info->fprintf_func) (info->stream, reg ? reg_names[reg] : "r0");
 }
 
 static void
-fput_fp_reg (reg, info)
-     unsigned reg;
-     disassemble_info *info;
+fput_fp_reg (unsigned reg, disassemble_info *info)
 {
   (*info->fprintf_func) (info->stream, reg ? fp_reg_names[reg] : "fr0");
 }
 
 static void
-fput_fp_reg_r (reg, info)
-     unsigned reg;
-     disassemble_info *info;
+fput_fp_reg_r (unsigned reg, disassemble_info *info)
 {
   /* Special case floating point exception registers.  */
   if (reg < 4)
@@ -201,9 +195,7 @@ fput_fp_reg_r (reg, info)
 }
 
 static void
-fput_creg (reg, info)
-     unsigned reg;
-     disassemble_info *info;
+fput_creg (unsigned reg, disassemble_info *info)
 {
   (*info->fprintf_func) (info->stream, control_reg[reg]);
 }
@@ -211,12 +203,10 @@ fput_creg (reg, info)
 /* Print constants with sign.  */
 
 static void
-fput_const (num, info)
-     unsigned num;
-     disassemble_info *info;
+fput_const (unsigned num, disassemble_info *info)
 {
-  if ((int)num < 0)
-    (*info->fprintf_func) (info->stream, "-%x", -(int)num);
+  if ((int) num < 0)
+    (*info->fprintf_func) (info->stream, "-%x", - (int) num);
   else
     (*info->fprintf_func) (info->stream, "%x", num);
 }
@@ -226,81 +216,80 @@ fput_const (num, info)
 
 /* Extract a 3-bit space register number from a be, ble, mtsp or mfsp.  */
 static int
-extract_3 (word)
-     unsigned word;
+extract_3 (unsigned word)
 {
   return GET_FIELD (word, 18, 18) << 2 | GET_FIELD (word, 16, 17);
 }
 
 static int
-extract_5_load (word)
-     unsigned word;
+extract_5_load (unsigned word)
 {
   return low_sign_extend (word >> 16 & MASK_5, 5);
 }
 
 /* Extract the immediate field from a st{bhw}s instruction.  */
+
 static int
-extract_5_store (word)
-     unsigned word;
+extract_5_store (unsigned word)
 {
   return low_sign_extend (word & MASK_5, 5);
 }
 
 /* Extract the immediate field from a break instruction.  */
+
 static unsigned
-extract_5r_store (word)
-     unsigned word;
+extract_5r_store (unsigned word)
 {
   return (word & MASK_5);
 }
 
 /* Extract the immediate field from a {sr}sm instruction.  */
+
 static unsigned
-extract_5R_store (word)
-     unsigned word;
+extract_5R_store (unsigned word)
 {
   return (word >> 16 & MASK_5);
 }
 
 /* Extract the 10 bit immediate field from a {sr}sm instruction.  */
+
 static unsigned
-extract_10U_store (word)
-     unsigned word;
+extract_10U_store (unsigned word)
 {
   return (word >> 16 & MASK_10);
 }
 
 /* Extract the immediate field from a bb instruction.  */
+
 static unsigned
-extract_5Q_store (word)
-     unsigned word;
+extract_5Q_store (unsigned word)
 {
   return (word >> 21 & MASK_5);
 }
 
 /* Extract an 11 bit immediate field.  */
+
 static int
-extract_11 (word)
-     unsigned word;
+extract_11 (unsigned word)
 {
   return low_sign_extend (word & MASK_11, 11);
 }
 
 /* Extract a 14 bit immediate field.  */
+
 static int
-extract_14 (word)
-     unsigned word;
+extract_14 (unsigned word)
 {
   return low_sign_extend (word & MASK_14, 14);
 }
 
 /* Extract a 16 bit immediate field (PA2.0 wide only).  */
+
 static int
-extract_16 (word)
-     unsigned word;
+extract_16 (unsigned word)
 {
   int m15, m0, m1;
+
   m0 = GET_BIT (word, 16);
   m1 = GET_BIT (word, 17);
   m15 = GET_BIT (word, 31);
@@ -312,8 +301,7 @@ extract_16 (word)
 /* Extract a 21 bit constant.  */
 
 static int
-extract_21 (word)
-     unsigned word;
+extract_21 (unsigned word)
 {
   int val;
 
@@ -334,43 +322,39 @@ extract_21 (word)
 /* Extract a 12 bit constant from branch instructions.  */
 
 static int
-extract_12 (word)
-     unsigned word;
+extract_12 (unsigned word)
 {
-  return sign_extend (GET_FIELD (word, 19, 28) |
-		      GET_FIELD (word, 29, 29) << 10 |
-		      (word & 0x1) << 11, 12) << 2;
+  return sign_extend (GET_FIELD (word, 19, 28)
+		      | GET_FIELD (word, 29, 29) << 10
+		      | (word & 0x1) << 11, 12) << 2;
 }
 
 /* Extract a 17 bit constant from branch instructions, returning the
    19 bit signed value.  */
 
 static int
-extract_17 (word)
-     unsigned word;
+extract_17 (unsigned word)
 {
-  return sign_extend (GET_FIELD (word, 19, 28) |
-		      GET_FIELD (word, 29, 29) << 10 |
-		      GET_FIELD (word, 11, 15) << 11 |
-		      (word & 0x1) << 16, 17) << 2;
+  return sign_extend (GET_FIELD (word, 19, 28)
+		      | GET_FIELD (word, 29, 29) << 10
+		      | GET_FIELD (word, 11, 15) << 11
+		      | (word & 0x1) << 16, 17) << 2;
 }
 
 static int
-extract_22 (word)
-     unsigned word;
+extract_22 (unsigned word)
 {
-  return sign_extend (GET_FIELD (word, 19, 28) |
-		      GET_FIELD (word, 29, 29) << 10 |
-		      GET_FIELD (word, 11, 15) << 11 |
-		      GET_FIELD (word, 6, 10) << 16 |
-		      (word & 0x1) << 21, 22) << 2;
+  return sign_extend (GET_FIELD (word, 19, 28)
+		      | GET_FIELD (word, 29, 29) << 10
+		      | GET_FIELD (word, 11, 15) << 11
+		      | GET_FIELD (word, 6, 10) << 16
+		      | (word & 0x1) << 21, 22) << 2;
 }
 
 /* Print one instruction.  */
+
 int
-print_insn_hppa (memaddr, info)
-     bfd_vma memaddr;
-     disassemble_info *info;
+print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
 {
   bfd_byte buffer[4];
   unsigned int insn, i;
@@ -390,9 +374,10 @@ print_insn_hppa (memaddr, info)
   for (i = 0; i < NUMOPCODES; ++i)
     {
       const struct pa_opcode *opcode = &pa_opcodes[i];
+
       if ((insn & opcode->mask) == opcode->match)
 	{
-	  register const char *s;
+	  const char *s;
 #ifndef BFD64
 	  if (opcode->arch == pa20w)
 	    continue;
@@ -789,10 +774,10 @@ print_insn_hppa (memaddr, info)
 			   float_comp_names[GET_FIELD (insn, 27, 31)]);
 			break;
 
-			/* these four conditions are for the set of instructions
+			/* These four conditions are for the set of instructions
 			   which distinguish true/false conditions by opcode
 			   rather than by the 'f' bit (sigh): comb, comib,
-			   addb, addib */
+			   addb, addib.  */
 		      case 't':
 			fputs_filtered
 			  (compare_cond_names[GET_FIELD (insn, 16, 18)], info);
@@ -1070,8 +1055,8 @@ print_insn_hppa (memaddr, info)
 					 GET_FIELD (insn, 23, 25));
 		  break;
 		case 'F':
-		  /* if no destination completer and not before a completer
-		     for fcmp, need a space here */
+		  /* If no destination completer and not before a completer
+		     for fcmp, need a space here.  */
 		  if (s[1] == 'G' || s[1] == '?')
 		    fputs_filtered
 		      (float_format_names[GET_FIELD (insn, 19, 20)], info);
@@ -1094,8 +1079,8 @@ print_insn_hppa (memaddr, info)
 					   float_format_names[1]);
 		  break;
 		case 'I':
-		  /* if no destination completer and not before a completer
-		     for fcmp, need a space here */
+		  /* If no destination completer and not before a completer
+		     for fcmp, need a space here.  */
 		  if (s[1] == '?')
 		    fputs_filtered
 		      (float_format_names[GET_FIELD (insn, 20, 20)], info);
@@ -1171,6 +1156,7 @@ print_insn_hppa (memaddr, info)
 		    const char * const * source = float_format_names;
 		    const char * const * dest = float_format_names;
 		    char *t = "";
+
 		    if (sub == 4)
 		      {
 			fputs_filtered (",UND ", info);
@@ -1212,22 +1198,18 @@ print_insn_hppa (memaddr, info)
 		  {
 		    int cond = GET_FIELD (insn, 27, 31);
 
-		    if (cond == 0)
-		      fputs_filtered (" ", info);
-		    else if (cond == 1)
-		      fputs_filtered ("acc ", info);
-		    else if (cond == 2)
-		      fputs_filtered ("rej ", info);
-		    else if (cond == 5)
-		      fputs_filtered ("acc8 ", info);
-		    else if (cond == 6)
-		      fputs_filtered ("rej8 ", info);
-		    else if (cond == 9)
-		      fputs_filtered ("acc6 ", info);
-		    else if (cond == 13)
-		      fputs_filtered ("acc4 ", info);
-		    else if (cond == 17)
-		      fputs_filtered ("acc2 ", info);
+		    switch (cond)
+		      {
+		      case  0: fputs_filtered (" ", info); break;
+		      case  1: fputs_filtered ("acc ", info); break;
+		      case  2: fputs_filtered ("rej ", info); break;
+		      case  5: fputs_filtered ("acc8 ", info); break;
+		      case  6: fputs_filtered ("rej8 ", info); break;
+		      case  9: fputs_filtered ("acc6 ", info); break;
+		      case 13: fputs_filtered ("acc4 ", info); break;
+		      case 17: fputs_filtered ("acc2 ", info); break;
+		      default: break;
+		      }
 		    break;
 		  }
 
@@ -1243,9 +1225,9 @@ print_insn_hppa (memaddr, info)
 		  break;
 		}
 	    }
-	  return sizeof(insn);
+	  return sizeof (insn);
 	}
     }
   (*info->fprintf_func) (info->stream, "#%8x", insn);
-  return sizeof(insn);
+  return sizeof (insn);
 }
diff --git a/opcodes/i370-dis.c b/opcodes/i370-dis.c
index 3a2351f..97ed5a2 100644
--- a/opcodes/i370-dis.c
+++ b/opcodes/i370-dis.c
@@ -1,23 +1,24 @@
 /* i370-dis.c -- Disassemble Instruction 370 (ESA/390) instructions
-   Copyright 1994, 2000, 2003 Free Software Foundation, Inc.
+   Copyright 1994, 2000, 2003, 2005 Free Software Foundation, Inc.
    PowerPC version written by Ian Lance Taylor, Cygnus Support
    Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org>
 
-This file is part of GDB, GAS, and the GNU binutils.
+   This file is part of GDB, GAS, and the GNU binutils.
 
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-2, or (at your option) any later version.
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
 
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
-the GNU General Public License for more details.
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING.  If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "sysdep.h"
@@ -25,8 +26,7 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
 #include "opcode/i370.h"
 
 /* This file provides several disassembler functions, all of which use
-   the disassembler interface defined in dis-asm.h.
-*/
+   the disassembler interface defined in dis-asm.h.  */
 
 int
 print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info)
@@ -44,7 +44,7 @@ print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info)
       return -1;
     }
 
-  /* Cast the bytes into the insn (in a host-endian indep way) */
+  /* Cast the bytes into the insn (in a host-endian indep way).  */
   insn.i[0] = (buffer[0] << 24) & 0xff000000;
   insn.i[0] |= (buffer[1] << 16) & 0xff0000;
   insn.i[0] |= (buffer[2] << 8) & 0xff00;
@@ -70,15 +70,17 @@ print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info)
           masked.i[0] &= 0xffff;
         }
       masked.i[0] &= opcode->mask.i[0];
-      if (masked.i[0] != opcode->opcode.i[0]) continue;
+      if (masked.i[0] != opcode->opcode.i[0])
+	continue;
 
       if (6 == opcode->len)
         {
           masked.i[1] &= opcode->mask.i[1];
-          if (masked.i[1] != opcode->opcode.i[1]) continue;
+          if (masked.i[1] != opcode->opcode.i[1])
+	    continue;
         }
 
-      /* Found a match.  adjust a tad */
+      /* Found a match.  adjust a tad.  */
       if (2 == opcode->len)
         {
           insn.i[0] >>= 16;
@@ -95,7 +97,8 @@ print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info)
           if (operand->extract)
             (*operand->extract) (insn, &invalid);
         }
-      if (invalid) continue;
+      if (invalid)
+	continue;
 
       /* The instruction is valid.  */
       (*info->fprintf_func) (info->stream, "%s", opcode->name);
@@ -113,9 +116,7 @@ print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info)
           if (operand->extract)
             value = (*operand->extract) (insn, (int *) NULL);
           else
-            {
-              value = (insn.i[0] >> operand->shift) & ((1 << operand->bits) - 1);
-            }
+	    value = (insn.i[0] >> operand->shift) & ((1 << operand->bits) - 1);
 
           /* Print the operand as directed by the flags.  */
           if ((operand->flags & I370_OPERAND_OPTIONAL) != 0)
@@ -148,14 +149,11 @@ print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info)
             (*info->fprintf_func) (info->stream, "%ld", value);
           else
             (*info->fprintf_func) (info->stream, " %ld, ", value);
-
         }
 
       return opcode->len;
-
     }
 
-
   /* We could not find a match.  */
   (*info->fprintf_func) (info->stream, ".short 0x%02x%02x", buffer[0], buffer[1]);
 
diff --git a/opcodes/i370-opc.c b/opcodes/i370-opc.c
index b91b22b..482e0c3 100644
--- a/opcodes/i370-opc.c
+++ b/opcodes/i370-opc.c
@@ -1,24 +1,24 @@
 /* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list
-   Copyright 1994, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
+   Copyright 1994, 1999, 2000, 2001, 2003, 2005 Free Software Foundation, Inc.
    PowerPC version written by Ian Lance Taylor, Cygnus Support
    Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> 1998, 1999
 
-This file is part of GDB, GAS, and the GNU binutils.
+   This file is part of GDB, GAS, and the GNU binutils.
 
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-2, or (at your option) any later version.
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
 
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
-the GNU General Public License for more details.
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING.  If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include <stdio.h>
 #include "sysdep.h"
@@ -35,14 +35,49 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    inserting operands into instructions and vice-versa is kept in this
    file.  */
 
-/* Local insertion and extraction functions.  */
-static i370_insn_t insert_ss_b2 (i370_insn_t, long, const char **);
-static i370_insn_t insert_ss_d2 (i370_insn_t, long, const char **);
-static i370_insn_t insert_rxf_r3 (i370_insn_t, long, const char **);
-static long extract_ss_b2 (i370_insn_t, int *);
-static long extract_ss_d2 (i370_insn_t, int *);
-static long extract_rxf_r3 (i370_insn_t, int *);
+/* The functions used to insert and extract complicated operands.  */
+
+static i370_insn_t
+insert_ss_b2 (i370_insn_t insn, long value,
+	      const char **errmsg ATTRIBUTE_UNUSED)
+{
+  insn.i[1] |= (value & 0xf) << 28;
+  return insn;
+}
+
+static i370_insn_t
+insert_ss_d2 (i370_insn_t insn, long value,
+	      const char **errmsg ATTRIBUTE_UNUSED)
+{
+  insn.i[1] |= (value & 0xfff) << 16;
+  return insn;
+}
+
+static i370_insn_t
+insert_rxf_r3 (i370_insn_t insn, long value,
+	       const char **errmsg ATTRIBUTE_UNUSED)
+{
+  insn.i[1] |= (value & 0xf) << 28;
+  return insn;
+}
+
+static long
+extract_ss_b2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
+{
+  return (insn.i[1] >>28) & 0xf;
+}
+
+static long
+extract_ss_d2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
+{
+  return (insn.i[1] >>16) & 0xfff;
+}
 
+static long
+extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
+{
+  return (insn.i[1] >>28) & 0xf;
+}
 
 /* The operands table.
    The fields are bits, shift, insert, extract, flags, name.
@@ -53,8 +88,7 @@ static long extract_rxf_r3 (i370_insn_t, int *);
                       if absent, should take value of zero
    I370_OPERAND_INDEX index register; if present, must name a register
                       if absent, should take value of zero
-   I370_OPERAND_OPTIONAL other optional operand (usuall reg?)
-*/
+   I370_OPERAND_OPTIONAL other optional operand (usuall reg?).  */
 
 const struct i370_operand i370_operands[] =
 {
@@ -223,180 +257,135 @@ const struct i370_operand i370_operands[] =
 #define SS_D2 (SS_B2 + 1)
 #define SS_D2_MASK (0xfff)
   { 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" },
-
-
+  
 };
 
-/* The functions used to insert and extract complicated operands.  */
-
-static i370_insn_t
-insert_ss_b2 (i370_insn_t insn, long value,
-	      const char **errmsg ATTRIBUTE_UNUSED)
-{
-  insn.i[1] |= (value & 0xf) << 28;
-  return insn;
-}
-
-static i370_insn_t
-insert_ss_d2 (i370_insn_t insn, long value,
-	      const char **errmsg ATTRIBUTE_UNUSED)
-{
-  insn.i[1] |= (value & 0xfff) << 16;
-  return insn;
-}
-
-static i370_insn_t
-insert_rxf_r3 (i370_insn_t insn, long value,
-	       const char **errmsg ATTRIBUTE_UNUSED)
-{
-  insn.i[1] |= (value & 0xf) << 28;
-  return insn;
-}
-
-static long
-extract_ss_b2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
-{
-  return (insn.i[1] >>28) & 0xf;
-}
-
-static long
-extract_ss_d2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
-{
-  return (insn.i[1] >>16) & 0xfff;
-}
-
-static long
-extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
-{
-  return (insn.i[1] >>28) & 0xf;
-}
-
 
 /* Macros used to form opcodes.  */
 
 /* The short-instruction opcode.  */
-#define OPS(x) ((((unsigned short)(x)) & 0xff) << 8)
+#define OPS(x) ((((unsigned short) (x)) & 0xff) << 8)
 #define OPS_MASK OPS (0xff)
 
 /* the extended instruction opcode */
-#define XOPS(x) ((((unsigned short)(x)) & 0xff) << 24)
+#define XOPS(x) ((((unsigned short) (x)) & 0xff) << 24)
 #define XOPS_MASK XOPS (0xff)
 
 /* the S instruction opcode */
-#define SOPS(x) ((((unsigned short)(x)) & 0xffff) << 16)
+#define SOPS(x) ((((unsigned short) (x)) & 0xffff) << 16)
 #define SOPS_MASK SOPS (0xffff)
 
 /* the E instruction opcode */
-#define EOPS(x) (((unsigned short)(x)) & 0xffff)
+#define EOPS(x) (((unsigned short) (x)) & 0xffff)
 #define EOPS_MASK EOPS (0xffff)
 
 /* the RI instruction opcode */
-#define ROPS(x) (((((unsigned short)(x)) & 0xff0) << 20) | \
-                 ((((unsigned short)(x)) & 0x00f) << 16))
+#define ROPS(x) (((((unsigned short) (x)) & 0xff0) << 20) | \
+                 ((((unsigned short) (x)) & 0x00f) << 16))
 #define ROPS_MASK ROPS (0xfff)
 
-/* --------------------------------------------------------- */
+
 /* An E form instruction.  */
 #define E(op)  (EOPS (op))
 #define E_MASK E (0xffff)
 
 /* An RR form instruction.  */
 #define RR(op, r1, r2) \
-  (OPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) |   \
-              ((((unsigned short)(r2)) & 0xf) ))
+  (OPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) |   \
+              ((((unsigned short) (r2)) & 0xf) ))
 
 #define RR_MASK RR (0xff, 0x0, 0x0)
 
 /* An SVC-style instruction.  */
 #define SVC(op, i) \
-  (OPS (op) | (((unsigned short)(i)) & 0xff))
+  (OPS (op) | (((unsigned short) (i)) & 0xff))
 
 #define SVC_MASK SVC (0xff, 0x0)
 
 /* An RRE form instruction.  */
 #define RRE(op, r1, r2) \
-  (SOPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) |   \
-               ((((unsigned short)(r2)) & 0xf) ))
+  (SOPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) |   \
+               ((((unsigned short) (r2)) & 0xf) ))
 
 #define RRE_MASK RRE (0xffff, 0x0, 0x0)
 
 /* An RRF form instruction.  */
 #define RRF(op, r3, r1, r2) \
-  (SOPS (op) | ((((unsigned short)(r3)) & 0xf) << 12) |   \
-               ((((unsigned short)(r1)) & 0xf) << 4)  |   \
-               ((((unsigned short)(r2)) & 0xf) ))
+  (SOPS (op) | ((((unsigned short) (r3)) & 0xf) << 12) |   \
+               ((((unsigned short) (r1)) & 0xf) << 4)  |   \
+               ((((unsigned short) (r2)) & 0xf) ))
 
 #define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0)
 
 /* An RX form instruction.  */
 #define RX(op, r1, x2, b2, d2) \
-  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
-              ((((unsigned short)(x2)) & 0xf) << 16) |  \
-              ((((unsigned short)(b2)) & 0xf) << 12) |  \
-              ((((unsigned short)(d2)) & 0xfff)))
+  (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \
+              ((((unsigned short) (x2)) & 0xf) << 16) |  \
+              ((((unsigned short) (b2)) & 0xf) << 12) |  \
+              ((((unsigned short) (d2)) & 0xfff)))
 
 #define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0)
 
 /* An RXE form instruction high word.  */
 #define RXEH(op, r1, x2, b2, d2) \
-  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
-              ((((unsigned short)(x2)) & 0xf) << 16) |  \
-              ((((unsigned short)(b2)) & 0xf) << 12) |  \
-              ((((unsigned short)(d2)) & 0xfff)))
+  (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \
+              ((((unsigned short) (x2)) & 0xf) << 16) |  \
+              ((((unsigned short) (b2)) & 0xf) << 12) |  \
+              ((((unsigned short) (d2)) & 0xfff)))
 
 #define RXEH_MASK RXEH (0xff, 0, 0, 0, 0)
 
 /* An RXE form instruction low word.  */
 #define RXEL(op) \
-              ((((unsigned short)(op)) & 0xff) << 16 )
+              ((((unsigned short) (op)) & 0xff) << 16 )
 
 #define RXEL_MASK RXEL (0xff)
 
 /* An RXF form instruction high word.  */
 #define RXFH(op, r1, x2, b2, d2) \
-  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
-              ((((unsigned short)(x2)) & 0xf) << 16) |  \
-              ((((unsigned short)(b2)) & 0xf) << 12) |  \
-              ((((unsigned short)(d2)) & 0xfff)))
+  (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \
+              ((((unsigned short) (x2)) & 0xf) << 16) |  \
+              ((((unsigned short) (b2)) & 0xf) << 12) |  \
+              ((((unsigned short) (d2)) & 0xfff)))
 
 #define RXFH_MASK RXFH (0xff, 0, 0, 0, 0)
 
 /* An RXF form instruction low word.  */
 #define RXFL(op, r3) \
-              (((((unsigned short)(r3)) & 0xf)  << 28 ) | \
-               ((((unsigned short)(op)) & 0xff) << 16 ))
+              (((((unsigned short) (r3)) & 0xf)  << 28 ) | \
+               ((((unsigned short) (op)) & 0xff) << 16 ))
 
 #define RXFL_MASK RXFL (0xff, 0)
 
 /* An RS form instruction.  */
 #define RS(op, r1, b3, b2, d2) \
-  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
-              ((((unsigned short)(b3)) & 0xf) << 16) |  \
-              ((((unsigned short)(b2)) & 0xf) << 12) |  \
-              ((((unsigned short)(d2)) & 0xfff)))
+  (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \
+              ((((unsigned short) (b3)) & 0xf) << 16) |  \
+              ((((unsigned short) (b2)) & 0xf) << 12) |  \
+              ((((unsigned short) (d2)) & 0xfff)))
 
 #define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0)
 
 /* An RSI form instruction.  */
 #define RSI(op, r1, r3, i2) \
-  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
-              ((((unsigned short)(r3)) & 0xf) << 16) |  \
-              ((((unsigned short)(i2)) & 0xffff)))
+  (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \
+              ((((unsigned short) (r3)) & 0xf) << 16) |  \
+              ((((unsigned short) (i2)) & 0xffff)))
 
 #define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0)
 
 /* An RI form instruction.  */
 #define RI(op, r1, i2) \
-  (ROPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
-              ((((unsigned short)(i2)) & 0xffff)))
+  (ROPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \
+              ((((unsigned short) (i2)) & 0xffff)))
 
 #define RI_MASK RI (0xfff, 0x0, 0x0)
 
 /* An SI form instruction.  */
 #define SI(op, i2, b1, d1) \
-  (XOPS(op) | ((((unsigned short)(i2)) & 0xff) << 16) |  \
-              ((((unsigned short)(b1)) & 0xf)  << 12) |  \
-              ((((unsigned short)(d1)) & 0xfff)))
+  (XOPS(op) | ((((unsigned short) (i2)) & 0xff) << 16) |  \
+              ((((unsigned short) (b1)) & 0xf)  << 12) |  \
+              ((((unsigned short) (d1)) & 0xfff)))
 
 #define SI_MASK SI (0xff, 0x0, 0x0, 0x0)
 
@@ -409,26 +398,26 @@ extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
 
 /* An SS form instruction high word.  */
 #define SSH(op, l, b1, d1) \
-  (XOPS(op) | ((((unsigned short)(l)) & 0xff) << 16) |  \
-              ((((unsigned short)(b1)) & 0xf)  << 12) |  \
-              ((((unsigned short)(d1)) & 0xfff)))
+  (XOPS(op) | ((((unsigned short) (l)) & 0xff) << 16) |  \
+              ((((unsigned short) (b1)) & 0xf)  << 12) |  \
+              ((((unsigned short) (d1)) & 0xfff)))
 
 /* An SS form instruction low word.  */
 #define SSL(b2, d2) \
-            ( ((((unsigned short)(b1)) & 0xf)   << 28) |  \
-              ((((unsigned short)(d1)) & 0xfff) << 16 ))
+            ( ((((unsigned short) (b1)) & 0xf)   << 28) |  \
+              ((((unsigned short) (d1)) & 0xfff) << 16 ))
 
 #define SS_MASK SSH (0xff, 0x0, 0x0, 0x0)
 
 /* An SSE form instruction high word.  */
 #define SSEH(op, b1, d1) \
-  (SOPS(op) | ((((unsigned short)(b1)) & 0xf)  << 12) |  \
-              ((((unsigned short)(d1)) & 0xfff)))
+  (SOPS(op) | ((((unsigned short) (b1)) & 0xf)  << 12) |  \
+              ((((unsigned short) (d1)) & 0xfff)))
 
 /* An SSE form instruction low word.  */
 #define SSEL(b2, d2) \
-            ( ((((unsigned short)(b1)) & 0xf)   << 28) |  \
-              ((((unsigned short)(d1)) & 0xfff) << 16 ))
+            ( ((((unsigned short) (b1)) & 0xf)   << 28) |  \
+              ((((unsigned short) (d1)) & 0xfff) << 16 ))
 
 #define SSE_MASK SSEH (0xffff, 0x0, 0x0)
 
@@ -436,8 +425,7 @@ extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
 /* Smaller names for the flags so each entry in the opcodes table will
    fit on a single line.  These flags are set up so that e.g. IXA means
    the insn is supported on the 370/XA or newer architecture.
-   Note that 370 or older obsolete insn's are not supported ...
- */
+   Note that 370 or older obsolete insn's are not supported ...  */
 #define	IBF	I370_OPCODE_ESA390_BF
 #define	IBS	I370_OPCODE_ESA390_BS
 #define	ICK	I370_OPCODE_ESA390_CK
@@ -479,8 +467,8 @@ extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
    specific instructions before more general instructions.  It is also
    sorted by major opcode.  */
 
-const struct i370_opcode i370_opcodes[] = {
-
+const struct i370_opcode i370_opcodes[] =
+{
 /* E form instructions */
 { "pr",     2, {{E(0x0101),    0}}, {{E_MASK,  0}}, IESA,  {0} },
 
@@ -546,10 +534,10 @@ const struct i370_opcode i370_opcodes[] = {
 { "sxr",    2, {{RR(0x37,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
 { "xr",     2, {{RR(0x17,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
 
-/* unusual RR formats */
+/* Unusual RR formats.  */
 { "svc",    2, {{SVC(0x0a,0), 0}},  {{SVC_MASK, 0}}, I370,  {RR_I} },
 
-/* RRE form instructions */
+/* RRE form instructions.  */
 { "adbr",   4, {{RRE(0xb31a,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
 { "aebr",   4, {{RRE(0xb30a,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
 { "axbr",   4, {{RRE(0xb34a,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
@@ -654,7 +642,7 @@ const struct i370_opcode i370_opcodes[] = {
 { "thdr",   4, {{RRE(0xb359,0,0),   0}}, {{RRE_MASK, 0}}, IFX,  {RRE_R1, RRE_R2} },
 { "thder",  4, {{RRE(0xb359,0,0),   0}}, {{RRE_MASK, 0}}, IFX,  {RRE_R1, RRE_R2} },
 
-/* RRF form instructions */
+/* RRF form instructions.  */
 { "cfdbr",  4, {{RRF(0xb399,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
 { "cfdr",   4, {{RRF(0xb3b9,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX,  {RRF_R1, RRF_R3, RRF_R2} },
 { "cfebr",  4, {{RRF(0xb398,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
@@ -673,7 +661,7 @@ const struct i370_opcode i370_opcodes[] = {
 { "tbdr",   4, {{RRF(0xb351,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX,  {RRF_R1, RRF_R3, RRF_R2} },
 { "tbedr",  4, {{RRF(0xb350,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX,  {RRF_R1, RRF_R3, RRF_R2} },
 
-/* RX form instructions */
+/* RX form instructions.  */
 { "a",      4, {{RX(0x5a,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
 { "ad",     4, {{RX(0x6a,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
 { "ae",     4, {{RX(0x7a,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
@@ -726,7 +714,7 @@ const struct i370_opcode i370_opcodes[] = {
 { "sw",     4, {{RX(0x6f,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
 { "x",      4, {{RX(0x57,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
 
-/* RXE form instructions */
+/* RXE form instructions.  */
 { "adb",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x1a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
 { "aeb",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x0a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
 { "cdb",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x19)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
@@ -756,13 +744,13 @@ const struct i370_opcode i370_opcodes[] = {
 { "tceb",   6, {{RXEH(0xed,0,0,0,0), RXEL(0x10)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
 { "tcxb",   6, {{RXEH(0xed,0,0,0,0), RXEL(0x12)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
 
-/* RXF form instructions */
+/* RXF form instructions.  */
 { "madb",   6, {{RXFH(0xed,0,0,0,0), RXFL(0x1e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
 { "maeb",   6, {{RXFH(0xed,0,0,0,0), RXFL(0x0e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
 { "msdb",   6, {{RXFH(0xed,0,0,0,0), RXFL(0x1f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
 { "mseb",   6, {{RXFH(0xed,0,0,0,0), RXFL(0x0f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
 
-/* RS form instructions */
+/* RS form instructions.  */
 { "bxh",    4, {{RS(0x86,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
 { "bxle",   4, {{RS(0x87,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
 { "cds",    4, {{RS(0xbb,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA,  {RX_R1, RS_R3, RS_D2, RS_B2} },
@@ -781,7 +769,7 @@ const struct i370_opcode i370_opcodes[] = {
 { "stm",    4, {{RS(0x90,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
 { "trace",  4, {{RS(0x99,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA,  {RX_R1, RS_R3, RS_D2, RS_B2} },
 
-/* RS form instructions with blank R3 and optional B2 (shift left/right) */
+/* RS form instructions with blank R3 and optional B2 (shift left/right).  */
 { "sla",    4, {{RS(0x8b,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
 { "slda",   4, {{RS(0x8f,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
 { "sldl",   4, {{RS(0x8d,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
@@ -791,11 +779,11 @@ const struct i370_opcode i370_opcodes[] = {
 { "srdl",   4, {{RS(0x8c,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
 { "srl",    4, {{RS(0x88,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
 
-/* RSI form instructions */
+/* RSI form instructions.  */
 { "brxh",   4, {{RSI(0x84,0,0,0),  0}}, {{RSI_MASK, 0}}, IIR,  {RSI_R1, RSI_R3, RSI_I2} },
 { "brxle",  4, {{RSI(0x85,0,0,0),  0}}, {{RSI_MASK, 0}}, IIR,  {RSI_R1, RSI_R3, RSI_I2} },
 
-/* RI form instructions */
+/* RI form instructions.  */
 { "ahi",    4, {{RI(0xa7a,0,0),    0}}, {{RI_MASK,  0}}, IIR,  {RI_R1, RI_I2} },
 { "bras",   4, {{RI(0xa75,0,0),    0}}, {{RI_MASK,  0}}, IIR,  {RI_R1, RI_I2} },
 { "brc",    4, {{RI(0xa74,0,0),    0}}, {{RI_MASK,  0}}, IIR,  {RI_R1, RI_I2} },
@@ -806,7 +794,7 @@ const struct i370_opcode i370_opcodes[] = {
 { "tmh",    4, {{RI(0xa70,0,0),    0}}, {{RI_MASK,  0}}, IIR,  {RI_R1, RI_I2} },
 { "tml",    4, {{RI(0xa71,0,0),    0}}, {{RI_MASK,  0}}, IIR,  {RI_R1, RI_I2} },
 
-/* SI form instructions */
+/* SI form instructions.  */
 { "cli",    4, {{SI(0x95,0,0,0),   0}}, {{SI_MASK,  0}}, I370, {SI_D1, SI_B1, SI_I2} },
 { "mc",     4, {{SI(0xaf,0,0,0),   0}}, {{SI_MASK,  0}}, I370, {SI_D1, SI_B1, SI_I2} },
 { "mvi",    4, {{SI(0x92,0,0,0),   0}}, {{SI_MASK,  0}}, I370, {SI_D1, SI_B1, SI_I2} },
@@ -817,7 +805,7 @@ const struct i370_opcode i370_opcodes[] = {
 { "tm",     4, {{SI(0x91,0,0,0),   0}}, {{SI_MASK,  0}}, I370, {SI_D1, SI_B1, SI_I2} },
 { "xi",     4, {{SI(0x97,0,0,0),   0}}, {{SI_MASK,  0}}, I370, {SI_D1, SI_B1, SI_I2} },
 
-/* S form instructions */
+/* S form instructions.  */
 { "cfc",    4, {{S(0xb21a,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
 { "csch",   4, {{S(0xb230,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {0} },
 { "hsch",   4, {{S(0xb231,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {0} },
@@ -858,7 +846,7 @@ const struct i370_opcode i370_opcodes[] = {
 { "ts",     4, {{S(0x9300,0,0),    0}}, {{S_MASK,	 0}}, I370, {S_D2, S_B2} },
 { "tsch",   4, {{S(0xb235,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
 
-/* SS form instructions */
+/* SS form instructions.  */
 { "ap",     6, {{SSH(0xfa,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
 { "clc",    6, {{SSH(0xd5,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
 { "cp",     6, {{SSH(0xf9,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
@@ -885,7 +873,7 @@ const struct i370_opcode i370_opcodes[] = {
 { "xc",     6, {{SSH(0xd7,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
 { "zap",    6, {{SSH(0xf8,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
 
-/* SSE form instructions */
+/* SSE form instructions.  */
 { "lasp",   6, {{SSEH(0xe500,0,0), 0}}, {{SSE_MASK, 0}}, IXA,  {SS_D1, SS_B1, SS_D2, SS_B2} },
 { "mvcdk",  6, {{SSEH(0xe50f,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
 { "mvcsk",  6, {{SSEH(0xe50e,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
@@ -899,7 +887,8 @@ const int i370_num_opcodes =
 
 /* The macro table.  This is only used by the assembler.  */
 
-const struct i370_macro i370_macros[] = {
+const struct i370_macro i370_macros[] =
+{
 { "b",     1,   I370,	"bc  15,%0" },
 { "br",    1,   I370,	"bcr 15,%0" },
 
diff --git a/opcodes/ip2k-asm.c b/opcodes/ip2k-asm.c
index 247e8c7..4a2408c 100644
--- a/opcodes/ip2k-asm.c
+++ b/opcodes/ip2k-asm.c
@@ -1,26 +1,27 @@
 /* Assembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-asm.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-asm.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -49,24 +50,11 @@ static const char * parse_insn_normal
 
 /* -- asm.c */
 
-#define PARSE_FUNC_DECL(name) \
-  static const char *name (CGEN_CPU_DESC, const char **, int, long *)
-#define PARSE_UFUNC_DECL(name) \
-  static const char *name (CGEN_CPU_DESC, const char **, int, unsigned long *)
-
-PARSE_UFUNC_DECL (parse_fr);
-PARSE_UFUNC_DECL (parse_addr16);
-PARSE_UFUNC_DECL (parse_addr16_cjp);
-PARSE_FUNC_DECL (parse_lit8);
-PARSE_UFUNC_DECL (parse_bit3);
-
-
 static const char *
-parse_fr (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_fr (CGEN_CPU_DESC cd,
+	  const char **strp,
+	  int opindex,
+	  unsigned long *valuep)
 {
   const char *errmsg;
   const char *old_strp;
@@ -77,7 +65,7 @@ parse_fr (cd, strp, opindex, valuep)
   bfd_vma tempvalue;
 
   old_strp = *strp;
-  afteroffset = NULL; 
+  afteroffset = NULL;
 
   /* Check here to see if you're about to try parsing a w as the first arg
      and return an error if you are.  */
@@ -155,7 +143,7 @@ parse_fr (cd, strp, opindex, valuep)
 	    {
 	      /* Value is ok.  Fix up the first 2 bits and return.  */
 	      *valuep = 0x0100 | tempvalue;
-	      *strp += 4; /* skip over the (DP) in *strp.  */
+	      *strp += 4; /* Skip over the (DP) in *strp.  */
 	      return errmsg;
 	    }
 	  else
@@ -196,7 +184,7 @@ parse_fr (cd, strp, opindex, valuep)
 	    {
 	      /* Value is ok.  Fix up the first 2 bits and return.  */
 	      *valuep = 0x0180 | tempvalue;
-	      *strp += 4; /* skip over the (SP) in *strp.  */
+	      *strp += 4; /* Skip over the (SP) in *strp.  */
 	      return errmsg;
 	    }
 	  else
@@ -217,11 +205,11 @@ parse_fr (cd, strp, opindex, valuep)
     {
       *valuep = value;
 
-      /* if a parenthesis is found, warn about invalid form.  */
+      /* If a parenthesis is found, warn about invalid form.  */
       if (**strp == '(')
 	errmsg = _("illegal use of parentheses");
 
-      /* if a numeric value is specified, ensure that it is between
+      /* If a numeric value is specified, ensure that it is between
 	 1 and 255.  */
       else if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
 	{
@@ -233,11 +221,10 @@ parse_fr (cd, strp, opindex, valuep)
 }
 
 static const char *
-parse_addr16 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_addr16 (CGEN_CPU_DESC cd,
+	      const char **strp,
+	      int opindex,
+	      unsigned long *valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
@@ -250,7 +237,7 @@ parse_addr16 (cd, strp, opindex, valuep)
     code = BFD_RELOC_IP2K_LO8DATA;
   else
     {
-      /* Something is very wrong. opindex has to be one of the above. */
+      /* Something is very wrong. opindex has to be one of the above.  */
       errmsg = _("parse_addr16: invalid opindex.");
       return errmsg;
     }
@@ -259,13 +246,14 @@ parse_addr16 (cd, strp, opindex, valuep)
 			       & result_type, & value);
   if (errmsg == NULL)
     {
-      /* We either have a relocation or a number now. */
+      /* We either have a relocation or a number now.  */
       if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
 	{
-	  /* We got a number back. */
+	  /* We got a number back.  */
 	  if (code == BFD_RELOC_IP2K_HI8DATA)
             value >>= 8;
-	  else    /* code = BFD_RELOC_IP2K_LOW8DATA */
+	  else
+	    /* code = BFD_RELOC_IP2K_LOW8DATA.  */
 	    value &= 0x00FF;
 	}   
       *valuep = value;
@@ -274,13 +262,11 @@ parse_addr16 (cd, strp, opindex, valuep)
   return errmsg;
 }
 
-
 static const char *
-parse_addr16_cjp (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_addr16_cjp (CGEN_CPU_DESC cd,
+		  const char **strp,
+		  int opindex,
+		  unsigned long *valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
@@ -301,7 +287,7 @@ parse_addr16_cjp (cd, strp, opindex, valuep)
 	  if ((value & 0x1) == 0)  /* If the address is even .... */
 	    {
 	      if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16CJP)
-                *valuep = (value >> 1) & 0x1FFF;  /* Should mask be 1FFF? */
+                *valuep = (value >> 1) & 0x1FFF;  /* Should mask be 1FFF?  */
 	      else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16P)
                 *valuep = (value >> 14) & 0x7;
 	    }
@@ -320,20 +306,18 @@ parse_addr16_cjp (cd, strp, opindex, valuep)
   return errmsg; 
 }
 
-
 static const char *
-parse_lit8 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     long *valuep;
+parse_lit8 (CGEN_CPU_DESC cd,
+	    const char **strp,
+	    int opindex,
+	    long *valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
   bfd_reloc_code_real_type code = BFD_RELOC_NONE;
   bfd_vma value;
 
-  /* Parse %OP relocating operators. */
+  /* Parse %OP relocating operators.  */
   if (strncmp (*strp, "%bank", 5) == 0)
     {
       *strp += 5;
@@ -364,7 +348,6 @@ parse_lit8 (cd, strp, opindex, valuep)
       *strp += 8;
       code = BFD_RELOC_IP2K_HI8INSN;
     }
-  
 
   /* Parse %op operand.  */
   if (code != BFD_RELOC_NONE)
@@ -382,7 +365,7 @@ parse_lit8 (cd, strp, opindex, valuep)
     {
       errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep);
 
-      /* Truncate to eight bits to accept both signed and unsigned input. */
+      /* Truncate to eight bits to accept both signed and unsigned input.  */
       if (errmsg == NULL)
 	*valuep &= 0xFF;
     }
@@ -391,11 +374,10 @@ parse_lit8 (cd, strp, opindex, valuep)
 }
 
 static const char *
-parse_bit3 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_bit3 (CGEN_CPU_DESC cd,
+	    const char **strp,
+	    int opindex,
+	    unsigned long *valuep)
 {
   const char *errmsg;
   char mode = 0;
@@ -456,11 +438,10 @@ parse_bit3 (cd, strp, opindex, valuep)
   return errmsg;
 }
 
-
 /* -- dis.c */
 
 const char * ip2k_cgen_parse_operand
-  PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
 
 /* Main entry point for operand parsing.
 
@@ -476,11 +457,10 @@ const char * ip2k_cgen_parse_operand
    the handlers.  */
 
 const char *
-ip2k_cgen_parse_operand (cd, opindex, strp, fields)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     const char ** strp;
-     CGEN_FIELDS * fields;
+ip2k_cgen_parse_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   const char ** strp,
+			   CGEN_FIELDS * fields)
 {
   const char * errmsg = NULL;
   /* Used by scalar operands that still need to be parsed.  */
@@ -540,8 +520,7 @@ cgen_parse_fn * const ip2k_cgen_parse_handlers[] =
 };
 
 void
-ip2k_cgen_init_asm (cd)
-     CGEN_CPU_DESC cd;
+ip2k_cgen_init_asm (CGEN_CPU_DESC cd)
 {
   ip2k_cgen_init_opcode_table (cd);
   ip2k_cgen_init_ibld_table (cd);
@@ -924,30 +903,3 @@ ip2k_cgen_assemble_insn (CGEN_CPU_DESC cd,
     return NULL;
   }
 }
-
-#if 0 /* This calls back to GAS which we can't do without care.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   This lets GAS parse registers for us.
-   ??? Interesting idea but not currently used.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   FIXME: Not currently used.  */
-
-void
-ip2k_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
-{
-  CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
-  const CGEN_KEYWORD_ENTRY * ke;
-
-  while ((ke = cgen_keyword_search_next (& search)) != NULL)
-    {
-#if 0 /* Unnecessary, should be done in the search routine.  */
-      if (! ip2k_cgen_opval_supported (ke))
-	continue;
-#endif
-      cgen_asm_record_register (cd, ke->name, ke->value);
-    }
-}
-
-#endif /* 0 */
diff --git a/opcodes/ip2k-desc.c b/opcodes/ip2k-desc.c
index eece4f5..ca48ba2 100644
--- a/opcodes/ip2k-desc.c
+++ b/opcodes/ip2k-desc.c
@@ -858,27 +858,23 @@ static const CGEN_IBASE ip2k_cgen_insn_table[MAX_INSNS] =
 #undef A
 
 /* Initialize anything needed to be done once, before any cpu_open call.  */
-static void init_tables PARAMS ((void));
 
 static void
-init_tables ()
+init_tables (void)
 {
 }
 
-static const CGEN_MACH * lookup_mach_via_bfd_name
-  PARAMS ((const CGEN_MACH *, const char *));
-static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
-static void ip2k_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
+static void build_hw_table      (CGEN_CPU_TABLE *);
+static void build_ifield_table  (CGEN_CPU_TABLE *);
+static void build_operand_table (CGEN_CPU_TABLE *);
+static void build_insn_table    (CGEN_CPU_TABLE *);
+static void ip2k_cgen_rebuild_tables (CGEN_CPU_TABLE *);
 
 /* Subroutine of ip2k_cgen_cpu_open to look up a mach via its bfd name.  */
 
 static const CGEN_MACH *
-lookup_mach_via_bfd_name (table, name)
-     const CGEN_MACH *table;
-     const char *name;
+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
 {
   while (table->name)
     {
@@ -892,8 +888,7 @@ lookup_mach_via_bfd_name (table, name)
 /* Subroutine of ip2k_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_hw_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_hw_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -919,8 +914,7 @@ build_hw_table (cd)
 /* Subroutine of ip2k_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_ifield_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_ifield_table (CGEN_CPU_TABLE *cd)
 {
   cd->ifld_table = & ip2k_cgen_ifld_table[0];
 }
@@ -928,8 +922,7 @@ build_ifield_table (cd)
 /* Subroutine of ip2k_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_operand_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_operand_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -937,8 +930,7 @@ build_operand_table (cd)
   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
      However each entry is indexed by it's enum so there can be holes in
      the table.  */
-  const CGEN_OPERAND **selected =
-    (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
 
   cd->operand_table.init_entries = init;
   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@@ -961,12 +953,11 @@ build_operand_table (cd)
    operand elements to be in the table [which they mightn't be].  */
 
 static void
-build_insn_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_insn_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   const CGEN_IBASE *ib = & ip2k_cgen_insn_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
 
   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
   for (i = 0; i < MAX_INSNS; ++i)
@@ -979,8 +970,7 @@ build_insn_table (cd)
 /* Subroutine of ip2k_cgen_cpu_open to rebuild the tables.  */
 
 static void
-ip2k_cgen_rebuild_tables (cd)
-     CGEN_CPU_TABLE *cd;
+ip2k_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
   unsigned int isas = cd->isas;
@@ -992,7 +982,7 @@ ip2k_cgen_rebuild_tables (cd)
 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
   cd->default_insn_bitsize = UNSET;
   cd->base_insn_bitsize = UNSET;
-  cd->min_insn_bitsize = 65535; /* some ridiculously big number */
+  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
     if (((1 << i) & isas) != 0)
@@ -1004,7 +994,7 @@ ip2k_cgen_rebuild_tables (cd)
 	if (cd->default_insn_bitsize == UNSET)
 	  cd->default_insn_bitsize = isa->default_insn_bitsize;
 	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -1013,7 +1003,7 @@ ip2k_cgen_rebuild_tables (cd)
 	if (cd->base_insn_bitsize == UNSET)
 	  cd->base_insn_bitsize = isa->base_insn_bitsize;
 	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -1125,12 +1115,12 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     }
   va_end (ap);
 
-  /* mach unspecified means "all" */
+  /* Mach unspecified means "all".  */
   if (machs == 0)
     machs = (1 << MAX_MACHS) - 1;
-  /* base mach is always selected */
+  /* Base mach is always selected.  */
   machs |= 1;
-  /* isa unspecified means "all" */
+  /* ISA unspecified means "all".  */
   if (isas == 0)
     isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
@@ -1163,9 +1153,7 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
    MACH_NAME is the bfd name of the mach.  */
 
 CGEN_CPU_DESC
-ip2k_cgen_cpu_open_1 (mach_name, endian)
-     const char *mach_name;
-     enum cgen_endian endian;
+ip2k_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
 {
   return ip2k_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
 			       CGEN_CPU_OPEN_ENDIAN, endian,
@@ -1178,8 +1166,7 @@ ip2k_cgen_cpu_open_1 (mach_name, endian)
    place as some simulator ports use this but they don't use libopcodes.  */
 
 void
-ip2k_cgen_cpu_close (cd)
-     CGEN_CPU_DESC cd;
+ip2k_cgen_cpu_close (CGEN_CPU_DESC cd)
 {
   unsigned int i;
   const CGEN_INSN *insns;
@@ -1188,23 +1175,17 @@ ip2k_cgen_cpu_close (cd)
     {
       insns = cd->macro_insn_table.init_entries;
       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX ((insns)))
-	    regfree (CGEN_INSN_RX (insns));
-	}
+	if (CGEN_INSN_RX ((insns)))
+	  regfree (CGEN_INSN_RX (insns));
     }
 
   if (cd->insn_table.init_entries)
     {
       insns = cd->insn_table.init_entries;
       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX (insns))
-	    regfree (CGEN_INSN_RX (insns));
-	}
-    }
-
-  
+	if (CGEN_INSN_RX (insns))
+	  regfree (CGEN_INSN_RX (insns));
+    }  
 
   if (cd->macro_insn_table.init_entries)
     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
diff --git a/opcodes/ip2k-dis.c b/opcodes/ip2k-dis.c
index 77bd3a8..7b43ccb 100644
--- a/opcodes/ip2k-dis.c
+++ b/opcodes/ip2k-dis.c
@@ -1,27 +1,27 @@
 /* Disassembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-dis.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-dis.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
-Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -56,30 +56,17 @@ static int read_insn
   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
    unsigned long *);
 
-/* -- disassembler routines inserted here */
+/* -- disassembler routines inserted here.  */
 
 /* -- dis.c */
 
-#define PRINT_FUNC_DECL(name) \
-static void name PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int))
-
-PRINT_FUNC_DECL (print_fr);
-PRINT_FUNC_DECL (print_dollarhex);
-PRINT_FUNC_DECL (print_dollarhex8);
-PRINT_FUNC_DECL (print_dollarhex_addr16h);
-PRINT_FUNC_DECL (print_dollarhex_addr16l);
-PRINT_FUNC_DECL (print_dollarhex_p);
-PRINT_FUNC_DECL (print_dollarhex_cj);
-PRINT_FUNC_DECL (print_decimal);
-
 static void
-print_fr (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_fr (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	  void * dis_info,
+	  long value,
+	  unsigned int attrs ATTRIBUTE_UNUSED,
+	  bfd_vma pc ATTRIBUTE_UNUSED,
+	  int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
   const CGEN_KEYWORD_ENTRY *ke;
@@ -87,7 +74,7 @@ print_fr (cd, dis_info, value, attrs, pc, length)
   long offsettest;
   long offsetvalue;
 
-  if ( value == 0 ) /* This is (IP) */
+  if (value == 0) /* This is (IP).  */
     {
       (*info->fprintf_func) (info->stream, "%s", "(IP)");
       return;
@@ -96,46 +83,43 @@ print_fr (cd, dis_info, value, attrs, pc, length)
   offsettest = value >> 7;
   offsetvalue = value & 0x7F;
 
-  /* Check to see if first two bits are 10 -> (DP) */
-  if ( offsettest == 2 )
+  /* Check to see if first two bits are 10 -> (DP).  */
+  if (offsettest == 2)
     {
-      if ( offsetvalue == 0 )
+      if (offsetvalue == 0)
 	(*info->fprintf_func) (info->stream, "%s","(DP)");
       else
 	(*info->fprintf_func) (info->stream, "$%x%s",offsetvalue, "(DP)");
       return;
     }
 
-  /* Check to see if first two bits are 11 -> (SP) */
-  if ( offsettest == 3 )
+  /* Check to see if first two bits are 11 -> (SP).  */
+  if (offsettest == 3)
     {
-      if ( offsetvalue == 0 )
+      if (offsetvalue == 0)
 	(*info->fprintf_func) (info->stream, "%s", "(SP)");
       else
 	(*info->fprintf_func) (info->stream, "$%x%s", offsetvalue,"(SP)");
       return;
     }
 
-  /* Attempt to print as a register keyword. */
+  /* Attempt to print as a register keyword.  */
   ke = cgen_keyword_lookup_value (& ip2k_cgen_opval_register_names, value);
-  if (ke != NULL)
-    {
-      (*info->fprintf_func) (info->stream, "%s", ke->name);
-      return;
-    }
 
-  /* Print as an address literal. */
-  (*info->fprintf_func) (info->stream, "$%02x", value);
+  if (ke != NULL)
+    (*info->fprintf_func) (info->stream, "%s", ke->name);
+  else
+    /* Print as an address literal.  */
+    (*info->fprintf_func) (info->stream, "$%02x", value);
 }
 
 static void
-print_dollarhex (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		 void * dis_info,
+		 long value,
+		 unsigned int attrs ATTRIBUTE_UNUSED,
+		 bfd_vma pc ATTRIBUTE_UNUSED,
+		 int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -143,13 +127,12 @@ print_dollarhex (cd, dis_info, value, attrs, pc, length)
 }
 
 static void
-print_dollarhex8 (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_dollarhex8 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		  void * dis_info,
+		  long value,
+		  unsigned int attrs ATTRIBUTE_UNUSED,
+		  bfd_vma pc ATTRIBUTE_UNUSED,
+		  int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -157,31 +140,29 @@ print_dollarhex8 (cd, dis_info, value, attrs, pc, length)
 }
 
 static void
-print_dollarhex_addr16h (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_dollarhex_addr16h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			 void * dis_info,
+			 long value,
+			 unsigned int attrs ATTRIBUTE_UNUSED,
+			 bfd_vma pc ATTRIBUTE_UNUSED,
+			 int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
-  /* This is a loadh instruction. Shift the value to the left      */
-  /* by 8 bits so that disassembled code will reassemble properly. */
+  /* This is a loadh instruction. Shift the value to the left
+     by 8 bits so that disassembled code will reassemble properly.  */
   value = ((value << 8) & 0xFF00);
 
   (*info->fprintf_func) (info->stream, "$%04x", value);
 }
 
 static void
-print_dollarhex_addr16l (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_dollarhex_addr16l (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			 void * dis_info,
+			 long value,
+			 unsigned int attrs ATTRIBUTE_UNUSED,
+			 bfd_vma pc ATTRIBUTE_UNUSED,
+			 int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -189,13 +170,12 @@ print_dollarhex_addr16l (cd, dis_info, value, attrs, pc, length)
 }
 
 static void
-print_dollarhex_p (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_dollarhex_p (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		   void * dis_info,
+		   long value,
+		   unsigned int attrs ATTRIBUTE_UNUSED,
+		   bfd_vma pc ATTRIBUTE_UNUSED,
+		   int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -205,13 +185,12 @@ print_dollarhex_p (cd, dis_info, value, attrs, pc, length)
 }
 
 static void
-print_dollarhex_cj (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_dollarhex_cj (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    void * dis_info,
+		    long value,
+		    unsigned int attrs ATTRIBUTE_UNUSED,
+		    bfd_vma pc ATTRIBUTE_UNUSED,
+		    int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -219,15 +198,13 @@ print_dollarhex_cj (cd, dis_info, value, attrs, pc, length)
   (*info->fprintf_func) (info->stream, "$%05x", value);
 }
 
-
 static void
-print_decimal (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_decimal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void * dis_info,
+	       long value,
+	       unsigned int attrs ATTRIBUTE_UNUSED,
+	       bfd_vma pc ATTRIBUTE_UNUSED,
+	       int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -239,8 +216,7 @@ print_decimal (cd, dis_info, value, attrs, pc, length)
 /* -- */
 
 void ip2k_cgen_print_operand
-  PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
-           void const *, bfd_vma, int));
+  (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
 
 /* Main entry point for printing operands.
    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@@ -258,16 +234,15 @@ void ip2k_cgen_print_operand
    the handlers.  */
 
 void
-ip2k_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     PTR xinfo;
-     CGEN_FIELDS *fields;
-     void const *attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     int length;
+ip2k_cgen_print_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   void * xinfo,
+			   CGEN_FIELDS *fields,
+			   void const *attrs ATTRIBUTE_UNUSED,
+			   bfd_vma pc,
+			   int length)
 {
- disassemble_info *info = (disassemble_info *) xinfo;
+  disassemble_info *info = (disassemble_info *) xinfo;
 
   switch (opindex)
     {
@@ -323,8 +298,7 @@ cgen_print_fn * const ip2k_cgen_print_handlers[] =
 
 
 void
-ip2k_cgen_init_dis (cd)
-     CGEN_CPU_DESC cd;
+ip2k_cgen_init_dis (CGEN_CPU_DESC cd)
 {
   ip2k_cgen_init_opcode_table (cd);
   ip2k_cgen_init_ibld_table (cd);
@@ -376,7 +350,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 
   /* Print the operand as directed by the attributes.  */
   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
-    ; /* nothing to do */
+    ; /* Nothing to do.  */
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
     (*info->print_address_func) (value, info);
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@@ -458,6 +432,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
+
   if (status != 0)
     {
       (*info->memory_error_func) (status, pc, info);
@@ -562,13 +537,13 @@ print_insn (CGEN_CPU_DESC cd,
 	    length = CGEN_EXTRACT_FN (cd, insn)
 	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 
-	  /* length < 0 -> error */
+	  /* Length < 0 -> error.  */
 	  if (length < 0)
 	    return length;
 	  if (length > 0)
 	    {
 	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
-	      /* length is in bits, result is in bytes */
+	      /* Length is in bits, result is in bytes.  */
 	      return length / 8;
 	    }
 	}
@@ -618,7 +593,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
    Print one instruction from PC on INFO->STREAM.
    Return the size of the instruction (in bytes).  */
 
-typedef struct cpu_desc_list {
+typedef struct cpu_desc_list
+{
   struct cpu_desc_list *next;
   int isa;
   int mach;
@@ -703,7 +679,7 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info)
       if (!cd)
 	abort ();
 
-      /* save this away for future reference */
+      /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
       cl->isa = isa;
diff --git a/opcodes/ip2k-ibld.c b/opcodes/ip2k-ibld.c
index b098158..cd39392 100644
--- a/opcodes/ip2k-ibld.c
+++ b/opcodes/ip2k-ibld.c
@@ -1,25 +1,26 @@
 /* Instruction building/extraction support for ip2k. -*- C -*-
 
-THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
-- the resultant file is machine generated, cgen-ibld.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+   - the resultant file is machine generated, cgen-ibld.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #include "opintl.h"
 #include "safe-ctype.h"
 
-#undef min
+#undef  min
 #define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
+#undef  max
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 /* Used by the ifield rtx function.  */
@@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
   if (length == 0)
     return NULL;
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
 
 #if CGEN_INT_INSN_P
 /* Cover function to store an insn value into an integral insn.  Must go here
- because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
+   because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
       int shift = insn_length - length;
       /* Written this way to avoid undefined behaviour.  */
       CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
       *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
     }
 }
@@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
 {
   unsigned long x;
   int shift;
-#if 0
-  int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
-#endif
+
   x = cgen_get_insn_value (cd, bufp, word_length);
 
   if (CGEN_INSN_LSB0_P)
@@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
       return 1;
     }
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
   return CGEN_INSN_BITSIZE (insn);
 }
 
-/* machine generated code added here */
+/* Machine generated code added here.  */
 
 const char * ip2k_cgen_insert_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 
 /* Main entry point for operand insertion.
 
@@ -559,12 +547,11 @@ const char * ip2k_cgen_insert_operand
    resolved during parsing.  */
 
 const char *
-ip2k_cgen_insert_operand (cd, opindex, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+ip2k_cgen_insert_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     CGEN_INSN_BYTES_PTR buffer,
+			     bfd_vma pc ATTRIBUTE_UNUSED)
 {
   const char * errmsg = NULL;
   unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@@ -615,8 +602,7 @@ ip2k_cgen_insert_operand (cd, opindex, fields, buffer, pc)
 }
 
 int ip2k_cgen_extract_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-           CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 
 /* Main entry point for operand extraction.
    The result is <= 0 for error, >0 for success.
@@ -634,13 +620,12 @@ int ip2k_cgen_extract_operand
    the handlers.  */
 
 int
-ip2k_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS * fields;
-     bfd_vma pc;
+ip2k_cgen_extract_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_EXTRACT_INFO *ex_info,
+			     CGEN_INSN_INT insn_value,
+			     CGEN_FIELDS * fields,
+			     bfd_vma pc)
 {
   /* Assume success (for those operands that are nops).  */
   int length = 1;
@@ -701,10 +686,8 @@ cgen_extract_fn * const ip2k_cgen_extract_handlers[] =
   extract_insn_normal,
 };
 
-int ip2k_cgen_get_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
-bfd_vma ip2k_cgen_get_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+int ip2k_cgen_get_int_operand     (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+bfd_vma ip2k_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
 
 /* Getting values from cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they return.
@@ -712,10 +695,9 @@ bfd_vma ip2k_cgen_get_vma_operand
    not appropriate.  */
 
 int
-ip2k_cgen_get_int_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+ip2k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   int value;
 
@@ -769,10 +751,9 @@ ip2k_cgen_get_int_operand (cd, opindex, fields)
 }
 
 bfd_vma
-ip2k_cgen_get_vma_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+ip2k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   bfd_vma value;
 
@@ -825,10 +806,8 @@ ip2k_cgen_get_vma_operand (cd, opindex, fields)
   return value;
 }
 
-void ip2k_cgen_set_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
-void ip2k_cgen_set_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+void ip2k_cgen_set_int_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
+void ip2k_cgen_set_vma_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
 
 /* Stuffing values in cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they accept.
@@ -836,11 +815,10 @@ void ip2k_cgen_set_vma_operand
    not appropriate.  */
 
 void
-ip2k_cgen_set_int_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     int value;
+ip2k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     int value)
 {
   switch (opindex)
     {
@@ -886,11 +864,10 @@ ip2k_cgen_set_int_operand (cd, opindex, fields, value)
 }
 
 void
-ip2k_cgen_set_vma_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     bfd_vma value;
+ip2k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     bfd_vma value)
 {
   switch (opindex)
     {
@@ -938,8 +915,7 @@ ip2k_cgen_set_vma_operand (cd, opindex, fields, value)
 /* Function to call before using the instruction builder tables.  */
 
 void
-ip2k_cgen_init_ibld_table (cd)
-     CGEN_CPU_DESC cd;
+ip2k_cgen_init_ibld_table (CGEN_CPU_DESC cd)
 {
   cd->insert_handlers = & ip2k_cgen_insert_handlers[0];
   cd->extract_handlers = & ip2k_cgen_extract_handlers[0];
diff --git a/opcodes/ip2k-opc.c b/opcodes/ip2k-opc.c
index ad4cf5b..dd4648f 100644
--- a/opcodes/ip2k-opc.c
+++ b/opcodes/ip2k-opc.c
@@ -34,16 +34,15 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 
 #include "safe-ctype.h"
 
-/* A better hash function for instruction mnemonics. */
+/* A better hash function for instruction mnemonics.  */
 unsigned int
-ip2k_asm_hash (insn)
-     const char* insn;
+ip2k_asm_hash (const char* insn)
 {
   unsigned int hash;
   const char* m = insn;
 
-  for (hash = 0; *m && !ISSPACE(*m); m++)
-    hash = (hash * 23) ^ (0x1F & TOLOWER(*m));
+  for (hash = 0; *m && ! ISSPACE (*m); m++)
+    hash = (hash * 23) ^ (0x1F & TOLOWER (*m));
 
   /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */
 
@@ -51,11 +50,10 @@ ip2k_asm_hash (insn)
 }
 
 
-/* Special check to ensure that instruction exists for given machine. */
+/* Special check to ensure that instruction exists for given machine.  */
+
 int
-ip2k_cgen_insn_supported (cd, insn)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
+ip2k_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
 {
   int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
 
@@ -63,7 +61,7 @@ ip2k_cgen_insn_supported (cd, insn)
   if (machs == 0)
     return 1;
   
-  return ((machs & cd->machs) != 0);
+  return (machs & cd->machs) != 0;
 }
 
 
@@ -71,10 +69,10 @@ ip2k_cgen_insn_supported (cd, insn)
 /* The hash functions are recorded here to help keep assembler code out of
    the disassembler and vice versa.  */
 
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static int asm_hash_insn_p        (const CGEN_INSN *);
+static unsigned int asm_hash_insn (const char *);
+static int dis_hash_insn_p        (const CGEN_INSN *);
+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
 
 /* Instruction formats.  */
 
@@ -873,14 +871,10 @@ dis_hash_insn (buf, value)
   return CGEN_DIS_HASH (buf, value);
 }
 
-static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
-
 /* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
 
 static void
-set_fields_bitsize (fields, size)
-     CGEN_FIELDS *fields;
-     int size;
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
 {
   CGEN_FIELDS_BITSIZE (fields) = size;
 }
@@ -889,15 +883,15 @@ set_fields_bitsize (fields, size)
    This plugs the opcode entries and macro instructions into the cpu table.  */
 
 void
-ip2k_cgen_init_opcode_table (cd)
-     CGEN_CPU_DESC cd;
+ip2k_cgen_init_opcode_table (CGEN_CPU_DESC cd)
 {
   int i;
   int num_macros = (sizeof (ip2k_cgen_macro_insn_table) /
 		    sizeof (ip2k_cgen_macro_insn_table[0]));
   const CGEN_IBASE *ib = & ip2k_cgen_macro_insn_table[0];
   const CGEN_OPCODE *oc = & ip2k_cgen_macro_insn_opcode_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
+
   memset (insns, 0, num_macros * sizeof (CGEN_INSN));
   for (i = 0; i < num_macros; ++i)
     {
diff --git a/opcodes/ip2k-opc.h b/opcodes/ip2k-opc.h
index 6d0d016..17b76dc 100644
--- a/opcodes/ip2k-opc.h
+++ b/opcodes/ip2k-opc.h
@@ -36,14 +36,14 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* Override disassembly hashing - there are variable bits in the top
    byte of these instructions.  */
 #define CGEN_DIS_HASH_SIZE 8
-#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)
+#define CGEN_DIS_HASH(buf, value) \
+  (((* (unsigned char*) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)
 
 #define CGEN_ASM_HASH_SIZE 127
-#define CGEN_ASM_HASH(insn) ip2k_asm_hash(insn)
+#define CGEN_ASM_HASH(insn) ip2k_asm_hash (insn)
 
-extern unsigned int ip2k_asm_hash PARAMS ((const char *insn));
-extern int ip2k_cgen_insn_supported
-  PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *));
+extern unsigned int ip2k_asm_hash (const char *);
+extern int ip2k_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
 
 /* -- opc.c */
 /* Enum declaration for ip2k instruction types.  */
diff --git a/opcodes/iq2000-asm.c b/opcodes/iq2000-asm.c
index 32991d6..0bbb4ae 100644
--- a/opcodes/iq2000-asm.c
+++ b/opcodes/iq2000-asm.c
@@ -1,26 +1,27 @@
 /* Assembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-asm.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-asm.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -51,30 +52,24 @@ static const char * parse_insn_normal
 
 #include "safe-ctype.h"
 
-static int iq2000_cgen_isa_register PARAMS ((const char **));
-static const char * parse_jtargq10 PARAMS ((CGEN_CPU_DESC, const char **, int, int, enum cgen_parse_operand_result *, bfd_vma *));
-static const char * parse_mimm PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_imm  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_lo16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_mlo16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
+
+/* Special check to ensure that instruction exists for given machine.  */
 
-/* Special check to ensure that instruction exists for given machine */
 int
-iq2000_cgen_insn_supported (cd, insn)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
+iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
 {
   int machs = cd->machs;
 
-  return ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0);
+  return (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0;
 }
 
-static int iq2000_cgen_isa_register (strp)
-     const char **strp;
+static int
+iq2000_cgen_isa_register (const char **strp)
 {
   int len;
   int ch1, ch2;
+
   if (**strp == 'r' || **strp == 'R') 
     {
       len = strlen (*strp);
@@ -94,7 +89,9 @@ static int iq2000_cgen_isa_register (strp)
             return 1;
         }
     }
-  if (**strp == '%' && TOLOWER((*strp)[1]) != 'l' && TOLOWER((*strp)[1]) != 'h')
+  if (**strp == '%'
+      && TOLOWER ((*strp)[1]) != 'l'
+      && TOLOWER ((*strp)[1]) != 'h')
     return 1;
   return 0;
 }
@@ -102,11 +99,10 @@ static int iq2000_cgen_isa_register (strp)
 /* Handle negated literal.  */
 
 static const char *
-parse_mimm (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_mimm (CGEN_CPU_DESC cd,
+	    const char **strp,
+	    int opindex,
+	    unsigned long *valuep)
 {
   const char *errmsg;
 
@@ -134,11 +130,10 @@ parse_mimm (cd, strp, opindex, valuep)
 /* Handle signed/unsigned literal.  */
 
 static const char *
-parse_imm (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_imm (CGEN_CPU_DESC cd,
+	   const char **strp,
+	   int opindex,
+	   unsigned long *valuep)
 {
   const char *errmsg;
 
@@ -152,6 +147,7 @@ parse_imm (cd, strp, opindex, valuep)
       if (errmsg == NULL)
 	{
 	  long x = value & 0xFFFF0000;
+
 	  if (x != 0 && x != (long) 0xFFFF0000)
 	    errmsg = _("immediate value out of range");
 	  else
@@ -164,23 +160,23 @@ parse_imm (cd, strp, opindex, valuep)
 /* Handle iq10 21-bit jmp offset.  */
 
 static const char *
-parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     int reloc ATTRIBUTE_UNUSED;
-     enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED;
-     bfd_vma *valuep;
+parse_jtargq10 (CGEN_CPU_DESC cd,
+		const char **strp,
+		int opindex,
+		int reloc ATTRIBUTE_UNUSED,
+		enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED,
+		bfd_vma *valuep)
 {
   const char *errmsg;
   bfd_vma value;
   enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER;
 
   errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21,
-			       &result_type, &value);
+			       & result_type, & value);
   if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
     {
-      /* Check value is within 23-bits (remembering that 2-bit shift right will occur).  */
+      /* Check value is within 23-bits
+	 (remembering that 2-bit shift right will occur).  */
       if (value > 0x7fffff)
         return _("21-bit offset out of range");
     }
@@ -191,11 +187,10 @@ parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep)
 /* Handle high().  */
 
 static const char *
-parse_hi16 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_hi16 (CGEN_CPU_DESC cd,
+	    const char **strp,
+	    int opindex,
+	    unsigned long *valuep)
 {
   if (strncasecmp (*strp, "%hi(", 4) == 0)
     {
@@ -205,17 +200,17 @@ parse_hi16 (cd, strp, opindex, valuep)
 
       *strp += 4;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
-				   &result_type, &value);
+				   & result_type, & value);
       if (**strp != ')')
-	return _("missing `)'");
+	return MISSING_CLOSING_PARENTHESIS;
 
       ++*strp;
       if (errmsg == NULL
   	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
 	{
-	  /* if value has top-bit of %lo on, then it will
+	  /* If value has top-bit of %lo on, then it will
 	     sign-propagate and so we compensate by adding
-	     1 to the resultant %hi value */
+	     1 to the resultant %hi value.  */
 	  if (value & 0x8000)
 	    value += 0x10000;
 	  value >>= 16;
@@ -225,8 +220,8 @@ parse_hi16 (cd, strp, opindex, valuep)
       return errmsg;
     }
 
-  /* we add %uhi in case a user just wants the high 16-bits or is using
-     an insn like ori for %lo which does not sign-propagate */
+  /* We add %uhi in case a user just wants the high 16-bits or is using
+     an insn like ori for %lo which does not sign-propagate.  */
   if (strncasecmp (*strp, "%uhi(", 5) == 0)
     {
       enum cgen_parse_operand_result result_type;
@@ -235,16 +230,15 @@ parse_hi16 (cd, strp, opindex, valuep)
 
       *strp += 5;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16,
-				   &result_type, &value);
+				   & result_type, & value);
       if (**strp != ')')
-	return _("missing `)'");
+	return MISSING_CLOSING_PARENTHESIS;
 
       ++*strp;
       if (errmsg == NULL
   	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
-	{
-	  value >>= 16;
-	}
+	value >>= 16;
+
       *valuep = value;
 
       return errmsg;
@@ -258,11 +252,10 @@ parse_hi16 (cd, strp, opindex, valuep)
    handles the case where %lo() isn't present.  */
 
 static const char *
-parse_lo16 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_lo16 (CGEN_CPU_DESC cd,
+	    const char **strp,
+	    int opindex,
+	    long *valuep)
 {
   if (strncasecmp (*strp, "%lo(", 4) == 0)
     {
@@ -272,9 +265,9 @@ parse_lo16 (cd, strp, opindex, valuep)
 
       *strp += 4;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
-				   &result_type, &value);
+				   & result_type, & value);
       if (**strp != ')')
-	return _("missing `)'");
+	return MISSING_CLOSING_PARENTHESIS;
       ++*strp;
       if (errmsg == NULL
 	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@@ -291,11 +284,10 @@ parse_lo16 (cd, strp, opindex, valuep)
    handles the case where %lo() isn't present.  */
 
 static const char *
-parse_mlo16 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_mlo16 (CGEN_CPU_DESC cd,
+	     const char **strp,
+	     int opindex,
+	     long *valuep)
 {
   if (strncasecmp (*strp, "%lo(", 4) == 0)
     {
@@ -305,9 +297,9 @@ parse_mlo16 (cd, strp, opindex, valuep)
 
       *strp += 4;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
-				   &result_type, &value);
+				   & result_type, & value);
       if (**strp != ')')
-	return _("missing `)'");
+	return MISSING_CLOSING_PARENTHESIS;
       ++*strp;
       if (errmsg == NULL
 	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@@ -322,7 +314,7 @@ parse_mlo16 (cd, strp, opindex, valuep)
 /* -- */
 
 const char * iq2000_cgen_parse_operand
-  PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
 
 /* Main entry point for operand parsing.
 
@@ -338,11 +330,10 @@ const char * iq2000_cgen_parse_operand
    the handlers.  */
 
 const char *
-iq2000_cgen_parse_operand (cd, opindex, strp, fields)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     const char ** strp;
-     CGEN_FIELDS * fields;
+iq2000_cgen_parse_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   const char ** strp,
+			   CGEN_FIELDS * fields)
 {
   const char * errmsg = NULL;
   /* Used by scalar operands that still need to be parsed.  */
@@ -475,8 +466,7 @@ cgen_parse_fn * const iq2000_cgen_parse_handlers[] =
 };
 
 void
-iq2000_cgen_init_asm (cd)
-     CGEN_CPU_DESC cd;
+iq2000_cgen_init_asm (CGEN_CPU_DESC cd)
 {
   iq2000_cgen_init_opcode_table (cd);
   iq2000_cgen_init_ibld_table (cd);
@@ -859,30 +849,3 @@ iq2000_cgen_assemble_insn (CGEN_CPU_DESC cd,
     return NULL;
   }
 }
-
-#if 0 /* This calls back to GAS which we can't do without care.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   This lets GAS parse registers for us.
-   ??? Interesting idea but not currently used.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   FIXME: Not currently used.  */
-
-void
-iq2000_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
-{
-  CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
-  const CGEN_KEYWORD_ENTRY * ke;
-
-  while ((ke = cgen_keyword_search_next (& search)) != NULL)
-    {
-#if 0 /* Unnecessary, should be done in the search routine.  */
-      if (! iq2000_cgen_opval_supported (ke))
-	continue;
-#endif
-      cgen_asm_record_register (cd, ke->name, ke->value);
-    }
-}
-
-#endif /* 0 */
diff --git a/opcodes/iq2000-desc.c b/opcodes/iq2000-desc.c
index 8cf95e6..39bda64 100644
--- a/opcodes/iq2000-desc.c
+++ b/opcodes/iq2000-desc.c
@@ -1863,27 +1863,23 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
 #undef A
 
 /* Initialize anything needed to be done once, before any cpu_open call.  */
-static void init_tables PARAMS ((void));
 
 static void
-init_tables ()
+init_tables (void)
 {
 }
 
-static const CGEN_MACH * lookup_mach_via_bfd_name
-  PARAMS ((const CGEN_MACH *, const char *));
-static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
-static void iq2000_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
+static void build_hw_table      (CGEN_CPU_TABLE *);
+static void build_ifield_table  (CGEN_CPU_TABLE *);
+static void build_operand_table (CGEN_CPU_TABLE *);
+static void build_insn_table    (CGEN_CPU_TABLE *);
+static void iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *);
 
 /* Subroutine of iq2000_cgen_cpu_open to look up a mach via its bfd name.  */
 
 static const CGEN_MACH *
-lookup_mach_via_bfd_name (table, name)
-     const CGEN_MACH *table;
-     const char *name;
+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
 {
   while (table->name)
     {
@@ -1897,8 +1893,7 @@ lookup_mach_via_bfd_name (table, name)
 /* Subroutine of iq2000_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_hw_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_hw_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -1924,8 +1919,7 @@ build_hw_table (cd)
 /* Subroutine of iq2000_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_ifield_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_ifield_table (CGEN_CPU_TABLE *cd)
 {
   cd->ifld_table = & iq2000_cgen_ifld_table[0];
 }
@@ -1933,8 +1927,7 @@ build_ifield_table (cd)
 /* Subroutine of iq2000_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_operand_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_operand_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -1942,8 +1935,7 @@ build_operand_table (cd)
   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
      However each entry is indexed by it's enum so there can be holes in
      the table.  */
-  const CGEN_OPERAND **selected =
-    (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
 
   cd->operand_table.init_entries = init;
   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@@ -1966,12 +1958,11 @@ build_operand_table (cd)
    operand elements to be in the table [which they mightn't be].  */
 
 static void
-build_insn_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_insn_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   const CGEN_IBASE *ib = & iq2000_cgen_insn_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
 
   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
   for (i = 0; i < MAX_INSNS; ++i)
@@ -1984,8 +1975,7 @@ build_insn_table (cd)
 /* Subroutine of iq2000_cgen_cpu_open to rebuild the tables.  */
 
 static void
-iq2000_cgen_rebuild_tables (cd)
-     CGEN_CPU_TABLE *cd;
+iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
   unsigned int isas = cd->isas;
@@ -1997,7 +1987,7 @@ iq2000_cgen_rebuild_tables (cd)
 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
   cd->default_insn_bitsize = UNSET;
   cd->base_insn_bitsize = UNSET;
-  cd->min_insn_bitsize = 65535; /* some ridiculously big number */
+  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
     if (((1 << i) & isas) != 0)
@@ -2009,7 +1999,7 @@ iq2000_cgen_rebuild_tables (cd)
 	if (cd->default_insn_bitsize == UNSET)
 	  cd->default_insn_bitsize = isa->default_insn_bitsize;
 	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -2018,7 +2008,7 @@ iq2000_cgen_rebuild_tables (cd)
 	if (cd->base_insn_bitsize == UNSET)
 	  cd->base_insn_bitsize = isa->base_insn_bitsize;
 	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -2130,12 +2120,12 @@ iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     }
   va_end (ap);
 
-  /* mach unspecified means "all" */
+  /* Mach unspecified means "all".  */
   if (machs == 0)
     machs = (1 << MAX_MACHS) - 1;
-  /* base mach is always selected */
+  /* Base mach is always selected.  */
   machs |= 1;
-  /* isa unspecified means "all" */
+  /* ISA unspecified means "all".  */
   if (isas == 0)
     isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
@@ -2168,9 +2158,7 @@ iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
    MACH_NAME is the bfd name of the mach.  */
 
 CGEN_CPU_DESC
-iq2000_cgen_cpu_open_1 (mach_name, endian)
-     const char *mach_name;
-     enum cgen_endian endian;
+iq2000_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
 {
   return iq2000_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
 			       CGEN_CPU_OPEN_ENDIAN, endian,
@@ -2183,8 +2171,7 @@ iq2000_cgen_cpu_open_1 (mach_name, endian)
    place as some simulator ports use this but they don't use libopcodes.  */
 
 void
-iq2000_cgen_cpu_close (cd)
-     CGEN_CPU_DESC cd;
+iq2000_cgen_cpu_close (CGEN_CPU_DESC cd)
 {
   unsigned int i;
   const CGEN_INSN *insns;
@@ -2193,23 +2180,17 @@ iq2000_cgen_cpu_close (cd)
     {
       insns = cd->macro_insn_table.init_entries;
       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX ((insns)))
-	    regfree (CGEN_INSN_RX (insns));
-	}
+	if (CGEN_INSN_RX ((insns)))
+	  regfree (CGEN_INSN_RX (insns));
     }
 
   if (cd->insn_table.init_entries)
     {
       insns = cd->insn_table.init_entries;
       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX (insns))
-	    regfree (CGEN_INSN_RX (insns));
-	}
-    }
-
-  
+	if (CGEN_INSN_RX (insns))
+	  regfree (CGEN_INSN_RX (insns));
+    }  
 
   if (cd->macro_insn_table.init_entries)
     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
diff --git a/opcodes/iq2000-dis.c b/opcodes/iq2000-dis.c
index b6ac507..02f535e 100644
--- a/opcodes/iq2000-dis.c
+++ b/opcodes/iq2000-dis.c
@@ -1,27 +1,27 @@
 /* Disassembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-dis.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-dis.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
-Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -56,12 +56,11 @@ static int read_insn
   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
    unsigned long *);
 
-/* -- disassembler routines inserted here */
+/* -- disassembler routines inserted here.  */
 
 
 void iq2000_cgen_print_operand
-  PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
-           void const *, bfd_vma, int));
+  (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
 
 /* Main entry point for printing operands.
    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@@ -79,16 +78,15 @@ void iq2000_cgen_print_operand
    the handlers.  */
 
 void
-iq2000_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     PTR xinfo;
-     CGEN_FIELDS *fields;
-     void const *attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     int length;
+iq2000_cgen_print_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   void * xinfo,
+			   CGEN_FIELDS *fields,
+			   void const *attrs ATTRIBUTE_UNUSED,
+			   bfd_vma pc,
+			   int length)
 {
- disassemble_info *info = (disassemble_info *) xinfo;
+  disassemble_info *info = (disassemble_info *) xinfo;
 
   switch (opindex)
     {
@@ -201,8 +199,7 @@ cgen_print_fn * const iq2000_cgen_print_handlers[] =
 
 
 void
-iq2000_cgen_init_dis (cd)
-     CGEN_CPU_DESC cd;
+iq2000_cgen_init_dis (CGEN_CPU_DESC cd)
 {
   iq2000_cgen_init_opcode_table (cd);
   iq2000_cgen_init_ibld_table (cd);
@@ -254,7 +251,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 
   /* Print the operand as directed by the attributes.  */
   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
-    ; /* nothing to do */
+    ; /* Nothing to do.  */
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
     (*info->print_address_func) (value, info);
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@@ -336,6 +333,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
+
   if (status != 0)
     {
       (*info->memory_error_func) (status, pc, info);
@@ -440,13 +438,13 @@ print_insn (CGEN_CPU_DESC cd,
 	    length = CGEN_EXTRACT_FN (cd, insn)
 	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 
-	  /* length < 0 -> error */
+	  /* Length < 0 -> error.  */
 	  if (length < 0)
 	    return length;
 	  if (length > 0)
 	    {
 	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
-	      /* length is in bits, result is in bytes */
+	      /* Length is in bits, result is in bytes.  */
 	      return length / 8;
 	    }
 	}
@@ -496,7 +494,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
    Print one instruction from PC on INFO->STREAM.
    Return the size of the instruction (in bytes).  */
 
-typedef struct cpu_desc_list {
+typedef struct cpu_desc_list
+{
   struct cpu_desc_list *next;
   int isa;
   int mach;
@@ -581,7 +580,7 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
       if (!cd)
 	abort ();
 
-      /* save this away for future reference */
+      /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
       cl->isa = isa;
diff --git a/opcodes/iq2000-ibld.c b/opcodes/iq2000-ibld.c
index 66d8d38..9be3f0f 100644
--- a/opcodes/iq2000-ibld.c
+++ b/opcodes/iq2000-ibld.c
@@ -1,25 +1,26 @@
 /* Instruction building/extraction support for iq2000. -*- C -*-
 
-THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
-- the resultant file is machine generated, cgen-ibld.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+   - the resultant file is machine generated, cgen-ibld.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #include "opintl.h"
 #include "safe-ctype.h"
 
-#undef min
+#undef  min
 #define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
+#undef  max
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 /* Used by the ifield rtx function.  */
@@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
   if (length == 0)
     return NULL;
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
 
 #if CGEN_INT_INSN_P
 /* Cover function to store an insn value into an integral insn.  Must go here
- because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
+   because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
       int shift = insn_length - length;
       /* Written this way to avoid undefined behaviour.  */
       CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
       *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
     }
 }
@@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
 {
   unsigned long x;
   int shift;
-#if 0
-  int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
-#endif
+
   x = cgen_get_insn_value (cd, bufp, word_length);
 
   if (CGEN_INSN_LSB0_P)
@@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
       return 1;
     }
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
   return CGEN_INSN_BITSIZE (insn);
 }
 
-/* machine generated code added here */
+/* Machine generated code added here.  */
 
 const char * iq2000_cgen_insert_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 
 /* Main entry point for operand insertion.
 
@@ -559,12 +547,11 @@ const char * iq2000_cgen_insert_operand
    resolved during parsing.  */
 
 const char *
-iq2000_cgen_insert_operand (cd, opindex, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+iq2000_cgen_insert_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     CGEN_INSN_BYTES_PTR buffer,
+			     bfd_vma pc ATTRIBUTE_UNUSED)
 {
   const char * errmsg = NULL;
   unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@@ -721,8 +708,7 @@ iq2000_cgen_insert_operand (cd, opindex, fields, buffer, pc)
 }
 
 int iq2000_cgen_extract_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-           CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 
 /* Main entry point for operand extraction.
    The result is <= 0 for error, >0 for success.
@@ -740,13 +726,12 @@ int iq2000_cgen_extract_operand
    the handlers.  */
 
 int
-iq2000_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS * fields;
-     bfd_vma pc;
+iq2000_cgen_extract_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_EXTRACT_INFO *ex_info,
+			     CGEN_INSN_INT insn_value,
+			     CGEN_FIELDS * fields,
+			     bfd_vma pc)
 {
   /* Assume success (for those operands that are nops).  */
   int length = 1;
@@ -907,10 +892,8 @@ cgen_extract_fn * const iq2000_cgen_extract_handlers[] =
   extract_insn_normal,
 };
 
-int iq2000_cgen_get_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
-bfd_vma iq2000_cgen_get_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+int iq2000_cgen_get_int_operand     (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+bfd_vma iq2000_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
 
 /* Getting values from cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they return.
@@ -918,10 +901,9 @@ bfd_vma iq2000_cgen_get_vma_operand
    not appropriate.  */
 
 int
-iq2000_cgen_get_int_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+iq2000_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   int value;
 
@@ -1032,10 +1014,9 @@ iq2000_cgen_get_int_operand (cd, opindex, fields)
 }
 
 bfd_vma
-iq2000_cgen_get_vma_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+iq2000_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   bfd_vma value;
 
@@ -1145,10 +1126,8 @@ iq2000_cgen_get_vma_operand (cd, opindex, fields)
   return value;
 }
 
-void iq2000_cgen_set_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
-void iq2000_cgen_set_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+void iq2000_cgen_set_int_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
+void iq2000_cgen_set_vma_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
 
 /* Stuffing values in cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they accept.
@@ -1156,11 +1135,10 @@ void iq2000_cgen_set_vma_operand
    not appropriate.  */
 
 void
-iq2000_cgen_set_int_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     int value;
+iq2000_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     int value)
 {
   switch (opindex)
     {
@@ -1267,11 +1245,10 @@ iq2000_cgen_set_int_operand (cd, opindex, fields, value)
 }
 
 void
-iq2000_cgen_set_vma_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     bfd_vma value;
+iq2000_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     bfd_vma value)
 {
   switch (opindex)
     {
@@ -1380,8 +1357,7 @@ iq2000_cgen_set_vma_operand (cd, opindex, fields, value)
 /* Function to call before using the instruction builder tables.  */
 
 void
-iq2000_cgen_init_ibld_table (cd)
-     CGEN_CPU_DESC cd;
+iq2000_cgen_init_ibld_table (CGEN_CPU_DESC cd)
 {
   cd->insert_handlers = & iq2000_cgen_insert_handlers[0];
   cd->extract_handlers = & iq2000_cgen_extract_handlers[0];
diff --git a/opcodes/iq2000-opc.c b/opcodes/iq2000-opc.c
index 2fc68f1..2ea3bf8 100644
--- a/opcodes/iq2000-opc.c
+++ b/opcodes/iq2000-opc.c
@@ -33,10 +33,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* The hash functions are recorded here to help keep assembler code out of
    the disassembler and vice versa.  */
 
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static int asm_hash_insn_p        (const CGEN_INSN *);
+static unsigned int asm_hash_insn (const char *);
+static int dis_hash_insn_p        (const CGEN_INSN *);
+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
 
 /* Instruction formats.  */
 
@@ -3425,14 +3425,10 @@ dis_hash_insn (buf, value)
   return CGEN_DIS_HASH (buf, value);
 }
 
-static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
-
 /* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
 
 static void
-set_fields_bitsize (fields, size)
-     CGEN_FIELDS *fields;
-     int size;
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
 {
   CGEN_FIELDS_BITSIZE (fields) = size;
 }
@@ -3441,15 +3437,15 @@ set_fields_bitsize (fields, size)
    This plugs the opcode entries and macro instructions into the cpu table.  */
 
 void
-iq2000_cgen_init_opcode_table (cd)
-     CGEN_CPU_DESC cd;
+iq2000_cgen_init_opcode_table (CGEN_CPU_DESC cd)
 {
   int i;
   int num_macros = (sizeof (iq2000_cgen_macro_insn_table) /
 		    sizeof (iq2000_cgen_macro_insn_table[0]));
   const CGEN_IBASE *ib = & iq2000_cgen_macro_insn_table[0];
   const CGEN_OPCODE *oc = & iq2000_cgen_macro_insn_opcode_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
+
   memset (insns, 0, num_macros * sizeof (CGEN_INSN));
   for (i = 0; i < num_macros; ++i)
     {
diff --git a/opcodes/iq2000-opc.h b/opcodes/iq2000-opc.h
index 76307e3..af18935 100644
--- a/opcodes/iq2000-opc.h
+++ b/opcodes/iq2000-opc.h
@@ -39,7 +39,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
    instructions have same mnemonics but different functionality. */
 #define CGEN_VALIDATE_INSN_SUPPORTED
 
-extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn);
+extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
 
 /* -- asm.c */
 /* Enum declaration for iq2000 instruction types.  */
diff --git a/opcodes/m10200-dis.c b/opcodes/m10200-dis.c
index 229cee9..92bc2fd 100644
--- a/opcodes/m10200-dis.c
+++ b/opcodes/m10200-dis.c
@@ -1,20 +1,20 @@
 /* Disassemble MN10200 instructions.
-   Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 2000, 2005 Free Software Foundation, Inc.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <stdio.h>
 
@@ -23,14 +23,141 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 #include "dis-asm.h"
 #include "opintl.h"
 
-static void disassemble PARAMS ((bfd_vma, struct disassemble_info *,
-				 unsigned long insn, unsigned long,
-				 unsigned int));
+static void
+disassemble (bfd_vma memaddr,
+	     struct disassemble_info *info,
+	     unsigned long insn,
+	     unsigned long extension,
+	     unsigned int size)
+{
+  struct mn10200_opcode *op = (struct mn10200_opcode *)mn10200_opcodes;
+  const struct mn10200_operand *operand;
+  int match = 0;
+
+  /* Find the opcode.  */
+  while (op->name)
+    {
+      int mysize, extra_shift;
+
+      if (op->format == FMT_1)
+	mysize = 1;
+      else if (op->format == FMT_2
+	       || op->format == FMT_4)
+	mysize = 2;
+      else if (op->format == FMT_3
+	       || op->format == FMT_5)
+	mysize = 3;
+      else if (op->format == FMT_6)
+	mysize = 4;
+      else if (op->format == FMT_7)
+	mysize = 5;
+      else
+	abort ();
+	
+      if (op->format == FMT_2 || op->format == FMT_5)
+	extra_shift = 8;
+      else if (op->format == FMT_3
+	       || op->format == FMT_6
+	       || op->format == FMT_7)
+	extra_shift = 16;
+      else
+	extra_shift = 0;
+
+      if ((op->mask & insn) == op->opcode
+	  && size == (unsigned int) mysize)
+	{
+	  const unsigned char *opindex_ptr;
+	  unsigned int nocomma;
+	  int paren = 0;
+	  
+	  match = 1;
+	  (*info->fprintf_func) (info->stream, "%s\t", op->name);
+
+	  /* Now print the operands.  */
+	  for (opindex_ptr = op->operands, nocomma = 1;
+	       *opindex_ptr != 0;
+	       opindex_ptr++)
+	    {
+	      unsigned long value;
+
+	      operand = &mn10200_operands[*opindex_ptr];
+
+	      if ((operand->flags & MN10200_OPERAND_EXTENDED) != 0)
+		{
+		  value = (insn & 0xffff) << 8;
+		  value |= extension;
+		}
+	      else
+		{
+		  value = ((insn >> (operand->shift))
+			   & ((1L << operand->bits) - 1L));
+		}
+
+	      if ((operand->flags & MN10200_OPERAND_SIGNED) != 0)
+		value = ((long)(value << (32 - operand->bits))
+			  >> (32 - operand->bits));
+
+	      if (!nocomma
+		  && (!paren
+		      || ((operand->flags & MN10200_OPERAND_PAREN) == 0)))
+		(*info->fprintf_func) (info->stream, ",");
+
+	      nocomma = 0;
+		
+	      if ((operand->flags & MN10200_OPERAND_DREG) != 0)
+		{
+		  value = ((insn >> (operand->shift + extra_shift))
+			   & ((1 << operand->bits) - 1));
+		  (*info->fprintf_func) (info->stream, "d%d", value);
+		}
+
+	      else if ((operand->flags & MN10200_OPERAND_AREG) != 0)
+		{
+		  value = ((insn >> (operand->shift + extra_shift))
+			   & ((1 << operand->bits) - 1));
+		  (*info->fprintf_func) (info->stream, "a%d", value);
+		}
+
+	      else if ((operand->flags & MN10200_OPERAND_PSW) != 0)
+		(*info->fprintf_func) (info->stream, "psw");
+
+	      else if ((operand->flags & MN10200_OPERAND_MDR) != 0)
+		(*info->fprintf_func) (info->stream, "mdr");
+
+	      else if ((operand->flags & MN10200_OPERAND_PAREN) != 0)
+		{
+		  if (paren)
+		    (*info->fprintf_func) (info->stream, ")");
+		  else
+		    {
+		      (*info->fprintf_func) (info->stream, "(");
+		      nocomma = 1;
+		    }
+		  paren = !paren;
+		}
+
+	      else if ((operand->flags & MN10200_OPERAND_PCREL) != 0)
+		(*info->print_address_func)
+		  ((value + memaddr + mysize) & 0xffffff, info);
+
+	      else if ((operand->flags & MN10200_OPERAND_MEMADDR) != 0)
+		(*info->print_address_func) (value, info);
+
+	      else 
+		(*info->fprintf_func) (info->stream, "%ld", value);
+	    }
+	  /* All done. */
+	  break;
+	}
+      op++;
+    }
+
+  if (!match)
+    (*info->fprintf_func) (info->stream, _("unknown\t0x%04lx"), insn);
+}
 
 int 
-print_insn_mn10200 (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_mn10200 (bfd_vma memaddr, struct disassemble_info *info)
 {
   int status;
   bfd_byte buffer[4];
@@ -204,138 +331,3 @@ print_insn_mn10200 (memaddr, info)
 
   return consume;
 }
-
-static void
-disassemble (memaddr, info, insn, extension, size)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
-     unsigned long insn;
-     unsigned long extension;
-     unsigned int size;
-{
-  struct mn10200_opcode *op = (struct mn10200_opcode *)mn10200_opcodes;
-  const struct mn10200_operand *operand;
-  int match = 0;
-
-  /* Find the opcode.  */
-  while (op->name)
-    {
-      int mysize, extra_shift;
-
-      if (op->format == FMT_1)
-	mysize = 1;
-      else if (op->format == FMT_2
-	       || op->format == FMT_4)
-	mysize = 2;
-      else if (op->format == FMT_3
-	       || op->format == FMT_5)
-	mysize = 3;
-      else if (op->format == FMT_6)
-	mysize = 4;
-      else if (op->format == FMT_7)
-	mysize = 5;
-      else
-	abort ();
-	
-      if (op->format == FMT_2 || op->format == FMT_5)
-	extra_shift = 8;
-      else if (op->format == FMT_3
-	       || op->format == FMT_6
-	       || op->format == FMT_7)
-	extra_shift = 16;
-      else
-	extra_shift = 0;
-
-      if ((op->mask & insn) == op->opcode
-	  && size == (unsigned int) mysize)
-	{
-	  const unsigned char *opindex_ptr;
-	  unsigned int nocomma;
-	  int paren = 0;
-	  
-	  match = 1;
-	  (*info->fprintf_func) (info->stream, "%s\t", op->name);
-
-	  /* Now print the operands.  */
-	  for (opindex_ptr = op->operands, nocomma = 1;
-	       *opindex_ptr != 0;
-	       opindex_ptr++)
-	    {
-	      unsigned long value;
-
-	      operand = &mn10200_operands[*opindex_ptr];
-
-	      if ((operand->flags & MN10200_OPERAND_EXTENDED) != 0)
-		{
-		  value = (insn & 0xffff) << 8;
-		  value |= extension;
-		}
-	      else
-		{
-		  value = ((insn >> (operand->shift))
-			   & ((1L << operand->bits) - 1L));
-		}
-
-	      if ((operand->flags & MN10200_OPERAND_SIGNED) != 0)
-		value = ((long)(value << (32 - operand->bits))
-			  >> (32 - operand->bits));
-
-	      if (!nocomma
-		  && (!paren
-		      || ((operand->flags & MN10200_OPERAND_PAREN) == 0)))
-		(*info->fprintf_func) (info->stream, ",");
-
-	      nocomma = 0;
-		
-	      if ((operand->flags & MN10200_OPERAND_DREG) != 0)
-		{
-		  value = ((insn >> (operand->shift + extra_shift))
-			   & ((1 << operand->bits) - 1));
-		  (*info->fprintf_func) (info->stream, "d%d", value);
-		}
-
-	      else if ((operand->flags & MN10200_OPERAND_AREG) != 0)
-		{
-		  value = ((insn >> (operand->shift + extra_shift))
-			   & ((1 << operand->bits) - 1));
-		  (*info->fprintf_func) (info->stream, "a%d", value);
-		}
-
-	      else if ((operand->flags & MN10200_OPERAND_PSW) != 0)
-		(*info->fprintf_func) (info->stream, "psw");
-
-	      else if ((operand->flags & MN10200_OPERAND_MDR) != 0)
-		(*info->fprintf_func) (info->stream, "mdr");
-
-	      else if ((operand->flags & MN10200_OPERAND_PAREN) != 0)
-		{
-		  if (paren)
-		    (*info->fprintf_func) (info->stream, ")");
-		  else
-		    {
-		      (*info->fprintf_func) (info->stream, "(");
-		      nocomma = 1;
-		    }
-		  paren = !paren;
-		}
-
-	      else if ((operand->flags & MN10200_OPERAND_PCREL) != 0)
-		(*info->print_address_func) ((value + memaddr + mysize) & 0xffffff, info);
-
-	      else if ((operand->flags & MN10200_OPERAND_MEMADDR) != 0)
-		(*info->print_address_func) (value, info);
-
-	      else 
-		(*info->fprintf_func) (info->stream, "%ld", value);
-	    }
-	  /* All done. */
-	  break;
-	}
-      op++;
-    }
-
-  if (!match)
-    {
-	(*info->fprintf_func) (info->stream, _("unknown\t0x%04lx"), insn);
-    }
-}
diff --git a/opcodes/m10300-dis.c b/opcodes/m10300-dis.c
index acd5e4c..158490e 100644
--- a/opcodes/m10300-dis.c
+++ b/opcodes/m10300-dis.c
@@ -1,21 +1,21 @@
 /* Disassemble MN10300 instructions.
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2005
    Free Software Foundation, Inc.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <stdio.h>
 
@@ -24,202 +24,17 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 #include "dis-asm.h"
 #include "opintl.h"
 
-static void disassemble PARAMS ((bfd_vma, struct disassemble_info *,
-				 unsigned long insn, unsigned int));
-
 #define HAVE_AM33_2 (info->mach == AM33_2)
-#define HAVE_AM33 (info->mach == AM33 || HAVE_AM33_2)
-#define HAVE_AM30 (info->mach == AM30)
-
-int
-print_insn_mn10300 (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
-{
-  int status;
-  bfd_byte buffer[4];
-  unsigned long insn;
-  unsigned int consume;
-
-  /* First figure out how big the opcode is.  */
-  status = (*info->read_memory_func) (memaddr, buffer, 1, info);
-  if (status != 0)
-    {
-      (*info->memory_error_func) (status, memaddr, info);
-      return -1;
-    }
-  insn = *(unsigned char *) buffer;
-
-  /* These are one byte insns.  */
-  if ((insn & 0xf3) == 0x00
-      || (insn & 0xf0) == 0x10
-      || (insn & 0xfc) == 0x3c
-      || (insn & 0xf3) == 0x41
-      || (insn & 0xf3) == 0x40
-      || (insn & 0xfc) == 0x50
-      || (insn & 0xfc) == 0x54
-      || (insn & 0xf0) == 0x60
-      || (insn & 0xf0) == 0x70
-      || ((insn & 0xf0) == 0x80
-	  && (insn & 0x0c) >> 2 != (insn & 0x03))
-      || ((insn & 0xf0) == 0x90
-	  && (insn & 0x0c) >> 2 != (insn & 0x03))
-      || ((insn & 0xf0) == 0xa0
-	  && (insn & 0x0c) >> 2 != (insn & 0x03))
-      || ((insn & 0xf0) == 0xb0
-	  && (insn & 0x0c) >> 2 != (insn & 0x03))
-      || (insn & 0xff) == 0xcb
-      || (insn & 0xfc) == 0xd0
-      || (insn & 0xfc) == 0xd4
-      || (insn & 0xfc) == 0xd8
-      || (insn & 0xf0) == 0xe0
-      || (insn & 0xff) == 0xff)
-    {
-      consume = 1;
-    }
-
-  /* These are two byte insns.  */
-  else if ((insn & 0xf0) == 0x80
-	   || (insn & 0xf0) == 0x90
-	   || (insn & 0xf0) == 0xa0
-	   || (insn & 0xf0) == 0xb0
-	   || (insn & 0xfc) == 0x20
-	   || (insn & 0xfc) == 0x28
-	   || (insn & 0xf3) == 0x43
-	   || (insn & 0xf3) == 0x42
-	   || (insn & 0xfc) == 0x58
-	   || (insn & 0xfc) == 0x5c
-	   || ((insn & 0xf0) == 0xc0
-	       && (insn & 0xff) != 0xcb
-	       && (insn & 0xff) != 0xcc
-	       && (insn & 0xff) != 0xcd)
-	   || (insn & 0xff) == 0xf0
-	   || (insn & 0xff) == 0xf1
-	   || (insn & 0xff) == 0xf2
-	   || (insn & 0xff) == 0xf3
-	   || (insn & 0xff) == 0xf4
-	   || (insn & 0xff) == 0xf5
-	   || (insn & 0xff) == 0xf6)
-    {
-      status = (*info->read_memory_func) (memaddr, buffer, 2, info);
-      if (status != 0)
-	{
-	  (*info->memory_error_func) (status, memaddr, info);
-	  return -1;
-	}
-      insn = bfd_getb16 (buffer);
-      consume = 2;
-    }
-
-  /* These are three byte insns.  */
-  else if ((insn & 0xff) == 0xf8
-	   || (insn & 0xff) == 0xcc
-	   || (insn & 0xff) == 0xf9
-	   || (insn & 0xf3) == 0x01
-	   || (insn & 0xf3) == 0x02
-	   || (insn & 0xf3) == 0x03
-	   || (insn & 0xfc) == 0x24
-	   || (insn & 0xfc) == 0x2c
-	   || (insn & 0xfc) == 0x30
-	   || (insn & 0xfc) == 0x34
-	   || (insn & 0xfc) == 0x38
-	   || (insn & 0xff) == 0xde
-	   || (insn & 0xff) == 0xdf
-	   || (insn & 0xff) == 0xf9
-	   || (insn & 0xff) == 0xcc)
-    {
-      status = (*info->read_memory_func) (memaddr, buffer, 2, info);
-      if (status != 0)
-	{
-	  (*info->memory_error_func) (status, memaddr, info);
-	  return -1;
-	}
-      insn = bfd_getb16 (buffer);
-      insn <<= 8;
-      status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info);
-      if (status != 0)
-	{
-	  (*info->memory_error_func) (status, memaddr, info);
-	  return -1;
-	}
-      insn |= *(unsigned char *) buffer;
-      consume = 3;
-    }
-
-  /* These are four byte insns.  */
-  else if ((insn & 0xff) == 0xfa
-	   || (insn & 0xff) == 0xf7
-	   || (insn & 0xff) == 0xfb)
-    {
-      status = (*info->read_memory_func) (memaddr, buffer, 4, info);
-      if (status != 0)
-	{
-	  (*info->memory_error_func) (status, memaddr, info);
-	  return -1;
-	}
-      insn = bfd_getb32 (buffer);
-      consume = 4;
-    }
-
-  /* These are five byte insns.  */
-  else if ((insn & 0xff) == 0xcd
-	   || (insn & 0xff) == 0xdc)
-    {
-      status = (*info->read_memory_func) (memaddr, buffer, 4, info);
-      if (status != 0)
-	{
-	  (*info->memory_error_func) (status, memaddr, info);
-	  return -1;
-	}
-      insn = bfd_getb32 (buffer);
-      consume = 5;
-    }
-
-  /* These are six byte insns.  */
-  else if ((insn & 0xff) == 0xfd
-	   || (insn & 0xff) == 0xfc)
-    {
-      status = (*info->read_memory_func) (memaddr, buffer, 4, info);
-      if (status != 0)
-	{
-	  (*info->memory_error_func) (status, memaddr, info);
-	  return -1;
-	}
-
-      insn = bfd_getb32 (buffer);
-      consume = 6;
-    }
-
-  /* Else its a seven byte insns (in theory).  */
-  else
-    {
-      status = (*info->read_memory_func) (memaddr, buffer, 4, info);
-      if (status != 0)
-	{
-	  (*info->memory_error_func) (status, memaddr, info);
-	  return -1;
-	}
-
-      insn = bfd_getb32 (buffer);
-      consume = 7;
-      /* Handle the 5-byte extended instruction codes.  */
-      if ((insn & 0xfff80000) == 0xfe800000)
-	consume = 5;
-    }
-
-  disassemble (memaddr, info, insn, consume);
-
-  return consume;
-}
+#define HAVE_AM33   (info->mach == AM33 || HAVE_AM33_2)
+#define HAVE_AM30   (info->mach == AM30)
 
 static void
-disassemble (memaddr, info, insn, size)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
-     unsigned long insn;
-     unsigned int size;
+disassemble (bfd_vma memaddr,
+	     struct disassemble_info *info,
+	     unsigned long insn,
+	     unsigned int size)
 {
-  struct mn10300_opcode *op = (struct mn10300_opcode *)mn10300_opcodes;
+  struct mn10300_opcode *op = (struct mn10300_opcode *) mn10300_opcodes;
   const struct mn10300_operand *operand;
   bfd_byte buffer[4];
   unsigned long extension = 0;
@@ -282,21 +97,18 @@ disassemble (memaddr, info, insn, size)
 	    extra_shift = 0;
 
 	  if (size == 1 || size == 2)
-	    {
-	      extension = 0;
-	    }
+	    extension = 0;
+
 	  else if (size == 3
 		   && (op->format == FMT_D1
 		       || op->opcode == 0xdf0000
 		       || op->opcode == 0xde0000))
-	    {
-	      extension = 0;
-	    }
+	    extension = 0;
+
 	  else if (size == 3
 		   && op->format == FMT_D6)
-	    {
-	      extension = 0;
-	    }
+	    extension = 0;
+
 	  else if (size == 3)
 	    {
 	      insn &= 0xff0000;
@@ -314,15 +126,13 @@ disassemble (memaddr, info, insn, size)
 		   && (op->opcode == 0xfaf80000
 		       || op->opcode == 0xfaf00000
 		       || op->opcode == 0xfaf40000))
-	    {
-	      extension = 0;
-	    }
+	    extension = 0;
+
 	  else if (size == 4
 		   && (op->format == FMT_D7
 		       || op->format == FMT_D10))
-	    {
-	      extension = 0;
-	    }
+	    extension = 0;
+
 	  else if (size == 4)
 	    {
 	      insn &= 0xffff0000;
@@ -339,6 +149,7 @@ disassemble (memaddr, info, insn, size)
 	  else if (size == 5 && op->opcode == 0xdc000000)
 	    {
 	      unsigned long temp = 0;
+
 	      status = (*info->read_memory_func) (memaddr + 1, buffer, 4, info);
 	      if (status != 0)
 		{
@@ -373,6 +184,7 @@ disassemble (memaddr, info, insn, size)
 	  else if (size == 5)
 	    {
 	      unsigned long temp = 0;
+
 	      status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info);
 	      if (status != 0)
 		{
@@ -414,6 +226,7 @@ disassemble (memaddr, info, insn, size)
 	  else if (size == 6)
 	    {
 	      unsigned long temp = 0;
+
 	      status = (*info->read_memory_func) (memaddr + 2, buffer, 4, info);
 	      if (status != 0)
 		{
@@ -442,6 +255,7 @@ disassemble (memaddr, info, insn, size)
 	  else if (size == 7 && op->opcode == 0xdd000000)
 	    {
 	      unsigned long temp = 0;
+
 	      status = (*info->read_memory_func) (memaddr + 1, buffer, 4, info);
 	      if (status != 0)
 		{
@@ -465,6 +279,7 @@ disassemble (memaddr, info, insn, size)
 	  else if (size == 7)
 	    {
 	      unsigned long temp = 0;
+
 	      status = (*info->read_memory_func) (memaddr + 2, buffer, 4, info);
 	      if (status != 0)
 		{
@@ -506,6 +321,7 @@ disassemble (memaddr, info, insn, size)
 	      if ((operand->flags & MN10300_OPERAND_SPLIT) != 0)
 		{
 		  unsigned long temp;
+
 		  value = insn & ((1 << operand->bits) - 1);
 		  value <<= (32 - operand->bits);
 		  temp = extension >> operand->shift;
@@ -517,6 +333,7 @@ disassemble (memaddr, info, insn, size)
 	      else if ((operand->flags & MN10300_OPERAND_24BIT) != 0)
 		{
 		  unsigned long temp;
+
 		  value = insn & ((1 << operand->bits) - 1);
 		  value <<= (24 - operand->bits);
 		  temp = extension >> operand->shift;
@@ -572,15 +389,12 @@ disassemble (memaddr, info, insn, size)
 			   | ((insn >> shl_low) & mask_low));
 		}
 	      else if ((operand->flags & MN10300_OPERAND_EXTENDED) != 0)
-		{
-		  value = ((extension >> (operand->shift))
-			   & ((1 << operand->bits) - 1));
-		}
+		value = ((extension >> (operand->shift))
+			 & ((1 << operand->bits) - 1));
+
 	      else
-		{
-		  value = ((insn >> (operand->shift))
-			   & ((1 << operand->bits) - 1));
-		}
+		value = ((insn >> (operand->shift))
+			 & ((1 << operand->bits) - 1));
 
 	      if ((operand->flags & MN10300_OPERAND_SIGNED) != 0
 		  /* These are properly extended by the code above.  */
@@ -762,8 +576,185 @@ disassemble (memaddr, info, insn, size)
     }
 
   if (!match)
+    /* xgettext:c-format */
+    (*info->fprintf_func) (info->stream, _("unknown\t0x%04x"), insn);
+}
+
+int
+print_insn_mn10300 (bfd_vma memaddr, struct disassemble_info *info)
+{
+  int status;
+  bfd_byte buffer[4];
+  unsigned long insn;
+  unsigned int consume;
+
+  /* First figure out how big the opcode is.  */
+  status = (*info->read_memory_func) (memaddr, buffer, 1, info);
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, memaddr, info);
+      return -1;
+    }
+  insn = *(unsigned char *) buffer;
+
+  /* These are one byte insns.  */
+  if ((insn & 0xf3) == 0x00
+      || (insn & 0xf0) == 0x10
+      || (insn & 0xfc) == 0x3c
+      || (insn & 0xf3) == 0x41
+      || (insn & 0xf3) == 0x40
+      || (insn & 0xfc) == 0x50
+      || (insn & 0xfc) == 0x54
+      || (insn & 0xf0) == 0x60
+      || (insn & 0xf0) == 0x70
+      || ((insn & 0xf0) == 0x80
+	  && (insn & 0x0c) >> 2 != (insn & 0x03))
+      || ((insn & 0xf0) == 0x90
+	  && (insn & 0x0c) >> 2 != (insn & 0x03))
+      || ((insn & 0xf0) == 0xa0
+	  && (insn & 0x0c) >> 2 != (insn & 0x03))
+      || ((insn & 0xf0) == 0xb0
+	  && (insn & 0x0c) >> 2 != (insn & 0x03))
+      || (insn & 0xff) == 0xcb
+      || (insn & 0xfc) == 0xd0
+      || (insn & 0xfc) == 0xd4
+      || (insn & 0xfc) == 0xd8
+      || (insn & 0xf0) == 0xe0
+      || (insn & 0xff) == 0xff)
     {
-      /* xgettext:c-format */
-      (*info->fprintf_func) (info->stream, _("unknown\t0x%04x"), insn);
+      consume = 1;
     }
+
+  /* These are two byte insns.  */
+  else if ((insn & 0xf0) == 0x80
+	   || (insn & 0xf0) == 0x90
+	   || (insn & 0xf0) == 0xa0
+	   || (insn & 0xf0) == 0xb0
+	   || (insn & 0xfc) == 0x20
+	   || (insn & 0xfc) == 0x28
+	   || (insn & 0xf3) == 0x43
+	   || (insn & 0xf3) == 0x42
+	   || (insn & 0xfc) == 0x58
+	   || (insn & 0xfc) == 0x5c
+	   || ((insn & 0xf0) == 0xc0
+	       && (insn & 0xff) != 0xcb
+	       && (insn & 0xff) != 0xcc
+	       && (insn & 0xff) != 0xcd)
+	   || (insn & 0xff) == 0xf0
+	   || (insn & 0xff) == 0xf1
+	   || (insn & 0xff) == 0xf2
+	   || (insn & 0xff) == 0xf3
+	   || (insn & 0xff) == 0xf4
+	   || (insn & 0xff) == 0xf5
+	   || (insn & 0xff) == 0xf6)
+    {
+      status = (*info->read_memory_func) (memaddr, buffer, 2, info);
+      if (status != 0)
+	{
+	  (*info->memory_error_func) (status, memaddr, info);
+	  return -1;
+	}
+      insn = bfd_getb16 (buffer);
+      consume = 2;
+    }
+
+  /* These are three byte insns.  */
+  else if ((insn & 0xff) == 0xf8
+	   || (insn & 0xff) == 0xcc
+	   || (insn & 0xff) == 0xf9
+	   || (insn & 0xf3) == 0x01
+	   || (insn & 0xf3) == 0x02
+	   || (insn & 0xf3) == 0x03
+	   || (insn & 0xfc) == 0x24
+	   || (insn & 0xfc) == 0x2c
+	   || (insn & 0xfc) == 0x30
+	   || (insn & 0xfc) == 0x34
+	   || (insn & 0xfc) == 0x38
+	   || (insn & 0xff) == 0xde
+	   || (insn & 0xff) == 0xdf
+	   || (insn & 0xff) == 0xf9
+	   || (insn & 0xff) == 0xcc)
+    {
+      status = (*info->read_memory_func) (memaddr, buffer, 2, info);
+      if (status != 0)
+	{
+	  (*info->memory_error_func) (status, memaddr, info);
+	  return -1;
+	}
+      insn = bfd_getb16 (buffer);
+      insn <<= 8;
+      status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info);
+      if (status != 0)
+	{
+	  (*info->memory_error_func) (status, memaddr, info);
+	  return -1;
+	}
+      insn |= *(unsigned char *) buffer;
+      consume = 3;
+    }
+
+  /* These are four byte insns.  */
+  else if ((insn & 0xff) == 0xfa
+	   || (insn & 0xff) == 0xf7
+	   || (insn & 0xff) == 0xfb)
+    {
+      status = (*info->read_memory_func) (memaddr, buffer, 4, info);
+      if (status != 0)
+	{
+	  (*info->memory_error_func) (status, memaddr, info);
+	  return -1;
+	}
+      insn = bfd_getb32 (buffer);
+      consume = 4;
+    }
+
+  /* These are five byte insns.  */
+  else if ((insn & 0xff) == 0xcd
+	   || (insn & 0xff) == 0xdc)
+    {
+      status = (*info->read_memory_func) (memaddr, buffer, 4, info);
+      if (status != 0)
+	{
+	  (*info->memory_error_func) (status, memaddr, info);
+	  return -1;
+	}
+      insn = bfd_getb32 (buffer);
+      consume = 5;
+    }
+
+  /* These are six byte insns.  */
+  else if ((insn & 0xff) == 0xfd
+	   || (insn & 0xff) == 0xfc)
+    {
+      status = (*info->read_memory_func) (memaddr, buffer, 4, info);
+      if (status != 0)
+	{
+	  (*info->memory_error_func) (status, memaddr, info);
+	  return -1;
+	}
+
+      insn = bfd_getb32 (buffer);
+      consume = 6;
+    }
+
+  /* Else its a seven byte insns (in theory).  */
+  else
+    {
+      status = (*info->read_memory_func) (memaddr, buffer, 4, info);
+      if (status != 0)
+	{
+	  (*info->memory_error_func) (status, memaddr, info);
+	  return -1;
+	}
+
+      insn = bfd_getb32 (buffer);
+      consume = 7;
+      /* Handle the 5-byte extended instruction codes.  */
+      if ((insn & 0xfff80000) == 0xfe800000)
+	consume = 5;
+    }
+
+  disassemble (memaddr, info, insn, consume);
+
+  return consume;
 }
diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c
index ea777bc..acb0762 100644
--- a/opcodes/m32r-asm.c
+++ b/opcodes/m32r-asm.c
@@ -1,26 +1,27 @@
 /* Assembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-asm.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-asm.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -48,23 +49,16 @@ static const char * parse_insn_normal
 /* -- assembler routines inserted here.  */
 
 /* -- asm.c */
-static const char * parse_hash
-  PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
-static const char * parse_hi16
-  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_slo16
-  PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
-static const char * parse_ulo16
-  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+
+static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
 
 /* Handle '#' prefixes (i.e. skip over them).  */
 
 static const char *
-parse_hash (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     const char **strp;
-     int opindex ATTRIBUTE_UNUSED;
-     long *valuep ATTRIBUTE_UNUSED;
+parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    const char **strp,
+	    int opindex ATTRIBUTE_UNUSED,
+	    long *valuep ATTRIBUTE_UNUSED)
 {
   if (**strp == '#')
     ++*strp;
@@ -74,11 +68,10 @@ parse_hash (cd, strp, opindex, valuep)
 /* Handle shigh(), high().  */
 
 static const char *
-parse_hi16 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_hi16 (CGEN_CPU_DESC cd,
+	    const char **strp,
+	    int opindex,
+	    unsigned long *valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
@@ -91,9 +84,9 @@ parse_hi16 (cd, strp, opindex, valuep)
     {
       *strp += 5;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO,
-				   &result_type, &value);
+				   & result_type, & value);
       if (**strp != ')')
-	return "missing `)'";
+	return MISSING_CLOSING_PARENTHESIS;
       ++*strp;
       if (errmsg == NULL
   	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@@ -105,9 +98,9 @@ parse_hi16 (cd, strp, opindex, valuep)
     {
       *strp += 6;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO,
- 				   &result_type, &value);
+ 				   & result_type, & value);
       if (**strp != ')')
-	return "missing `)'";
+	return MISSING_CLOSING_PARENTHESIS;
       ++*strp;
       if (errmsg == NULL
 	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@@ -127,11 +120,7 @@ parse_hi16 (cd, strp, opindex, valuep)
    handles the case where low() isn't present.  */
 
 static const char *
-parse_slo16 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     long *valuep;
+parse_slo16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
@@ -144,9 +133,9 @@ parse_slo16 (cd, strp, opindex, valuep)
     {
       *strp += 4;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
-				   &result_type, &value);
+				   & result_type, & value);
       if (**strp != ')')
-	return "missing `)'";
+	return MISSING_CLOSING_PARENTHESIS;
       ++*strp;
       if (errmsg == NULL
 	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@@ -163,9 +152,9 @@ parse_slo16 (cd, strp, opindex, valuep)
     {
       *strp += 4;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16,
-				   NULL, &value);
+				   NULL, & value);
       if (**strp != ')')
-	return "missing `)'";
+	return MISSING_CLOSING_PARENTHESIS;
       ++*strp;
       *valuep = value;
       return errmsg;
@@ -179,11 +168,10 @@ parse_slo16 (cd, strp, opindex, valuep)
    handles the case where low() isn't present.  */
 
 static const char *
-parse_ulo16 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_ulo16 (CGEN_CPU_DESC cd,
+	     const char **strp,
+	     int opindex,
+	     unsigned long *valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
@@ -196,9 +184,9 @@ parse_ulo16 (cd, strp, opindex, valuep)
     {
       *strp += 4;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
-				   &result_type, &value);
+				   & result_type, & value);
       if (**strp != ')')
-	return "missing `)'";
+	return MISSING_CLOSING_PARENTHESIS;
       ++*strp;
       if (errmsg == NULL
 	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@@ -213,7 +201,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
 /* -- */
 
 const char * m32r_cgen_parse_operand
-  PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
 
 /* Main entry point for operand parsing.
 
@@ -229,11 +217,10 @@ const char * m32r_cgen_parse_operand
    the handlers.  */
 
 const char *
-m32r_cgen_parse_operand (cd, opindex, strp, fields)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     const char ** strp;
-     CGEN_FIELDS * fields;
+m32r_cgen_parse_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   const char ** strp,
+			   CGEN_FIELDS * fields)
 {
   const char * errmsg = NULL;
   /* Used by scalar operands that still need to be parsed.  */
@@ -348,8 +335,7 @@ cgen_parse_fn * const m32r_cgen_parse_handlers[] =
 };
 
 void
-m32r_cgen_init_asm (cd)
-     CGEN_CPU_DESC cd;
+m32r_cgen_init_asm (CGEN_CPU_DESC cd)
 {
   m32r_cgen_init_opcode_table (cd);
   m32r_cgen_init_ibld_table (cd);
@@ -732,30 +718,3 @@ m32r_cgen_assemble_insn (CGEN_CPU_DESC cd,
     return NULL;
   }
 }
-
-#if 0 /* This calls back to GAS which we can't do without care.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   This lets GAS parse registers for us.
-   ??? Interesting idea but not currently used.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   FIXME: Not currently used.  */
-
-void
-m32r_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
-{
-  CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
-  const CGEN_KEYWORD_ENTRY * ke;
-
-  while ((ke = cgen_keyword_search_next (& search)) != NULL)
-    {
-#if 0 /* Unnecessary, should be done in the search routine.  */
-      if (! m32r_cgen_opval_supported (ke))
-	continue;
-#endif
-      cgen_asm_record_register (cd, ke->name, ke->value);
-    }
-}
-
-#endif /* 0 */
diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c
index e0d7b1f..3b8cb56 100644
--- a/opcodes/m32r-desc.c
+++ b/opcodes/m32r-desc.c
@@ -1209,27 +1209,23 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 #undef A
 
 /* Initialize anything needed to be done once, before any cpu_open call.  */
-static void init_tables PARAMS ((void));
 
 static void
-init_tables ()
+init_tables (void)
 {
 }
 
-static const CGEN_MACH * lookup_mach_via_bfd_name
-  PARAMS ((const CGEN_MACH *, const char *));
-static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
-static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
+static void build_hw_table      (CGEN_CPU_TABLE *);
+static void build_ifield_table  (CGEN_CPU_TABLE *);
+static void build_operand_table (CGEN_CPU_TABLE *);
+static void build_insn_table    (CGEN_CPU_TABLE *);
+static void m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *);
 
 /* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name.  */
 
 static const CGEN_MACH *
-lookup_mach_via_bfd_name (table, name)
-     const CGEN_MACH *table;
-     const char *name;
+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
 {
   while (table->name)
     {
@@ -1243,8 +1239,7 @@ lookup_mach_via_bfd_name (table, name)
 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_hw_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_hw_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -1270,8 +1265,7 @@ build_hw_table (cd)
 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_ifield_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_ifield_table (CGEN_CPU_TABLE *cd)
 {
   cd->ifld_table = & m32r_cgen_ifld_table[0];
 }
@@ -1279,8 +1273,7 @@ build_ifield_table (cd)
 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_operand_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_operand_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -1288,8 +1281,7 @@ build_operand_table (cd)
   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
      However each entry is indexed by it's enum so there can be holes in
      the table.  */
-  const CGEN_OPERAND **selected =
-    (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
 
   cd->operand_table.init_entries = init;
   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@@ -1312,12 +1304,11 @@ build_operand_table (cd)
    operand elements to be in the table [which they mightn't be].  */
 
 static void
-build_insn_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_insn_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
 
   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
   for (i = 0; i < MAX_INSNS; ++i)
@@ -1330,8 +1321,7 @@ build_insn_table (cd)
 /* Subroutine of m32r_cgen_cpu_open to rebuild the tables.  */
 
 static void
-m32r_cgen_rebuild_tables (cd)
-     CGEN_CPU_TABLE *cd;
+m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
   unsigned int isas = cd->isas;
@@ -1343,7 +1333,7 @@ m32r_cgen_rebuild_tables (cd)
 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
   cd->default_insn_bitsize = UNSET;
   cd->base_insn_bitsize = UNSET;
-  cd->min_insn_bitsize = 65535; /* some ridiculously big number */
+  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
     if (((1 << i) & isas) != 0)
@@ -1355,7 +1345,7 @@ m32r_cgen_rebuild_tables (cd)
 	if (cd->default_insn_bitsize == UNSET)
 	  cd->default_insn_bitsize = isa->default_insn_bitsize;
 	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -1364,7 +1354,7 @@ m32r_cgen_rebuild_tables (cd)
 	if (cd->base_insn_bitsize == UNSET)
 	  cd->base_insn_bitsize = isa->base_insn_bitsize;
 	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -1476,12 +1466,12 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     }
   va_end (ap);
 
-  /* mach unspecified means "all" */
+  /* Mach unspecified means "all".  */
   if (machs == 0)
     machs = (1 << MAX_MACHS) - 1;
-  /* base mach is always selected */
+  /* Base mach is always selected.  */
   machs |= 1;
-  /* isa unspecified means "all" */
+  /* ISA unspecified means "all".  */
   if (isas == 0)
     isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
@@ -1514,9 +1504,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
    MACH_NAME is the bfd name of the mach.  */
 
 CGEN_CPU_DESC
-m32r_cgen_cpu_open_1 (mach_name, endian)
-     const char *mach_name;
-     enum cgen_endian endian;
+m32r_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
 {
   return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
 			       CGEN_CPU_OPEN_ENDIAN, endian,
@@ -1529,8 +1517,7 @@ m32r_cgen_cpu_open_1 (mach_name, endian)
    place as some simulator ports use this but they don't use libopcodes.  */
 
 void
-m32r_cgen_cpu_close (cd)
-     CGEN_CPU_DESC cd;
+m32r_cgen_cpu_close (CGEN_CPU_DESC cd)
 {
   unsigned int i;
   const CGEN_INSN *insns;
@@ -1539,23 +1526,17 @@ m32r_cgen_cpu_close (cd)
     {
       insns = cd->macro_insn_table.init_entries;
       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX ((insns)))
-	    regfree (CGEN_INSN_RX (insns));
-	}
+	if (CGEN_INSN_RX ((insns)))
+	  regfree (CGEN_INSN_RX (insns));
     }
 
   if (cd->insn_table.init_entries)
     {
       insns = cd->insn_table.init_entries;
       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX (insns))
-	    regfree (CGEN_INSN_RX (insns));
-	}
-    }
-
-  
+	if (CGEN_INSN_RX (insns))
+	  regfree (CGEN_INSN_RX (insns));
+    }  
 
   if (cd->macro_insn_table.init_entries)
     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c
index 1f1a8e9..fb65bfe 100644
--- a/opcodes/m32r-dis.c
+++ b/opcodes/m32r-dis.c
@@ -1,27 +1,27 @@
 /* Disassembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-dis.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-dis.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
-Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -56,12 +56,9 @@ static int read_insn
   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
    unsigned long *);
 
-/* -- disassembler routines inserted here */
+/* -- disassembler routines inserted here.  */
 
 /* -- dis.c */
-static void print_hash PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
-static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
-
 /* Immediate values are prefixed with '#'.  */
 
 #define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length)	\
@@ -75,15 +72,15 @@ static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
 /* Handle '#' prefixes as operands.  */
 
 static void
-print_hash (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value ATTRIBUTE_UNUSED;
-     unsigned int attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    void * dis_info,
+	    long value ATTRIBUTE_UNUSED,
+	    unsigned int attrs ATTRIBUTE_UNUSED,
+	    bfd_vma pc ATTRIBUTE_UNUSED,
+	    int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
+
   (*info->fprintf_func) (info->stream, "#");
 }
 
@@ -91,10 +88,9 @@ print_hash (cd, dis_info, value, attrs, pc, length)
 #define CGEN_PRINT_INSN my_print_insn
 
 static int
-my_print_insn (cd, pc, info)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
+my_print_insn (CGEN_CPU_DESC cd,
+	       bfd_vma pc,
+	       disassemble_info *info)
 {
   bfd_byte buffer[CGEN_MAX_INSN_SIZE];
   bfd_byte *buf = buffer;
@@ -149,8 +145,7 @@ my_print_insn (cd, pc, info)
 /* -- */
 
 void m32r_cgen_print_operand
-  PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
-           void const *, bfd_vma, int));
+  (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
 
 /* Main entry point for printing operands.
    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@@ -168,16 +163,15 @@ void m32r_cgen_print_operand
    the handlers.  */
 
 void
-m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     PTR xinfo;
-     CGEN_FIELDS *fields;
-     void const *attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     int length;
+m32r_cgen_print_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   void * xinfo,
+			   CGEN_FIELDS *fields,
+			   void const *attrs ATTRIBUTE_UNUSED,
+			   bfd_vma pc,
+			   int length)
 {
- disassemble_info *info = (disassemble_info *) xinfo;
+  disassemble_info *info = (disassemble_info *) xinfo;
 
   switch (opindex)
     {
@@ -272,8 +266,7 @@ cgen_print_fn * const m32r_cgen_print_handlers[] =
 
 
 void
-m32r_cgen_init_dis (cd)
-     CGEN_CPU_DESC cd;
+m32r_cgen_init_dis (CGEN_CPU_DESC cd)
 {
   m32r_cgen_init_opcode_table (cd);
   m32r_cgen_init_ibld_table (cd);
@@ -325,7 +318,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 
   /* Print the operand as directed by the attributes.  */
   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
-    ; /* nothing to do */
+    ; /* Nothing to do.  */
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
     (*info->print_address_func) (value, info);
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@@ -407,6 +400,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
+
   if (status != 0)
     {
       (*info->memory_error_func) (status, pc, info);
@@ -511,13 +505,13 @@ print_insn (CGEN_CPU_DESC cd,
 	    length = CGEN_EXTRACT_FN (cd, insn)
 	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 
-	  /* length < 0 -> error */
+	  /* Length < 0 -> error.  */
 	  if (length < 0)
 	    return length;
 	  if (length > 0)
 	    {
 	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
-	      /* length is in bits, result is in bytes */
+	      /* Length is in bits, result is in bytes.  */
 	      return length / 8;
 	    }
 	}
@@ -567,7 +561,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
    Print one instruction from PC on INFO->STREAM.
    Return the size of the instruction (in bytes).  */
 
-typedef struct cpu_desc_list {
+typedef struct cpu_desc_list
+{
   struct cpu_desc_list *next;
   int isa;
   int mach;
@@ -652,7 +647,7 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info)
       if (!cd)
 	abort ();
 
-      /* save this away for future reference */
+      /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
       cl->isa = isa;
diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c
index 02a05d8..ffd47dd 100644
--- a/opcodes/m32r-ibld.c
+++ b/opcodes/m32r-ibld.c
@@ -1,25 +1,26 @@
 /* Instruction building/extraction support for m32r. -*- C -*-
 
-THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
-- the resultant file is machine generated, cgen-ibld.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+   - the resultant file is machine generated, cgen-ibld.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #include "opintl.h"
 #include "safe-ctype.h"
 
-#undef min
+#undef  min
 #define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
+#undef  max
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 /* Used by the ifield rtx function.  */
@@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
   if (length == 0)
     return NULL;
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
 
 #if CGEN_INT_INSN_P
 /* Cover function to store an insn value into an integral insn.  Must go here
- because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
+   because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
       int shift = insn_length - length;
       /* Written this way to avoid undefined behaviour.  */
       CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
       *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
     }
 }
@@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
 {
   unsigned long x;
   int shift;
-#if 0
-  int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
-#endif
+
   x = cgen_get_insn_value (cd, bufp, word_length);
 
   if (CGEN_INSN_LSB0_P)
@@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
       return 1;
     }
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
   return CGEN_INSN_BITSIZE (insn);
 }
 
-/* machine generated code added here */
+/* Machine generated code added here.  */
 
 const char * m32r_cgen_insert_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 
 /* Main entry point for operand insertion.
 
@@ -559,12 +547,11 @@ const char * m32r_cgen_insert_operand
    resolved during parsing.  */
 
 const char *
-m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+m32r_cgen_insert_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     CGEN_INSN_BYTES_PTR buffer,
+			     bfd_vma pc ATTRIBUTE_UNUSED)
 {
   const char * errmsg = NULL;
   unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@@ -673,8 +660,7 @@ m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
 }
 
 int m32r_cgen_extract_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-           CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 
 /* Main entry point for operand extraction.
    The result is <= 0 for error, >0 for success.
@@ -692,13 +678,12 @@ int m32r_cgen_extract_operand
    the handlers.  */
 
 int
-m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS * fields;
-     bfd_vma pc;
+m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_EXTRACT_INFO *ex_info,
+			     CGEN_INSN_INT insn_value,
+			     CGEN_FIELDS * fields,
+			     bfd_vma pc)
 {
   /* Assume success (for those operands that are nops).  */
   int length = 1;
@@ -821,10 +806,8 @@ cgen_extract_fn * const m32r_cgen_extract_handlers[] =
   extract_insn_normal,
 };
 
-int m32r_cgen_get_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
-bfd_vma m32r_cgen_get_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+int m32r_cgen_get_int_operand     (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+bfd_vma m32r_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
 
 /* Getting values from cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they return.
@@ -832,10 +815,9 @@ bfd_vma m32r_cgen_get_vma_operand
    not appropriate.  */
 
 int
-m32r_cgen_get_int_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+m32r_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   int value;
 
@@ -928,10 +910,9 @@ m32r_cgen_get_int_operand (cd, opindex, fields)
 }
 
 bfd_vma
-m32r_cgen_get_vma_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+m32r_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   bfd_vma value;
 
@@ -1023,10 +1004,8 @@ m32r_cgen_get_vma_operand (cd, opindex, fields)
   return value;
 }
 
-void m32r_cgen_set_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
-void m32r_cgen_set_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+void m32r_cgen_set_int_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
+void m32r_cgen_set_vma_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
 
 /* Stuffing values in cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they accept.
@@ -1034,11 +1013,10 @@ void m32r_cgen_set_vma_operand
    not appropriate.  */
 
 void
-m32r_cgen_set_int_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     int value;
+m32r_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     int value)
 {
   switch (opindex)
     {
@@ -1126,11 +1104,10 @@ m32r_cgen_set_int_operand (cd, opindex, fields, value)
 }
 
 void
-m32r_cgen_set_vma_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     bfd_vma value;
+m32r_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     bfd_vma value)
 {
   switch (opindex)
     {
@@ -1220,8 +1197,7 @@ m32r_cgen_set_vma_operand (cd, opindex, fields, value)
 /* Function to call before using the instruction builder tables.  */
 
 void
-m32r_cgen_init_ibld_table (cd)
-     CGEN_CPU_DESC cd;
+m32r_cgen_init_ibld_table (CGEN_CPU_DESC cd)
 {
   cd->insert_handlers = & m32r_cgen_insert_handlers[0];
   cd->extract_handlers = & m32r_cgen_extract_handlers[0];
diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c
index 670f724..29b7a21 100644
--- a/opcodes/m32r-opc.c
+++ b/opcodes/m32r-opc.c
@@ -32,36 +32,34 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 
 /* -- opc.c */
 unsigned int
-m32r_cgen_dis_hash (buf, value)
-     const char * buf ATTRIBUTE_UNUSED;
-     CGEN_INSN_INT value;
+m32r_cgen_dis_hash (const char * buf ATTRIBUTE_UNUSED, CGEN_INSN_INT value)
 {
   unsigned int x;
-                                                                                
-  if (value & 0xffff0000) /* 32bit instructions */
+
+  if (value & 0xffff0000) /* 32bit instructions.  */
     value = (value >> 16) & 0xffff;
-                                                                                
-  x = (value>>8) & 0xf0;
+
+  x = (value >> 8) & 0xf0;
   if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
     return x;
-                                                                                
+
   if (x == 0x70 || x == 0xf0)
-    return x | ((value>>8) & 0x0f);
-                                                                                
+    return x | ((value >> 8) & 0x0f);
+
   if (x == 0x30)
     return x | ((value & 0x70) >> 4);
   else
     return x | ((value & 0xf0) >> 4);
 }
-                                                                                
+
 /* -- */
 /* The hash functions are recorded here to help keep assembler code out of
    the disassembler and vice versa.  */
 
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static int asm_hash_insn_p        (const CGEN_INSN *);
+static unsigned int asm_hash_insn (const char *);
+static int dis_hash_insn_p        (const CGEN_INSN *);
+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
 
 /* Instruction formats.  */
 
@@ -1778,14 +1776,10 @@ dis_hash_insn (buf, value)
   return CGEN_DIS_HASH (buf, value);
 }
 
-static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
-
 /* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
 
 static void
-set_fields_bitsize (fields, size)
-     CGEN_FIELDS *fields;
-     int size;
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
 {
   CGEN_FIELDS_BITSIZE (fields) = size;
 }
@@ -1794,15 +1788,15 @@ set_fields_bitsize (fields, size)
    This plugs the opcode entries and macro instructions into the cpu table.  */
 
 void
-m32r_cgen_init_opcode_table (cd)
-     CGEN_CPU_DESC cd;
+m32r_cgen_init_opcode_table (CGEN_CPU_DESC cd)
 {
   int i;
   int num_macros = (sizeof (m32r_cgen_macro_insn_table) /
 		    sizeof (m32r_cgen_macro_insn_table[0]));
   const CGEN_IBASE *ib = & m32r_cgen_macro_insn_table[0];
   const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
+
   memset (insns, 0, num_macros * sizeof (CGEN_INSN));
   for (i = 0; i < num_macros; ++i)
     {
diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h
index 2a5df83..d8da2e6 100644
--- a/opcodes/m32r-opc.h
+++ b/opcodes/m32r-opc.h
@@ -39,8 +39,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
   : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
   : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
 #else
-#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash(buffer, value)
-extern unsigned int m32r_cgen_dis_hash(const char *, CGEN_INSN_INT);
+#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash (buffer, value)
+extern unsigned int m32r_cgen_dis_hash (const char *, CGEN_INSN_INT);
 #endif
 
 /* -- */
diff --git a/opcodes/m68k-dis.c b/opcodes/m68k-dis.c
index c24c2ad..3504467 100644
--- a/opcodes/m68k-dis.c
+++ b/opcodes/m68k-dis.c
@@ -15,7 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include "sysdep.h"
 #include "dis-asm.h"
@@ -25,37 +26,28 @@
 
 #include "opcode/m68k.h"
 
-/* Local function prototypes */
-
-static int fetch_data (struct disassemble_info *, bfd_byte *);
-static void dummy_print_address (bfd_vma, struct disassemble_info *);
-static int fetch_arg (unsigned char *, int, int, disassemble_info *);
-static void print_base (int, bfd_vma, disassemble_info *);
-static unsigned char * print_indexed (int, unsigned char *, bfd_vma, disassemble_info *);
-static int print_insn_arg (const char *, unsigned char *, unsigned char *,
-			   bfd_vma, disassemble_info *);
-static bfd_boolean m68k_valid_ea (char code, int val);
+/* Local function prototypes.  */
 
 const char * const fpcr_names[] =
 {
-    "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr",
-    "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr"
+  "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr",
+  "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr"
 };
 
 static char *const reg_names[] =
 {
-    "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
-    "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",
-    "%ps", "%pc"
+  "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
+  "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",
+  "%ps", "%pc"
 };
 
 /* Name of register halves for MAC/EMAC.
    Seperate from reg_names since 'spu', 'fpl' look weird.  */
 static char *const reg_half_names[] =
 {
-    "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
-    "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7",
-    "%ps", "%pc"
+  "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
+  "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7",
+  "%ps", "%pc"
 };
 
 /* Sign-extend an (unsigned char).  */
@@ -112,7 +104,8 @@ static char *const reg_half_names[] =
 
 #include <setjmp.h>
 
-struct private {
+struct private
+{
   /* Points to first byte not fetched.  */
   bfd_byte *max_fetched;
   bfd_byte the_buffer[MAXLEN];
@@ -148,344 +141,436 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
   return 1;
 }
 
-/* This function is used to print to the bit-bucket. */
+/* This function is used to print to the bit-bucket.  */
 static int
-#ifdef __STDC__
 dummy_printer (FILE *file ATTRIBUTE_UNUSED,
-	       const char *format ATTRIBUTE_UNUSED, ...)
-#else
-dummy_printer (FILE *file ATTRIBUTE_UNUSED)
-#endif
+	       const char *format ATTRIBUTE_UNUSED,
+	       ...)
 {
   return 0;
 }
 
 static void
-dummy_print_address (vma, info)
-     bfd_vma vma ATTRIBUTE_UNUSED;
-     struct disassemble_info *info ATTRIBUTE_UNUSED;
+dummy_print_address (bfd_vma vma ATTRIBUTE_UNUSED,
+		     struct disassemble_info *info ATTRIBUTE_UNUSED)
 {
 }
 
-/* Try to match the current instruction to best and if so, return the
-   number of bytes consumed from the instruction stream, else zero.  */
+/* Fetch BITS bits from a position in the instruction specified by CODE.
+   CODE is a "place to put an argument", or 'x' for a destination
+   that is a general address (mode and register).
+   BUFFER contains the instruction.  */
 
 static int
-match_insn_m68k (bfd_vma memaddr, disassemble_info * info,
-		 const struct m68k_opcode * best, struct private * priv)
+fetch_arg (unsigned char *buffer,
+	   int code,
+	   int bits,
+	   disassemble_info *info)
 {
-  unsigned char *save_p;
-  unsigned char *p;
-  const char *d;
+  int val = 0;
 
-  bfd_byte *buffer = priv->the_buffer;
-  fprintf_ftype save_printer = info->fprintf_func;
-  void (* save_print_address) (bfd_vma, struct disassemble_info *)
-    = info->print_address_func;
+  switch (code)
+    {
+    case '/': /* MAC/EMAC mask bit.  */
+      val = buffer[3] >> 5;
+      break;
 
-  /* Point at first word of argument data,
-     and at descriptor for first argument.  */
-  p = buffer + 2;
+    case 'G': /* EMAC ACC load.  */
+      val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1);
+      break;
 
-  /* Figure out how long the fixed-size portion of the instruction is.
-     The only place this is stored in the opcode table is
-     in the arguments--look for arguments which specify fields in the 2nd
-     or 3rd words of the instruction.  */
-  for (d = best->args; *d; d += 2)
-    {
-      /* I don't think it is necessary to be checking d[0] here;
-	 I suspect all this could be moved to the case statement below.  */
-      if (d[0] == '#')
-	{
-	  if (d[1] == 'l' && p - buffer < 6)
-	    p = buffer + 6;
-	  else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8')
-	    p = buffer + 4;
-	}
+    case 'H': /* EMAC ACC !load.  */
+      val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1);
+      break;
 
-      if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4)
-	p = buffer + 4;
+    case ']': /* EMAC ACCEXT bit.  */
+      val = buffer[0] >> 2;
+      break;
 
-      switch (d[1])
-	{
-	case '1':
-	case '2':
-	case '3':
-	case '7':
-	case '8':
-	case '9':
-	case 'i':
-	  if (p - buffer < 4)
-	    p = buffer + 4;
-	  break;
-	case '4':
-	case '5':
-	case '6':
-	  if (p - buffer < 6)
-	    p = buffer + 6;
-	  break;
-	default:
-	  break;
-	}
-    }
+    case 'I': /* MAC/EMAC scale factor.  */
+      val = buffer[2] >> 1;
+      break;
 
-  /* pflusha is an exceptions.  It takes no arguments but is two words
-     long.  Recognize it by looking at the lower 16 bits of the mask.  */
-  if (p - buffer < 4 && (best->match & 0xFFFF) != 0)
-    p = buffer + 4;
+    case 'F': /* EMAC ACCx.  */
+      val = buffer[0] >> 1;
+      break;
 
-  /* lpstop is another exception.  It takes a one word argument but is
-     three words long.  */
-  if (p - buffer < 6
-      && (best->match & 0xffff) == 0xffff
-      && best->args[0] == '#'
-      && best->args[1] == 'w')
-    {
-      /* Copy the one word argument into the usual location for a one
-	 word argument, to simplify printing it.  We can get away with
-	 this because we know exactly what the second word is, and we
-	 aren't going to print anything based on it.  */
-      p = buffer + 6;
-      FETCH_DATA (info, p);
-      buffer[2] = buffer[4];
-      buffer[3] = buffer[5];
-    }
+    case 'f':
+      val = buffer[1];
+      break;
 
-  FETCH_DATA (info, p);
+    case 's':
+      val = buffer[1];
+      break;
 
-  d = best->args;
+    case 'd':			/* Destination, for register or quick.  */
+      val = (buffer[0] << 8) + buffer[1];
+      val >>= 9;
+      break;
 
-  save_p = p;
-  info->print_address_func = dummy_print_address;
-  info->fprintf_func = (fprintf_ftype) dummy_printer;
+    case 'x':			/* Destination, for general arg.  */
+      val = (buffer[0] << 8) + buffer[1];
+      val >>= 6;
+      break;
 
-  /* We scan the operands twice.  The first time we don't print anything,
-     but look for errors. */
-  for (; *d; d += 2)
-    {
-      int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
+    case 'k':
+      FETCH_DATA (info, buffer + 3);
+      val = (buffer[3] >> 4);
+      break;
 
-      if (eaten >= 0)
-	p += eaten;
-      else if (eaten == -1)
-	{
-	  info->fprintf_func = save_printer;
-	  info->print_address_func = save_print_address;
-	  return 0;
-	}
-      else
-	{
-	  info->fprintf_func (info->stream,
-			      /* xgettext:c-format */
-			      _("<internal error in opcode table: %s %s>\n"),
-			      best->name,  best->args);
-	  info->fprintf_func = save_printer;
-	  info->print_address_func = save_print_address;
-	  return 2;
-	}
-    }
+    case 'C':
+      FETCH_DATA (info, buffer + 3);
+      val = buffer[3];
+      break;
 
-  p = save_p;
-  info->fprintf_func = save_printer;
-  info->print_address_func = save_print_address;
+    case '1':
+      FETCH_DATA (info, buffer + 3);
+      val = (buffer[2] << 8) + buffer[3];
+      val >>= 12;
+      break;
 
-  d = best->args;
+    case '2':
+      FETCH_DATA (info, buffer + 3);
+      val = (buffer[2] << 8) + buffer[3];
+      val >>= 6;
+      break;
 
-  info->fprintf_func (info->stream, "%s", best->name);
+    case '3':
+    case 'j':
+      FETCH_DATA (info, buffer + 3);
+      val = (buffer[2] << 8) + buffer[3];
+      break;
 
-  if (*d)
-    info->fprintf_func (info->stream, " ");
+    case '4':
+      FETCH_DATA (info, buffer + 5);
+      val = (buffer[4] << 8) + buffer[5];
+      val >>= 12;
+      break;
 
-  while (*d)
-    {
-      p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
-      d += 2;
+    case '5':
+      FETCH_DATA (info, buffer + 5);
+      val = (buffer[4] << 8) + buffer[5];
+      val >>= 6;
+      break;
 
-      if (*d && *(d - 2) != 'I' && *d != 'k')
-	info->fprintf_func (info->stream, ",");
-    }
+    case '6':
+      FETCH_DATA (info, buffer + 5);
+      val = (buffer[4] << 8) + buffer[5];
+      break;
 
-  return p - buffer;
-}
+    case '7':
+      FETCH_DATA (info, buffer + 3);
+      val = (buffer[2] << 8) + buffer[3];
+      val >>= 7;
+      break;
 
-/* Print the m68k instruction at address MEMADDR in debugged memory,
-   on INFO->STREAM.  Returns length of the instruction, in bytes.  */
+    case '8':
+      FETCH_DATA (info, buffer + 3);
+      val = (buffer[2] << 8) + buffer[3];
+      val >>= 10;
+      break;
 
-int
-print_insn_m68k (bfd_vma memaddr, disassemble_info *info)
-{
-  int i;
-  const char *d;
-  unsigned int arch_mask;
-  struct private priv;
-  bfd_byte *buffer = priv.the_buffer;
-  int major_opcode;
-  static int numopcodes[16];
-  static const struct m68k_opcode **opcodes[16];
-  int val;
+    case '9':
+      FETCH_DATA (info, buffer + 3);
+      val = (buffer[2] << 8) + buffer[3];
+      val >>= 5;
+      break;
 
-  if (!opcodes[0])
-    {
-      /* Speed up the matching by sorting the opcode
-	 table on the upper four bits of the opcode.  */
-      const struct m68k_opcode **opc_pointer[16];
+    case 'e':
+      val = (buffer[1] >> 6);
+      break;
 
-      /* First count how many opcodes are in each of the sixteen buckets.  */
-      for (i = 0; i < m68k_numopcodes; i++)
-	numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++;
+    case 'm':
+      val = (buffer[1] & 0x40 ? 0x8 : 0)
+	| ((buffer[0] >> 1) & 0x7)
+	| (buffer[3] & 0x80 ? 0x10 : 0);
+      break;
 
-      /* Then create a sorted table of pointers
-	 that point into the unsorted table.  */
-      opc_pointer[0] = xmalloc (sizeof (struct m68k_opcode *)
-				* m68k_numopcodes);
-      opcodes[0] = opc_pointer[0];
+    case 'n':
+      val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7);
+      break;
 
-      for (i = 1; i < 16; i++)
-	{
-	  opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1];
-	  opcodes[i] = opc_pointer[i];
-	}
+    case 'o':
+      val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0);
+      break;
 
-      for (i = 0; i < m68k_numopcodes; i++)
-	*opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i];
-    }
+    case 'M':
+      val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
+      break;
 
-  info->private_data = (PTR) &priv;
-  /* Tell objdump to use two bytes per chunk
-     and six bytes per line for displaying raw data.  */
-  info->bytes_per_chunk = 2;
-  info->bytes_per_line = 6;
-  info->display_endian = BFD_ENDIAN_BIG;
-  priv.max_fetched = priv.the_buffer;
-  priv.insn_start = memaddr;
+    case 'N':
+      val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
+      break;
 
-  if (setjmp (priv.bailout) != 0)
-    /* Error return.  */
-    return -1;
+    case 'h':
+      val = buffer[2] >> 2;
+      break;
 
-  switch (info->mach)
+    default:
+      abort ();
+    }
+
+  switch (bits)
     {
+    case 1:
+      return val & 1;
+    case 2:
+      return val & 3;
+    case 3:
+      return val & 7;
+    case 4:
+      return val & 017;
+    case 5:
+      return val & 037;
+    case 6:
+      return val & 077;
+    case 7:
+      return val & 0177;
+    case 8:
+      return val & 0377;
+    case 12:
+      return val & 07777;
     default:
-    case 0:
-      arch_mask = (unsigned int) -1;
+      abort ();
+    }
+}
+
+/* Check if an EA is valid for a particular code.  This is required
+   for the EMAC instructions since the type of source address determines
+   if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it
+   is a non-load EMAC instruction and the bits mean register Ry.
+   A similar case exists for the movem instructions where the register
+   mask is interpreted differently for different EAs.  */
+
+static bfd_boolean
+m68k_valid_ea (char code, int val)
+{
+  int mode, mask;
+#define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \
+  (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \
+   | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11)
+
+  switch (code)
+    {
+    case '*':
+      mask = M (1,1,1,1,1,1,1,1,1,1,1,1);
       break;
-    case bfd_mach_m68000:
-      arch_mask = m68000|m68881|m68851;
+    case '~':
+      mask = M (0,0,1,1,1,1,1,1,1,0,0,0);
       break;
-    case bfd_mach_m68008:
-      arch_mask = m68008|m68881|m68851;
+    case '%':
+      mask = M (1,1,1,1,1,1,1,1,1,0,0,0);
       break;
-    case bfd_mach_m68010:
-      arch_mask = m68010|m68881|m68851;
+    case ';':
+      mask = M (1,0,1,1,1,1,1,1,1,1,1,1);
       break;
-    case bfd_mach_m68020:
-      arch_mask = m68020|m68881|m68851;
+    case '@':
+      mask = M (1,0,1,1,1,1,1,1,1,1,1,0);
       break;
-    case bfd_mach_m68030:
-      arch_mask = m68030|m68881|m68851;
+    case '!':
+      mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
       break;
-    case bfd_mach_m68040:
-      arch_mask = m68040|m68881|m68851;
+    case '&':
+      mask = M (0,0,1,0,0,1,1,1,1,0,0,0);
       break;
-    case bfd_mach_m68060:
-      arch_mask = m68060|m68881|m68851;
+    case '$':
+      mask = M (1,0,1,1,1,1,1,1,1,0,0,0);
       break;
-    case bfd_mach_mcf5200:
-      arch_mask = mcfisa_a;
+    case '?':
+      mask = M (1,0,1,0,0,1,1,1,1,0,0,0);
       break;
-    case bfd_mach_mcf521x:
-    case bfd_mach_mcf528x:
-      arch_mask = mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp|mcfemac;
+    case '/':
+      mask = M (1,0,1,0,0,1,1,1,1,1,1,0);
       break;
-    case bfd_mach_mcf5206e:
-      arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
+    case '|':
+      mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
       break;
-    case bfd_mach_mcf5249:
-      arch_mask = mcfisa_a|mcfhwdiv|mcfemac;
+    case '>':
+      mask = M (0,0,1,0,1,1,1,1,1,0,0,0);
       break;
-    case bfd_mach_mcf5307:
-      arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
+    case '<':
+      mask = M (0,0,1,1,0,1,1,1,1,1,1,0);
       break;
-    case bfd_mach_mcf5407:
-      arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac;
+    case 'm':
+      mask = M (1,1,1,1,1,0,0,0,0,0,0,0);
       break;
-    case bfd_mach_mcf547x:
-    case bfd_mach_mcf548x:
-    case bfd_mach_mcfv4e:
-      arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac;
+    case 'n':
+      mask = M (0,0,0,0,0,1,0,0,0,1,0,0);
+      break;
+    case 'o':
+      mask = M (0,0,0,0,0,0,1,1,1,0,1,1);
+      break;
+    case 'p':
+      mask = M (1,1,1,1,1,1,0,0,0,0,0,0);
+      break;
+    case 'q':
+      mask = M (1,0,1,1,1,1,0,0,0,0,0,0);
+      break;
+    case 'v':
+      mask = M (1,0,1,1,1,1,0,1,1,0,0,0);
       break;
+    case 'b':
+      mask = M (1,0,1,1,1,1,0,0,0,1,0,0);
+      break;
+    case 'w':
+      mask = M (0,0,1,1,1,1,0,0,0,1,0,0);
+      break;
+    case 'y':
+      mask = M (0,0,1,0,0,1,0,0,0,0,0,0);
+      break;
+    case 'z':
+      mask = M (0,0,1,0,0,1,0,0,0,1,0,0);
+      break;
+    case '4':
+      mask = M (0,0,1,1,1,1,0,0,0,0,0,0);
+      break;
+    default:
+      abort ();
     }
+#undef M
 
-  FETCH_DATA (info, buffer + 2);
-  major_opcode = (buffer[0] >> 4) & 15;
+  mode = (val >> 3) & 7;
+  if (mode == 7)
+    mode += val & 7;
+  return (mask & (1 << mode)) != 0;
+}
 
-  for (i = 0; i < numopcodes[major_opcode]; i++)
+/* Print a base register REGNO and displacement DISP, on INFO->STREAM.
+   REGNO = -1 for pc, -2 for none (suppressed).  */
+
+static void
+print_base (int regno, bfd_vma disp, disassemble_info *info)
+{
+  if (regno == -1)
     {
-      const struct m68k_opcode *opc = opcodes[major_opcode][i];
-      unsigned long opcode = opc->opcode;
-      unsigned long match = opc->match;
+      (*info->fprintf_func) (info->stream, "%%pc@(");
+      (*info->print_address_func) (disp, info);
+    }
+  else
+    {
+      char buf[50];
 
-      if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24)))
-	  && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16)))
-	  /* Only fetch the next two bytes if we need to.  */
-	  && (((0xffff & match) == 0)
-	      ||
-	      (FETCH_DATA (info, buffer + 4)
-	       && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8)))
-	       && ((0xff & buffer[3] & match) == (0xff & opcode)))
-	      )
-	  && (opc->arch & arch_mask) != 0)
-	{
-	  /* Don't use for printout the variants of divul and divsl
-	     that have the same register number in two places.
-	     The more general variants will match instead.  */
-	  for (d = opc->args; *d; d += 2)
-	    if (d[1] == 'D')
-	      break;
+      if (regno == -2)
+	(*info->fprintf_func) (info->stream, "@(");
+      else if (regno == -3)
+	(*info->fprintf_func) (info->stream, "%%zpc@(");
+      else
+	(*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]);
 
-	  /* Don't use for printout the variants of most floating
-	     point coprocessor instructions which use the same
-	     register number in two places, as above.  */
-	  if (*d == '\0')
-	    for (d = opc->args; *d; d += 2)
-	      if (d[1] == 't')
-		break;
+      sprintf_vma (buf, disp);
+      (*info->fprintf_func) (info->stream, "%s", buf);
+    }
+}
 
-	  /* Don't match fmovel with more than one register;
-	     wait for fmoveml.  */
-	  if (*d == '\0')
-	    {
-	      for (d = opc->args; *d; d += 2)
-		{
-		  if (d[0] == 's' && d[1] == '8')
-		    {
-		      val = fetch_arg (buffer, d[1], 3, info);
-		      if ((val & (val - 1)) != 0)
-			break;
-		    }
-		}
-	    }
+/* Print an indexed argument.  The base register is BASEREG (-1 for pc).
+   P points to extension word, in buffer.
+   ADDR is the nominal core address of that extension word.  */
 
-	  if (*d == '\0')
-	    if ((val = match_insn_m68k (memaddr, info, opc, & priv)))
-	      return val;
-	}
+static unsigned char *
+print_indexed (int basereg,
+	       unsigned char *p,
+	       bfd_vma addr,
+	       disassemble_info *info)
+{
+  int word;
+  static char *const scales[] = { "", ":2", ":4", ":8" };
+  bfd_vma base_disp;
+  bfd_vma outer_disp;
+  char buf[40];
+  char vmabuf[50];
+
+  word = NEXTWORD (p);
+
+  /* Generate the text for the index register.
+     Where this will be output is not yet determined.  */
+  sprintf (buf, "%s:%c%s",
+	   reg_names[(word >> 12) & 0xf],
+	   (word & 0x800) ? 'l' : 'w',
+	   scales[(word >> 9) & 3]);
+
+  /* Handle the 68000 style of indexing.  */
+
+  if ((word & 0x100) == 0)
+    {
+      base_disp = word & 0xff;
+      if ((base_disp & 0x80) != 0)
+	base_disp -= 0x100;
+      if (basereg == -1)
+	base_disp += addr;
+      print_base (basereg, base_disp, info);
+      (*info->fprintf_func) (info->stream, ",%s)", buf);
+      return p;
     }
 
-  /* Handle undefined instructions.  */
-  info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]);
-  return 2;
+  /* Handle the generalized kind.  */
+  /* First, compute the displacement to add to the base register.  */
+  if (word & 0200)
+    {
+      if (basereg == -1)
+	basereg = -3;
+      else
+	basereg = -2;
+    }
+  if (word & 0100)
+    buf[0] = '\0';
+  base_disp = 0;
+  switch ((word >> 4) & 3)
+    {
+    case 2:
+      base_disp = NEXTWORD (p);
+      break;
+    case 3:
+      base_disp = NEXTLONG (p);
+    }
+  if (basereg == -1)
+    base_disp += addr;
+
+  /* Handle single-level case (not indirect).  */
+  if ((word & 7) == 0)
+    {
+      print_base (basereg, base_disp, info);
+      if (buf[0] != '\0')
+	(*info->fprintf_func) (info->stream, ",%s", buf);
+      (*info->fprintf_func) (info->stream, ")");
+      return p;
+    }
+
+  /* Two level.  Compute displacement to add after indirection.  */
+  outer_disp = 0;
+  switch (word & 3)
+    {
+    case 2:
+      outer_disp = NEXTWORD (p);
+      break;
+    case 3:
+      outer_disp = NEXTLONG (p);
+    }
+
+  print_base (basereg, base_disp, info);
+  if ((word & 4) == 0 && buf[0] != '\0')
+    {
+      (*info->fprintf_func) (info->stream, ",%s", buf);
+      buf[0] = '\0';
+    }
+  sprintf_vma (vmabuf, outer_disp);
+  (*info->fprintf_func) (info->stream, ")@(%s", vmabuf);
+  if (buf[0] != '\0')
+    (*info->fprintf_func) (info->stream, ",%s", buf);
+  (*info->fprintf_func) (info->stream, ")");
+
+  return p;
 }
 
 /* Returns number of bytes "eaten" by the operand, or
    return -1 if an invalid operand was found, or -2 if
-   an opcode tabe error was found.  */
-
-/* ADDR is the pc for this arg to be relative to.  */
+   an opcode tabe error was found.
+   ADDR is the pc for this arg to be relative to.  */
 
 static int
-print_insn_arg (const char *d, unsigned char *buffer,
-		unsigned char *p0, bfd_vma addr,
+print_insn_arg (const char *d,
+		unsigned char *buffer,
+		unsigned char *p0,
+		bfd_vma addr,
 		disassemble_info *info)
 {
   int val = 0;
@@ -675,7 +760,7 @@ print_insn_arg (const char *d, unsigned char *buffer,
       else if (place == 'C')
 	{
 	  val = fetch_arg (buffer, place, 7, info);
-	  if (val > 63)		/* This is a signed constant. */
+	  if (val > 63)		/* This is a signed constant.  */
 	    val -= 128;
 	  (*info->fprintf_func) (info->stream, "{#%d}", val);
 	}
@@ -724,7 +809,7 @@ print_insn_arg (const char *d, unsigned char *buffer,
 	}
       else if (place == 'c')
 	{
-	  if (buffer[1] & 0x40)		/* If bit six is one, long offset */
+	  if (buffer[1] & 0x40)		/* If bit six is one, long offset.  */
 	    disp = NEXTLONG (p);
 	  else
 	    disp = NEXTWORD (p);
@@ -756,7 +841,7 @@ print_insn_arg (const char *d, unsigned char *buffer,
       val = fetch_arg(buffer, place, 1, info);
       (*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23");
       break;
-      
+
     case 'i':
       val = fetch_arg(buffer, place, 2, info);
       if (val == 1)
@@ -771,7 +856,7 @@ print_insn_arg (const char *d, unsigned char *buffer,
       /* Get coprocessor ID... */
       val = fetch_arg (buffer, 'd', 3, info);
 
-      if (val != 1)				/* Unusual coprocessor ID? */
+      if (val != 1)				/* Unusual coprocessor ID?  */
 	(*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
       break;
 
@@ -946,7 +1031,8 @@ print_insn_arg (const char *d, unsigned char *buffer,
 	      }
 	    if (*d == 'l')
 	      {
-		register int newval = 0;
+		int newval = 0;
+
 		for (regno = 0; regno < 16; ++regno)
 		  if (val & (0x8000 >> regno))
 		    newval |= 1 << regno;
@@ -958,6 +1044,7 @@ print_insn_arg (const char *d, unsigned char *buffer,
 	      if (val & (1 << regno))
 		{
 		  int first_regno;
+
 		  if (doneany)
 		    (*info->fprintf_func) (info->stream, "/");
 		  doneany = 1;
@@ -982,7 +1069,8 @@ print_insn_arg (const char *d, unsigned char *buffer,
 	      }
 	    if (*d == 'l')
 	      {
-		register int newval = 0;
+		int newval = 0;
+
 		for (regno = 0; regno < 8; ++regno)
 		  if (val & (0x80 >> regno))
 		    newval |= 1 << regno;
@@ -1007,7 +1095,7 @@ print_insn_arg (const char *d, unsigned char *buffer,
 	  }
 	else if (place == '8')
 	  {
-	    /* fmoveml for FP status registers */
+	    /* fmoveml for FP status registers.  */
 	    (*info->fprintf_func) (info->stream, "%s",
 				   fpcr_names[fetch_arg (buffer, place, 3,
 							 info)]);
@@ -1028,6 +1116,7 @@ print_insn_arg (const char *d, unsigned char *buffer,
       {
 	int val = fetch_arg (buffer, place, 5, info);
 	char *name = 0;
+
 	switch (val)
 	  {
 	  case 2: name = "%tt0"; break;
@@ -1046,6 +1135,7 @@ print_insn_arg (const char *d, unsigned char *buffer,
 	  case 0x1d:
 	    {
 	      int break_reg = ((buffer[3] >> 2) & 7);
+
 	      (*info->fprintf_func)
 		(info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d",
 		 break_reg);
@@ -1062,6 +1152,7 @@ print_insn_arg (const char *d, unsigned char *buffer,
     case 'f':
       {
 	int fc = fetch_arg (buffer, place, 5, info);
+
 	if (fc == 1)
 	  (*info->fprintf_func) (info->stream, "%%dfc");
 	else if (fc == 0)
@@ -1079,6 +1170,7 @@ print_insn_arg (const char *d, unsigned char *buffer,
     case 't':
       {
 	int level = fetch_arg (buffer, place, 3, info);
+
 	(*info->fprintf_func) (info->stream, "%d", level);
       }
       break;
@@ -1106,406 +1198,314 @@ print_insn_arg (const char *d, unsigned char *buffer,
   return p - p0;
 }
 
-/* Check if an EA is valid for a particular code.  This is required
-   for the EMAC instructions since the type of source address determines
-   if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it
-   is a non-load EMAC instruction and the bits mean register Ry.
-   A similar case exists for the movem instructions where the register
-   mask is interpreted differently for different EAs.  */
+/* Try to match the current instruction to best and if so, return the
+   number of bytes consumed from the instruction stream, else zero.  */
 
-static bfd_boolean
-m68k_valid_ea (char code, int val)
+static int
+match_insn_m68k (bfd_vma memaddr,
+		 disassemble_info * info,
+		 const struct m68k_opcode * best,
+		 struct private * priv)
 {
-  int mode, mask;
-#define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \
-  (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \
-   | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11)
+  unsigned char *save_p;
+  unsigned char *p;
+  const char *d;
 
-  switch (code)
+  bfd_byte *buffer = priv->the_buffer;
+  fprintf_ftype save_printer = info->fprintf_func;
+  void (* save_print_address) (bfd_vma, struct disassemble_info *)
+    = info->print_address_func;
+
+  /* Point at first word of argument data,
+     and at descriptor for first argument.  */
+  p = buffer + 2;
+
+  /* Figure out how long the fixed-size portion of the instruction is.
+     The only place this is stored in the opcode table is
+     in the arguments--look for arguments which specify fields in the 2nd
+     or 3rd words of the instruction.  */
+  for (d = best->args; *d; d += 2)
     {
-    case '*':
-      mask = M (1,1,1,1,1,1,1,1,1,1,1,1);
-      break;
-    case '~':
-      mask = M (0,0,1,1,1,1,1,1,1,0,0,0);
-      break;
-    case '%':
-      mask = M (1,1,1,1,1,1,1,1,1,0,0,0);
-      break;
-    case ';':
-      mask = M (1,0,1,1,1,1,1,1,1,1,1,1);
-      break;
-    case '@':
-      mask = M (1,0,1,1,1,1,1,1,1,1,1,0);
-      break;
-    case '!':
-      mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
-      break;
-    case '&':
-      mask = M (0,0,1,0,0,1,1,1,1,0,0,0);
-      break;
-    case '$':
-      mask = M (1,0,1,1,1,1,1,1,1,0,0,0);
-      break;
-    case '?':
-      mask = M (1,0,1,0,0,1,1,1,1,0,0,0);
-      break;
-    case '/':
-      mask = M (1,0,1,0,0,1,1,1,1,1,1,0);
-      break;
-    case '|':
-      mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
-      break;
-    case '>':
-      mask = M (0,0,1,0,1,1,1,1,1,0,0,0);
-      break;
-    case '<':
-      mask = M (0,0,1,1,0,1,1,1,1,1,1,0);
-      break;
-    case 'm':
-      mask = M (1,1,1,1,1,0,0,0,0,0,0,0);
-      break;
-    case 'n':
-      mask = M (0,0,0,0,0,1,0,0,0,1,0,0);
-      break;
-    case 'o':
-      mask = M (0,0,0,0,0,0,1,1,1,0,1,1);
-      break;
-    case 'p':
-      mask = M (1,1,1,1,1,1,0,0,0,0,0,0);
-      break;
-    case 'q':
-      mask = M (1,0,1,1,1,1,0,0,0,0,0,0);
-      break;
-    case 'v':
-      mask = M (1,0,1,1,1,1,0,1,1,0,0,0);
-      break;
-    case 'b':
-      mask = M (1,0,1,1,1,1,0,0,0,1,0,0);
-      break;
-    case 'w':
-      mask = M (0,0,1,1,1,1,0,0,0,1,0,0);
-      break;
-    case 'y':
-      mask = M (0,0,1,0,0,1,0,0,0,0,0,0);
-      break;
-    case 'z':
-      mask = M (0,0,1,0,0,1,0,0,0,1,0,0);
-      break;
-    case '4':
-      mask = M (0,0,1,1,1,1,0,0,0,0,0,0);
-      break;
-    default:
-      abort ();
+      /* I don't think it is necessary to be checking d[0] here;
+	 I suspect all this could be moved to the case statement below.  */
+      if (d[0] == '#')
+	{
+	  if (d[1] == 'l' && p - buffer < 6)
+	    p = buffer + 6;
+	  else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8')
+	    p = buffer + 4;
+	}
+
+      if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4)
+	p = buffer + 4;
+
+      switch (d[1])
+	{
+	case '1':
+	case '2':
+	case '3':
+	case '7':
+	case '8':
+	case '9':
+	case 'i':
+	  if (p - buffer < 4)
+	    p = buffer + 4;
+	  break;
+	case '4':
+	case '5':
+	case '6':
+	  if (p - buffer < 6)
+	    p = buffer + 6;
+	  break;
+	default:
+	  break;
+	}
     }
-#undef M
 
-  mode = (val >> 3) & 7;
-  if (mode == 7)
-    mode += val & 7;
-  return (mask & (1 << mode)) != 0;
-}
+  /* pflusha is an exceptions.  It takes no arguments but is two words
+     long.  Recognize it by looking at the lower 16 bits of the mask.  */
+  if (p - buffer < 4 && (best->match & 0xFFFF) != 0)
+    p = buffer + 4;
 
-/* Fetch BITS bits from a position in the instruction specified by CODE.
-   CODE is a "place to put an argument", or 'x' for a destination
-   that is a general address (mode and register).
-   BUFFER contains the instruction.  */
+  /* lpstop is another exception.  It takes a one word argument but is
+     three words long.  */
+  if (p - buffer < 6
+      && (best->match & 0xffff) == 0xffff
+      && best->args[0] == '#'
+      && best->args[1] == 'w')
+    {
+      /* Copy the one word argument into the usual location for a one
+	 word argument, to simplify printing it.  We can get away with
+	 this because we know exactly what the second word is, and we
+	 aren't going to print anything based on it.  */
+      p = buffer + 6;
+      FETCH_DATA (info, p);
+      buffer[2] = buffer[4];
+      buffer[3] = buffer[5];
+    }
 
-static int
-fetch_arg (unsigned char *buffer, int code, int bits,
-	   disassemble_info *info)
-{
-  int val = 0;
+  FETCH_DATA (info, p);
 
-  switch (code)
+  d = best->args;
+
+  save_p = p;
+  info->print_address_func = dummy_print_address;
+  info->fprintf_func = (fprintf_ftype) dummy_printer;
+
+  /* We scan the operands twice.  The first time we don't print anything,
+     but look for errors.  */
+  for (; *d; d += 2)
     {
-    case '/': /* MAC/EMAC mask bit.  */
-      val = buffer[3] >> 5;
-      break;
+      int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
 
-    case 'G': /* EMAC ACC load.  */
-      val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1);
-      break;
+      if (eaten >= 0)
+	p += eaten;
+      else if (eaten == -1)
+	{
+	  info->fprintf_func = save_printer;
+	  info->print_address_func = save_print_address;
+	  return 0;
+	}
+      else
+	{
+	  info->fprintf_func (info->stream,
+			      /* xgettext:c-format */
+			      _("<internal error in opcode table: %s %s>\n"),
+			      best->name,  best->args);
+	  info->fprintf_func = save_printer;
+	  info->print_address_func = save_print_address;
+	  return 2;
+	}
+    }
 
-    case 'H': /* EMAC ACC !load.  */
-      val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1);
-      break;
+  p = save_p;
+  info->fprintf_func = save_printer;
+  info->print_address_func = save_print_address;
 
-    case ']': /* EMAC ACCEXT bit.  */
-      val = buffer[0] >> 2;
-      break;
+  d = best->args;
 
-    case 'I': /* MAC/EMAC scale factor.  */
-      val = buffer[2] >> 1;
-      break;
+  info->fprintf_func (info->stream, "%s", best->name);
 
-    case 'F': /* EMAC ACCx.  */
-      val = buffer[0] >> 1;
-      break;
+  if (*d)
+    info->fprintf_func (info->stream, " ");
 
-    case 'f':
-      val = buffer[1];
-      break;
+  while (*d)
+    {
+      p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
+      d += 2;
 
-    case 's':
-      val = buffer[1];
-      break;
+      if (*d && *(d - 2) != 'I' && *d != 'k')
+	info->fprintf_func (info->stream, ",");
+    }
 
-    case 'd':			/* Destination, for register or quick.  */
-      val = (buffer[0] << 8) + buffer[1];
-      val >>= 9;
-      break;
+  return p - buffer;
+}
 
-    case 'x':			/* Destination, for general arg */
-      val = (buffer[0] << 8) + buffer[1];
-      val >>= 6;
-      break;
+/* Print the m68k instruction at address MEMADDR in debugged memory,
+   on INFO->STREAM.  Returns length of the instruction, in bytes.  */
 
-    case 'k':
-      FETCH_DATA (info, buffer + 3);
-      val = (buffer[3] >> 4);
-      break;
+int
+print_insn_m68k (bfd_vma memaddr, disassemble_info *info)
+{
+  int i;
+  const char *d;
+  unsigned int arch_mask;
+  struct private priv;
+  bfd_byte *buffer = priv.the_buffer;
+  int major_opcode;
+  static int numopcodes[16];
+  static const struct m68k_opcode **opcodes[16];
+  int val;
 
-    case 'C':
-      FETCH_DATA (info, buffer + 3);
-      val = buffer[3];
-      break;
+  if (!opcodes[0])
+    {
+      /* Speed up the matching by sorting the opcode
+	 table on the upper four bits of the opcode.  */
+      const struct m68k_opcode **opc_pointer[16];
 
-    case '1':
-      FETCH_DATA (info, buffer + 3);
-      val = (buffer[2] << 8) + buffer[3];
-      val >>= 12;
-      break;
+      /* First count how many opcodes are in each of the sixteen buckets.  */
+      for (i = 0; i < m68k_numopcodes; i++)
+	numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++;
 
-    case '2':
-      FETCH_DATA (info, buffer + 3);
-      val = (buffer[2] << 8) + buffer[3];
-      val >>= 6;
-      break;
+      /* Then create a sorted table of pointers
+	 that point into the unsorted table.  */
+      opc_pointer[0] = xmalloc (sizeof (struct m68k_opcode *)
+				* m68k_numopcodes);
+      opcodes[0] = opc_pointer[0];
 
-    case '3':
-    case 'j':
-      FETCH_DATA (info, buffer + 3);
-      val = (buffer[2] << 8) + buffer[3];
-      break;
+      for (i = 1; i < 16; i++)
+	{
+	  opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1];
+	  opcodes[i] = opc_pointer[i];
+	}
 
-    case '4':
-      FETCH_DATA (info, buffer + 5);
-      val = (buffer[4] << 8) + buffer[5];
-      val >>= 12;
-      break;
+      for (i = 0; i < m68k_numopcodes; i++)
+	*opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i];
+    }
 
-    case '5':
-      FETCH_DATA (info, buffer + 5);
-      val = (buffer[4] << 8) + buffer[5];
-      val >>= 6;
-      break;
+  info->private_data = (PTR) &priv;
+  /* Tell objdump to use two bytes per chunk
+     and six bytes per line for displaying raw data.  */
+  info->bytes_per_chunk = 2;
+  info->bytes_per_line = 6;
+  info->display_endian = BFD_ENDIAN_BIG;
+  priv.max_fetched = priv.the_buffer;
+  priv.insn_start = memaddr;
 
-    case '6':
-      FETCH_DATA (info, buffer + 5);
-      val = (buffer[4] << 8) + buffer[5];
-      break;
+  if (setjmp (priv.bailout) != 0)
+    /* Error return.  */
+    return -1;
 
-    case '7':
-      FETCH_DATA (info, buffer + 3);
-      val = (buffer[2] << 8) + buffer[3];
-      val >>= 7;
+  switch (info->mach)
+    {
+    default:
+    case 0:
+      arch_mask = (unsigned int) -1;
       break;
-
-    case '8':
-      FETCH_DATA (info, buffer + 3);
-      val = (buffer[2] << 8) + buffer[3];
-      val >>= 10;
+    case bfd_mach_m68000:
+      arch_mask = m68000|m68881|m68851;
       break;
-
-    case '9':
-      FETCH_DATA (info, buffer + 3);
-      val = (buffer[2] << 8) + buffer[3];
-      val >>= 5;
+    case bfd_mach_m68008:
+      arch_mask = m68008|m68881|m68851;
       break;
-
-    case 'e':
-      val = (buffer[1] >> 6);
+    case bfd_mach_m68010:
+      arch_mask = m68010|m68881|m68851;
       break;
-
-    case 'm':
-      val = (buffer[1] & 0x40 ? 0x8 : 0)
-	| ((buffer[0] >> 1) & 0x7)
-	| (buffer[3] & 0x80 ? 0x10 : 0);
+    case bfd_mach_m68020:
+      arch_mask = m68020|m68881|m68851;
       break;
-
-    case 'n':
-      val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7);
+    case bfd_mach_m68030:
+      arch_mask = m68030|m68881|m68851;
       break;
-
-    case 'o':
-      val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0);
+    case bfd_mach_m68040:
+      arch_mask = m68040|m68881|m68851;
       break;
-
-    case 'M':
-      val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
+    case bfd_mach_m68060:
+      arch_mask = m68060|m68881|m68851;
       break;
-
-    case 'N':
-      val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
+    case bfd_mach_mcf5200:
+      arch_mask = mcfisa_a;
       break;
-
-    case 'h':
-      val = buffer[2] >> 2;
+    case bfd_mach_mcf521x:
+    case bfd_mach_mcf528x:
+      arch_mask = mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp|mcfemac;
       break;
-
-    default:
-      abort ();
-    }
-
-  switch (bits)
-    {
-    case 1:
-      return val & 1;
-    case 2:
-      return val & 3;
-    case 3:
-      return val & 7;
-    case 4:
-      return val & 017;
-    case 5:
-      return val & 037;
-    case 6:
-      return val & 077;
-    case 7:
-      return val & 0177;
-    case 8:
-      return val & 0377;
-    case 12:
-      return val & 07777;
-    default:
-      abort ();
-    }
-}
-
-/* Print an indexed argument.  The base register is BASEREG (-1 for pc).
-   P points to extension word, in buffer.
-   ADDR is the nominal core address of that extension word.  */
-
-static unsigned char *
-print_indexed (int basereg, unsigned char *p,
-	       bfd_vma addr, disassemble_info *info)
-{
-  int word;
-  static char *const scales[] = { "", ":2", ":4", ":8" };
-  bfd_vma base_disp;
-  bfd_vma outer_disp;
-  char buf[40];
-  char vmabuf[50];
-
-  word = NEXTWORD (p);
-
-  /* Generate the text for the index register.
-     Where this will be output is not yet determined.  */
-  sprintf (buf, "%s:%c%s",
-	   reg_names[(word >> 12) & 0xf],
-	   (word & 0x800) ? 'l' : 'w',
-	   scales[(word >> 9) & 3]);
-
-  /* Handle the 68000 style of indexing.  */
-
-  if ((word & 0x100) == 0)
-    {
-      base_disp = word & 0xff;
-      if ((base_disp & 0x80) != 0)
-	base_disp -= 0x100;
-      if (basereg == -1)
-	base_disp += addr;
-      print_base (basereg, base_disp, info);
-      (*info->fprintf_func) (info->stream, ",%s)", buf);
-      return p;
-    }
-
-  /* Handle the generalized kind.  */
-  /* First, compute the displacement to add to the base register.  */
-
-  if (word & 0200)
-    {
-      if (basereg == -1)
-	basereg = -3;
-      else
-	basereg = -2;
-    }
-  if (word & 0100)
-    buf[0] = '\0';
-  base_disp = 0;
-  switch ((word >> 4) & 3)
-    {
-    case 2:
-      base_disp = NEXTWORD (p);
+    case bfd_mach_mcf5206e:
+      arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
+      break;
+    case bfd_mach_mcf5249:
+      arch_mask = mcfisa_a|mcfhwdiv|mcfemac;
+      break;
+    case bfd_mach_mcf5307:
+      arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
+      break;
+    case bfd_mach_mcf5407:
+      arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac;
+      break;
+    case bfd_mach_mcf547x:
+    case bfd_mach_mcf548x:
+    case bfd_mach_mcfv4e:
+      arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac;
       break;
-    case 3:
-      base_disp = NEXTLONG (p);
-    }
-  if (basereg == -1)
-    base_disp += addr;
-
-  /* Handle single-level case (not indirect) */
-
-  if ((word & 7) == 0)
-    {
-      print_base (basereg, base_disp, info);
-      if (buf[0] != '\0')
-	(*info->fprintf_func) (info->stream, ",%s", buf);
-      (*info->fprintf_func) (info->stream, ")");
-      return p;
     }
 
-  /* Two level.  Compute displacement to add after indirection.  */
+  FETCH_DATA (info, buffer + 2);
+  major_opcode = (buffer[0] >> 4) & 15;
 
-  outer_disp = 0;
-  switch (word & 3)
+  for (i = 0; i < numopcodes[major_opcode]; i++)
     {
-    case 2:
-      outer_disp = NEXTWORD (p);
-      break;
-    case 3:
-      outer_disp = NEXTLONG (p);
-    }
+      const struct m68k_opcode *opc = opcodes[major_opcode][i];
+      unsigned long opcode = opc->opcode;
+      unsigned long match = opc->match;
 
-  print_base (basereg, base_disp, info);
-  if ((word & 4) == 0 && buf[0] != '\0')
-    {
-      (*info->fprintf_func) (info->stream, ",%s", buf);
-      buf[0] = '\0';
-    }
-  sprintf_vma (vmabuf, outer_disp);
-  (*info->fprintf_func) (info->stream, ")@(%s", vmabuf);
-  if (buf[0] != '\0')
-    (*info->fprintf_func) (info->stream, ",%s", buf);
-  (*info->fprintf_func) (info->stream, ")");
+      if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24)))
+	  && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16)))
+	  /* Only fetch the next two bytes if we need to.  */
+	  && (((0xffff & match) == 0)
+	      ||
+	      (FETCH_DATA (info, buffer + 4)
+	       && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8)))
+	       && ((0xff & buffer[3] & match) == (0xff & opcode)))
+	      )
+	  && (opc->arch & arch_mask) != 0)
+	{
+	  /* Don't use for printout the variants of divul and divsl
+	     that have the same register number in two places.
+	     The more general variants will match instead.  */
+	  for (d = opc->args; *d; d += 2)
+	    if (d[1] == 'D')
+	      break;
 
-  return p;
-}
+	  /* Don't use for printout the variants of most floating
+	     point coprocessor instructions which use the same
+	     register number in two places, as above.  */
+	  if (*d == '\0')
+	    for (d = opc->args; *d; d += 2)
+	      if (d[1] == 't')
+		break;
 
-/* Print a base register REGNO and displacement DISP, on INFO->STREAM.
-   REGNO = -1 for pc, -2 for none (suppressed).  */
+	  /* Don't match fmovel with more than one register;
+	     wait for fmoveml.  */
+	  if (*d == '\0')
+	    {
+	      for (d = opc->args; *d; d += 2)
+		{
+		  if (d[0] == 's' && d[1] == '8')
+		    {
+		      val = fetch_arg (buffer, d[1], 3, info);
+		      if ((val & (val - 1)) != 0)
+			break;
+		    }
+		}
+	    }
 
-static void
-print_base (int regno, bfd_vma disp, disassemble_info *info)
-{
-  if (regno == -1)
-    {
-      (*info->fprintf_func) (info->stream, "%%pc@(");
-      (*info->print_address_func) (disp, info);
+	  if (*d == '\0')
+	    if ((val = match_insn_m68k (memaddr, info, opc, & priv)))
+	      return val;
+	}
     }
-  else
-    {
-      char buf[50];
-
-      if (regno == -2)
-	(*info->fprintf_func) (info->stream, "@(");
-      else if (regno == -3)
-	(*info->fprintf_func) (info->stream, "%%zpc@(");
-      else
-	(*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]);
 
-      sprintf_vma (buf, disp);
-      (*info->fprintf_func) (info->stream, "%s", buf);
-    }
+  /* Handle undefined instructions.  */
+  info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]);
+  return 2;
 }
diff --git a/opcodes/m88k-dis.c b/opcodes/m88k-dis.c
index e3950cd..b60462e 100644
--- a/opcodes/m88k-dis.c
+++ b/opcodes/m88k-dis.c
@@ -1,24 +1,25 @@
 /* Print instructions for the Motorola 88000, for GDB and GNU Binutils.
    Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1993, 1998, 2000, 2001,
-   2002 Free Software Foundation, Inc.
+   2002, 2005 Free Software Foundation, Inc.
    Contributed by Data General Corporation, November 1989.
    Partially derived from an earlier printcmd.c.
 
-This file is part of GDB and the GNU Binutils.
+   This file is part of GDB and the GNU Binutils.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include "sysdep.h"
 #include "dis-asm.h"
@@ -26,14 +27,16 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 #include "opintl.h"
 #include "libiberty.h"
 
-typedef struct HASHTAB {
+typedef struct HASHTAB
+{
   const INSTAB	 *instr;
   struct HASHTAB *next;
 } HASHTAB;
 
 /* Opcode     Mnemonic       Op 1 Spec     Op 2 Spec    Op 3 Spec         Simflags             Next  */
 
-const INSTAB  instructions[] = {
+const INSTAB  instructions[] =
+{
   {0xf400c800,"jsr         ",{0,5,REG}   ,NO_OPERAND      ,NO_OPERAND   , {2,2,NA,JSR ,          0,0,1,0,0,0,0,1,0,0,0,0} },
   {0xf400cc00,"jsr.n       ",{0,5,REG}   ,NO_OPERAND      ,NO_OPERAND   , {1,1,NA,JSR ,          0,0,1,0,0,0,1,1,0,0,0,0} },
   {0xf400c000,"jmp         ",{0,5,REG}   ,NO_OPERAND      ,NO_OPERAND   , {2,2,NA,JMP ,          0,0,1,0,0,0,0,1,0,0,0,0} },
@@ -517,134 +520,64 @@ const INSTAB  instructions[] = {
 };
 
 HASHTAB  *hashtable[HASHVAL] = {0};
-
-static int
-m88kdis PARAMS ((bfd_vma, unsigned long, struct disassemble_info *));
-
-static void
-printop PARAMS ((struct disassemble_info *, const OPSPEC *, unsigned long, bfd_vma, int));
-
-static void
-init_disasm PARAMS ((void));
 
 
-/* Disassemble an M88000 instruction at `memaddr'.  */
+/* Initialize the disassembler instruction table.
+  
+   Initialize the hash table and instruction table for the
+   disassembler.  This should be called once before the first call to
+   disasm().  */
 
-int
-print_insn_m88k (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
-{
-  bfd_byte buffer[4];
-  int status;
-
-  /* Instruction addresses may have low two bits set. Clear them.  */
-  memaddr &=~ (bfd_vma) 3;
-
-  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
-  if (status != 0)
-    {
-      (*info->memory_error_func) (status, memaddr, info);
-      return -1;
-    }
-
-  return m88kdis (memaddr, bfd_getb32 (buffer), info);
-}
-
-/*
- * Disassemble the instruction in `instruction'.
- * `pc' should be the address of this instruction, it will be used to
- * print the target address if this is a relative jump or call the
- * disassembled instruction is written to `info'.
- *
- * The function returns the length of this instruction in bytes.
- */
-
-static int
-m88kdis (pc, instruction, info)
-     bfd_vma pc;
-     unsigned long instruction;
-     struct disassemble_info *info;
+static void
+init_disasm (void)
 {
-  static int ihashtab_initialized = 0;
-  unsigned int opcode;
-  const HASHTAB *entry_ptr;
-  int opmask;
-  unsigned int class;
-
-  if (! ihashtab_initialized)
-    {
-      init_disasm ();
-      ihashtab_initialized = 1;
-    }
+  unsigned int hashvalue, hashsize;
+  struct HASHTAB *hashentries;
+  unsigned int i;
 
-  /* Create the appropriate mask to isolate the opcode.  */
-  opmask = DEFMASK;
-  class = instruction & DEFMASK;
-  if ((class >= SFU0) && (class <= SFU7))
-    {
-      if (instruction < SFU1)
-	opmask = CTRLMASK;
-      else
-	opmask = SFUMASK;
-    }
-  else if (class == RRR)
-    opmask = RRRMASK;
-  else if (class == RRI10)
-    opmask = RRI10MASK;
+  hashsize = sizeof (instructions) / sizeof (INSTAB);
 
-  /* Isolate the opcode.  */
-  opcode = instruction & opmask;
+  hashentries = xmalloc (hashsize * sizeof (struct HASHTAB));
 
-  /* Search the hash table with the isolated opcode.  */
-  for (entry_ptr = hashtable[opcode % HASHVAL];
-       (entry_ptr != NULL) && (entry_ptr->instr->opcode != opcode);
-       entry_ptr = entry_ptr->next)
-    ;
+  for (i = 0; i < HASHVAL; i++)
+    hashtable[i] = NULL;
 
-  if (entry_ptr == NULL)
-    (*info->fprintf_func) (info->stream, "word\t%08x", instruction);
-  else
+  for (i = 0; i < hashsize; i++)
     {
-      (*info->fprintf_func) (info->stream, "%s", entry_ptr->instr->mnemonic);
-      printop (info, &(entry_ptr->instr->op1), instruction, pc, 1);
-      printop (info, &(entry_ptr->instr->op2), instruction, pc, 0);
-      printop (info, &(entry_ptr->instr->op3), instruction, pc, 0);
+      hashvalue = (instructions[i].opcode) % HASHVAL;
+      hashentries[i].instr = &instructions[i];
+      hashentries[i].next = hashtable[hashvalue];
+      hashtable[hashvalue] = &hashentries[i];
     }
-
-  return 4;
 }
-
-/*
- * Decode an Operand of an instruction.
- *
- * This function formats and writes an operand of an instruction to
- * info based on the operand specification.  When the `first' flag is
- * set this is the first operand of an instruction.  Undefined operand
- * types cause a <dis error> message.
- *
- * Parameters:
- *  disassemble_info	where the operand may be printed
- *  OPSPEC  *opptr      pointer to an operand specification
- *  UINT    inst        instruction from which operand is extracted
- *  UINT    pc		pc of instruction; used for pc-relative disp.
- *  int     first       flag which if nonzero indicates the first
- *                      operand of an instruction
- *
- * The operand specified is extracted from the instruction and is
- * written to buf in the format specified. The operand is preceded by
- * a comma if it is not the first operand of an instruction and it is
- * not a register indirect form.  Registers are preceded by 'r' and
- * hex values by '0x'.
- */
+ 
+/* Decode an Operand of an instruction.
+  
+   This function formats and writes an operand of an instruction to
+   info based on the operand specification.  When the `first' flag is
+   set this is the first operand of an instruction.  Undefined operand
+   types cause a <dis error> message.
+  
+   Parameters:
+    disassemble_info	where the operand may be printed
+    OPSPEC  *opptr      pointer to an operand specification
+    UINT    inst        instruction from which operand is extracted
+    UINT    pc		pc of instruction; used for pc-relative disp.
+    int     first       flag which if nonzero indicates the first
+                        operand of an instruction
+  
+   The operand specified is extracted from the instruction and is
+   written to buf in the format specified. The operand is preceded by
+   a comma if it is not the first operand of an instruction and it is
+   not a register indirect form.  Registers are preceded by 'r' and
+   hex values by '0x'.  */
 
 static void
-printop (info, opptr, inst, pc, first)
-     struct disassemble_info *info;
-     const OPSPEC *opptr;
-     unsigned long inst;
-     bfd_vma pc;
-     int first;
+printop (struct disassemble_info *info,
+	 const OPSPEC *opptr,
+	 unsigned long inst,
+	 bfd_vma pc,
+	 int first)
 {
   int extracted_field;
   char *cond_mask_sym;
@@ -747,34 +680,84 @@ printop (info, opptr, inst, pc, first)
     }
 }
 
-/*
- * Initialize the disassembler instruction table.
- *
- * Initialize the hash table and instruction table for the
- * disassembler.  This should be called once before the first call to
- * disasm().
- */
+/* Disassemble the instruction in `instruction'.
+   `pc' should be the address of this instruction, it will be used to
+   print the target address if this is a relative jump or call the
+   disassembled instruction is written to `info'.
+  
+   The function returns the length of this instruction in bytes.  */
 
-static void
-init_disasm ()
+static int
+m88kdis (bfd_vma pc,
+	 unsigned long instruction,
+	 struct disassemble_info *info)
 {
-  unsigned int hashvalue, hashsize;
-  struct HASHTAB *hashentries;
-  unsigned int i;
+  static int ihashtab_initialized = 0;
+  unsigned int opcode;
+  const HASHTAB *entry_ptr;
+  int opmask;
+  unsigned int class;
 
-  hashsize = sizeof (instructions) / sizeof (INSTAB);
+  if (! ihashtab_initialized)
+    {
+      init_disasm ();
+      ihashtab_initialized = 1;
+    }
 
-  hashentries = (struct HASHTAB *) xmalloc (hashsize * sizeof (struct HASHTAB));
+  /* Create the appropriate mask to isolate the opcode.  */
+  opmask = DEFMASK;
+  class = instruction & DEFMASK;
+  if ((class >= SFU0) && (class <= SFU7))
+    {
+      if (instruction < SFU1)
+	opmask = CTRLMASK;
+      else
+	opmask = SFUMASK;
+    }
+  else if (class == RRR)
+    opmask = RRRMASK;
+  else if (class == RRI10)
+    opmask = RRI10MASK;
 
-  for (i = 0; i < HASHVAL; i++)
-    hashtable[i] = NULL;
+  /* Isolate the opcode.  */
+  opcode = instruction & opmask;
 
-  for (i = 0; i < hashsize; i++)
+  /* Search the hash table with the isolated opcode.  */
+  for (entry_ptr = hashtable[opcode % HASHVAL];
+       (entry_ptr != NULL) && (entry_ptr->instr->opcode != opcode);
+       entry_ptr = entry_ptr->next)
+    ;
+
+  if (entry_ptr == NULL)
+    (*info->fprintf_func) (info->stream, "word\t%08x", instruction);
+  else
     {
-      hashvalue = (instructions[i].opcode) % HASHVAL;
-      hashentries[i].instr = &instructions[i];
-      hashentries[i].next = hashtable[hashvalue];
-      hashtable[hashvalue] = &hashentries[i];
+      (*info->fprintf_func) (info->stream, "%s", entry_ptr->instr->mnemonic);
+      printop (info, &(entry_ptr->instr->op1), instruction, pc, 1);
+      printop (info, &(entry_ptr->instr->op2), instruction, pc, 0);
+      printop (info, &(entry_ptr->instr->op3), instruction, pc, 0);
     }
+
+  return 4;
+}
+
+/* Disassemble an M88000 instruction at `memaddr'.  */
+
+int
+print_insn_m88k (bfd_vma memaddr, struct disassemble_info *info)
+{
+  bfd_byte buffer[4];
+  int status;
+
+  /* Instruction addresses may have low two bits set. Clear them.  */
+  memaddr &=~ (bfd_vma) 3;
+
+  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, memaddr, info);
+      return -1;
+    }
+
+  return m88kdis (memaddr, bfd_getb32 (buffer), info);
 }
- 
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index a09a7e9..bc3a03b 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -4,21 +4,22 @@
    Free Software Foundation, Inc.
    Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
 
-This file is part of GDB, GAS, and the GNU binutils.
+   This file is part of GDB, GAS, and the GNU binutils.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include "sysdep.h"
 #include "dis-asm.h"
@@ -40,96 +41,88 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 /* Mips instructions are at maximum this many bytes long.  */
 #define INSNLEN 4
 
-static void set_default_mips_dis_options
-  PARAMS ((struct disassemble_info *));
-static void parse_mips_dis_option
-  PARAMS ((const char *, unsigned int));
-static void parse_mips_dis_options
-  PARAMS ((const char *));
-static int _print_insn_mips
-  PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian));
-static int print_insn_mips
-  PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *));
-static void print_insn_args
-  PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *));
-static int print_insn_mips16
-  PARAMS ((bfd_vma, struct disassemble_info *));
-static int is_newabi
-  PARAMS ((Elf_Internal_Ehdr *));
-static void print_mips16_insn_arg
-  PARAMS ((int, const struct mips_opcode *, int, bfd_boolean, int, bfd_vma,
-	   struct disassemble_info *));
 
 /* FIXME: These should be shared with gdb somehow.  */
 
-struct mips_cp0sel_name {
-	unsigned int cp0reg;
-	unsigned int sel;
-	const char * const name;
+struct mips_cp0sel_name
+{
+  unsigned int cp0reg;
+  unsigned int sel;
+  const char * const name;
 };
 
 /* The mips16 register names.  */
-static const char * const mips16_reg_names[] = {
+static const char * const mips16_reg_names[] =
+{
   "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
 };
 
-static const char * const mips_gpr_names_numeric[32] = {
+static const char * const mips_gpr_names_numeric[32] =
+{
   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
 };
 
-static const char * const mips_gpr_names_oldabi[32] = {
+static const char * const mips_gpr_names_oldabi[32] =
+{
   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
   "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",
   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
 };
 
-static const char * const mips_gpr_names_newabi[32] = {
+static const char * const mips_gpr_names_newabi[32] =
+{
   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
   "a4",   "a5",   "a6",   "a7",   "t0",   "t1",   "t2",   "t3",
   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
 };
 
-static const char * const mips_fpr_names_numeric[32] = {
+static const char * const mips_fpr_names_numeric[32] =
+{
   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
 };
 
-static const char * const mips_fpr_names_32[32] = {
+static const char * const mips_fpr_names_32[32] =
+{
   "fv0",  "fv0f", "fv1",  "fv1f", "ft0",  "ft0f", "ft1",  "ft1f",
   "ft2",  "ft2f", "ft3",  "ft3f", "fa0",  "fa0f", "fa1",  "fa1f",
   "ft4",  "ft4f", "ft5",  "ft5f", "fs0",  "fs0f", "fs1",  "fs1f",
   "fs2",  "fs2f", "fs3",  "fs3f", "fs4",  "fs4f", "fs5",  "fs5f"
 };
 
-static const char * const mips_fpr_names_n32[32] = {
+static const char * const mips_fpr_names_n32[32] =
+{
   "fv0",  "ft14", "fv1",  "ft15", "ft0",  "ft1",  "ft2",  "ft3",
   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
   "fa4",  "fa5",  "fa6",  "fa7",  "fs0",  "ft8",  "fs1",  "ft9",
   "fs2",  "ft10", "fs3",  "ft11", "fs4",  "ft12", "fs5",  "ft13"
 };
 
-static const char * const mips_fpr_names_64[32] = {
+static const char * const mips_fpr_names_64[32] =
+{
   "fv0",  "ft12", "fv1",  "ft13", "ft0",  "ft1",  "ft2",  "ft3",
   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
   "fa4",  "fa5",  "fa6",  "fa7",  "ft8",  "ft9",  "ft10", "ft11",
   "fs0",  "fs1",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7"
 };
 
-static const char * const mips_cp0_names_numeric[32] = {
+static const char * const mips_cp0_names_numeric[32] =
+{
   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
 };
 
-static const char * const mips_cp0_names_mips3264[32] = {
+static const char * const mips_cp0_names_mips3264[32] =
+{
   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
@@ -140,7 +133,8 @@ static const char * const mips_cp0_names_mips3264[32] = {
   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
 };
 
-static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = {
+static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
+{
   { 16, 1, "c0_config1"		},
   { 16, 2, "c0_config2"		},
   { 16, 3, "c0_config3"		},
@@ -172,7 +166,8 @@ static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = {
   { 29, 1, "c0_datahi"		}
 };
 
-static const char * const mips_cp0_names_mips3264r2[32] = {
+static const char * const mips_cp0_names_mips3264r2[32] =
+{
   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
   "c0_context",   "c0_pagemask",  "c0_wired",     "c0_hwrena",
   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
@@ -183,7 +178,8 @@ static const char * const mips_cp0_names_mips3264r2[32] = {
   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
 };
 
-static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = {
+static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
+{
   {  4, 1, "c0_contextconfig"	},
   {  5, 1, "c0_pagegrain"	},
   { 12, 1, "c0_intctl"		},
@@ -238,7 +234,8 @@ static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = {
 };
 
 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods.  */
-static const char * const mips_cp0_names_sb1[32] = {
+static const char * const mips_cp0_names_sb1[32] =
+{
   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
@@ -249,7 +246,8 @@ static const char * const mips_cp0_names_sb1[32] = {
   "c0_taglo_i",   "c0_taghi_i",   "c0_errorepc",  "c0_desave",
 };
 
-static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = {
+static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
+{
   { 16, 1, "c0_config1"		},
   { 18, 1, "c0_watchlo,1"	},
   { 19, 1, "c0_watchhi,1"	},
@@ -273,14 +271,16 @@ static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = {
   { 29, 3, "c0_datahi_d"	},
 };
 
-static const char * const mips_hwr_names_numeric[32] = {
+static const char * const mips_hwr_names_numeric[32] =
+{
   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
 };
 
-static const char * const mips_hwr_names_mips3264r2[32] = {
+static const char * const mips_hwr_names_mips3264r2[32] =
+{
   "hwr_cpunum",   "hwr_synci_step", "hwr_cc",     "hwr_ccres",
   "$4",          "$5",            "$6",           "$7",
   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
@@ -288,20 +288,23 @@ static const char * const mips_hwr_names_mips3264r2[32] = {
   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
 };
 
-struct mips_abi_choice {
-  const char *name;
+struct mips_abi_choice
+{
+  const char * name;
   const char * const *gpr_names;
   const char * const *fpr_names;
 };
 
-struct mips_abi_choice mips_abi_choices[] = {
+struct mips_abi_choice mips_abi_choices[] =
+{
   { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
   { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
   { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
   { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
 };
 
-struct mips_arch_choice {
+struct mips_arch_choice
+{
   const char *name;
   int bfd_mach_valid;
   unsigned long bfd_mach;
@@ -313,7 +316,8 @@ struct mips_arch_choice {
   const char * const *hwr_names;
 };
 
-const struct mips_arch_choice mips_arch_choices[] = {
+const struct mips_arch_choice mips_arch_choices[] =
+{
   { "numeric",	0, 0, 0, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
 
@@ -415,55 +419,38 @@ static int mips_cp0sel_names_len;
 static const char * const *mips_hwr_names;
 
 /* Other options */
-static int no_aliases;	/* If set disassemble as most general inst. */
-
-static const struct mips_abi_choice *choose_abi_by_name
-  PARAMS ((const char *, unsigned int));
-static const struct mips_arch_choice *choose_arch_by_name
-  PARAMS ((const char *, unsigned int));
-static const struct mips_arch_choice *choose_arch_by_number
-  PARAMS ((unsigned long));
-static const struct mips_cp0sel_name *lookup_mips_cp0sel_name
-  PARAMS ((const struct mips_cp0sel_name *, unsigned int, unsigned int,
-	   unsigned int));
+static int no_aliases;	/* If set disassemble as most general inst.  */
 
 static const struct mips_abi_choice *
-choose_abi_by_name (name, namelen)
-     const char *name;
-     unsigned int namelen;
+choose_abi_by_name (const char *name, unsigned int namelen)
 {
   const struct mips_abi_choice *c;
   unsigned int i;
 
   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
-    {
-      if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
-	  && strlen (mips_abi_choices[i].name) == namelen)
-	c = &mips_abi_choices[i];
-    }
+    if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
+	&& strlen (mips_abi_choices[i].name) == namelen)
+      c = &mips_abi_choices[i];
+
   return c;
 }
 
 static const struct mips_arch_choice *
-choose_arch_by_name (name, namelen)
-     const char *name;
-     unsigned int namelen;
+choose_arch_by_name (const char *name, unsigned int namelen)
 {
   const struct mips_arch_choice *c = NULL;
   unsigned int i;
 
   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
-    {
-      if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
-	  && strlen (mips_arch_choices[i].name) == namelen)
-	c = &mips_arch_choices[i];
-    }
+    if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
+	&& strlen (mips_arch_choices[i].name) == namelen)
+      c = &mips_arch_choices[i];
+
   return c;
 }
 
 static const struct mips_arch_choice *
-choose_arch_by_number (mach)
-     unsigned long mach;
+choose_arch_by_number (unsigned long mach)
 {
   static unsigned long hint_bfd_mach;
   static const struct mips_arch_choice *hint_arch_choice;
@@ -490,9 +477,24 @@ choose_arch_by_number (mach)
   return c;
 }
 
-void
-set_default_mips_dis_options (info)
-     struct disassemble_info *info;
+/* Check if the object uses NewABI conventions.  */
+
+static int
+is_newabi (Elf_Internal_Ehdr *header)
+{
+  /* There are no old-style ABIs which use 64-bit ELF.  */
+  if (header->e_ident[EI_CLASS] == ELFCLASS64)
+    return 1;
+
+  /* If a 32-bit ELF file, n32 is a new-style ABI.  */
+  if ((header->e_flags & EF_MIPS_ABI2) != 0)
+    return 1;
+
+  return 0;
+}
+
+static void
+set_default_mips_dis_options (struct disassemble_info *info)
 {
   const struct mips_arch_choice *chosen_arch;
 
@@ -538,10 +540,8 @@ set_default_mips_dis_options (info)
 #endif
 }
 
-void
-parse_mips_dis_option (option, len)
-     const char *option;
-     unsigned int len;
+static void
+parse_mips_dis_option (const char *option, unsigned int len)
 {
   unsigned int i, optionlen, vallen;
   const char *val;
@@ -557,10 +557,9 @@ parse_mips_dis_option (option, len)
   
   /* Look for the = that delimits the end of the option name.  */
   for (i = 0; i < len; i++)
-    {
-      if (option[i] == '=')
-	break;
-    }
+    if (option[i] == '=')
+      break;
+
   if (i == 0)		/* Invalid option: no name before '='.  */
     return;
   if (i == len)		/* Invalid option: no '='.  */
@@ -572,8 +571,8 @@ parse_mips_dis_option (option, len)
   val = option + (optionlen + 1);
   vallen = len - (optionlen + 1);
 
-  if (strncmp("gpr-names", option, optionlen) == 0
-      && strlen("gpr-names") == optionlen)
+  if (strncmp ("gpr-names", option, optionlen) == 0
+      && strlen ("gpr-names") == optionlen)
     {
       chosen_abi = choose_abi_by_name (val, vallen);
       if (chosen_abi != NULL)
@@ -581,8 +580,8 @@ parse_mips_dis_option (option, len)
       return;
     }
 
-  if (strncmp("fpr-names", option, optionlen) == 0
-      && strlen("fpr-names") == optionlen)
+  if (strncmp ("fpr-names", option, optionlen) == 0
+      && strlen ("fpr-names") == optionlen)
     {
       chosen_abi = choose_abi_by_name (val, vallen);
       if (chosen_abi != NULL)
@@ -590,8 +589,8 @@ parse_mips_dis_option (option, len)
       return;
     }
 
-  if (strncmp("cp0-names", option, optionlen) == 0
-      && strlen("cp0-names") == optionlen)
+  if (strncmp ("cp0-names", option, optionlen) == 0
+      && strlen ("cp0-names") == optionlen)
     {
       chosen_arch = choose_arch_by_name (val, vallen);
       if (chosen_arch != NULL)
@@ -603,8 +602,8 @@ parse_mips_dis_option (option, len)
       return;
     }
 
-  if (strncmp("hwr-names", option, optionlen) == 0
-      && strlen("hwr-names") == optionlen)
+  if (strncmp ("hwr-names", option, optionlen) == 0
+      && strlen ("hwr-names") == optionlen)
     {
       chosen_arch = choose_arch_by_name (val, vallen);
       if (chosen_arch != NULL)
@@ -612,8 +611,8 @@ parse_mips_dis_option (option, len)
       return;
     }
 
-  if (strncmp("reg-names", option, optionlen) == 0
-      && strlen("reg-names") == optionlen)
+  if (strncmp ("reg-names", option, optionlen) == 0
+      && strlen ("reg-names") == optionlen)
     {
       /* We check both ABI and ARCH here unconditionally, so
 	 that "numeric" will do the desirable thing: select
@@ -639,9 +638,8 @@ parse_mips_dis_option (option, len)
   /* Invalid option.  */
 }
 
-void
-parse_mips_dis_options (options)
-     const char *options;
+static void
+parse_mips_dis_options (const char *options)
 {
   const char *option_end;
 
@@ -671,9 +669,10 @@ parse_mips_dis_options (options)
 }
 
 static const struct mips_cp0sel_name *
-lookup_mips_cp0sel_name(names, len, cp0reg, sel)
-	const struct mips_cp0sel_name *names;
-	unsigned int len, cp0reg, sel;
+lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
+			 unsigned int len,
+			 unsigned int cp0reg,
+			 unsigned int sel)
 {
   unsigned int i;
 
@@ -686,11 +685,10 @@ lookup_mips_cp0sel_name(names, len, cp0reg, sel)
 /* Print insn arguments for 32/64-bit code.  */
 
 static void
-print_insn_args (d, l, pc, info)
-     const char *d;
-     register unsigned long int l;
-     bfd_vma pc;
-     struct disassemble_info *info;
+print_insn_args (const char *d,
+		 register unsigned long int l,
+		 bfd_vma pc,
+		 struct disassemble_info *info)
 {
   int op, delta;
   unsigned int lsb, msb, msbd;
@@ -992,9 +990,11 @@ print_insn_args (d, l, pc, info)
 	case 'Q':
 	  {
 	    unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
+
 	    if ((vsel & 0x10) == 0)
 	      {
 		int fmt;
+
 		vsel &= 0x0f;
 		for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
 		  if ((vsel & 1) == 0)
@@ -1041,35 +1041,17 @@ print_insn_args (d, l, pc, info)
     }
 }
 
-/* Check if the object uses NewABI conventions.  */
-
-static int
-is_newabi (header)
-     Elf_Internal_Ehdr *header;
-{
-  /* There are no old-style ABIs which use 64-bit ELF.  */
-  if (header->e_ident[EI_CLASS] == ELFCLASS64)
-    return 1;
-
-  /* If a 32-bit ELF file, n32 is a new-style ABI.  */
-  if ((header->e_flags & EF_MIPS_ABI2) != 0)
-    return 1;
-
-  return 0;
-}
-
 /* Print the mips instruction at address MEMADDR in debugged memory,
    on using INFO.  Returns length of the instruction, in bytes, which is
    always INSNLEN.  BIGENDIAN must be 1 if this is big-endian code, 0 if
    this is little-endian code.  */
 
 static int
-print_insn_mips (memaddr, word, info)
-     bfd_vma memaddr;
-     unsigned long int word;
-     struct disassemble_info *info;
+print_insn_mips (bfd_vma memaddr,
+		 unsigned long int word,
+		 struct disassemble_info *info)
 {
-  register const struct mips_opcode *op;
+  const struct mips_opcode *op;
   static bfd_boolean init = 0;
   static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
 
@@ -1114,7 +1096,7 @@ print_insn_mips (memaddr, word, info)
 	      && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
 	      && (word & op->mask) == op->match)
 	    {
-	      register const char *d;
+	      const char *d;
 
 	      /* We always allow to disassemble the jalx instruction.  */
 	      if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
@@ -1163,244 +1145,16 @@ print_insn_mips (memaddr, word, info)
   return INSNLEN;
 }
 
-/* In an environment where we do not know the symbol type of the
-   instruction we are forced to assume that the low order bit of the
-   instructions' address may mark it as a mips16 instruction.  If we
-   are single stepping, or the pc is within the disassembled function,
-   this works.  Otherwise, we need a clue.  Sometimes.  */
-
-static int
-_print_insn_mips (memaddr, info, endianness)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
-     enum bfd_endian endianness;
-{
-  bfd_byte buffer[INSNLEN];
-  int status;
-
-  set_default_mips_dis_options (info);
-  parse_mips_dis_options (info->disassembler_options);
-
-#if 1
-  /* FIXME: If odd address, this is CLEARLY a mips 16 instruction.  */
-  /* Only a few tools will work this way.  */
-  if (memaddr & 0x01)
-    return print_insn_mips16 (memaddr, info);
-#endif
-
-#if SYMTAB_AVAILABLE
-  if (info->mach == bfd_mach_mips16
-      || (info->flavour == bfd_target_elf_flavour
-	  && info->symbols != NULL
-	  && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
-	      == STO_MIPS16)))
-    return print_insn_mips16 (memaddr, info);
-#endif
-
-  status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
-  if (status == 0)
-    {
-      unsigned long insn;
-
-      if (endianness == BFD_ENDIAN_BIG)
-	insn = (unsigned long) bfd_getb32 (buffer);
-      else
-	insn = (unsigned long) bfd_getl32 (buffer);
-
-      return print_insn_mips (memaddr, insn, info);
-    }
-  else
-    {
-      (*info->memory_error_func) (status, memaddr, info);
-      return -1;
-    }
-}
-
-int
-print_insn_big_mips (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
-{
-  return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
-}
-
-int
-print_insn_little_mips (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
-{
-  return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
-}
-
-/* Disassemble mips16 instructions.  */
-
-static int
-print_insn_mips16 (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
-{
-  int status;
-  bfd_byte buffer[2];
-  int length;
-  int insn;
-  bfd_boolean use_extend;
-  int extend = 0;
-  const struct mips_opcode *op, *opend;
-
-  info->bytes_per_chunk = 2;
-  info->display_endian = info->endian;
-  info->insn_info_valid = 1;
-  info->branch_delay_insns = 0;
-  info->data_size = 0;
-  info->insn_type = dis_nonbranch;
-  info->target = 0;
-  info->target2 = 0;
-
-  status = (*info->read_memory_func) (memaddr, buffer, 2, info);
-  if (status != 0)
-    {
-      (*info->memory_error_func) (status, memaddr, info);
-      return -1;
-    }
-
-  length = 2;
-
-  if (info->endian == BFD_ENDIAN_BIG)
-    insn = bfd_getb16 (buffer);
-  else
-    insn = bfd_getl16 (buffer);
-
-  /* Handle the extend opcode specially.  */
-  use_extend = FALSE;
-  if ((insn & 0xf800) == 0xf000)
-    {
-      use_extend = TRUE;
-      extend = insn & 0x7ff;
-
-      memaddr += 2;
-
-      status = (*info->read_memory_func) (memaddr, buffer, 2, info);
-      if (status != 0)
-	{
-	  (*info->fprintf_func) (info->stream, "extend 0x%x",
-				 (unsigned int) extend);
-	  (*info->memory_error_func) (status, memaddr, info);
-	  return -1;
-	}
-
-      if (info->endian == BFD_ENDIAN_BIG)
-	insn = bfd_getb16 (buffer);
-      else
-	insn = bfd_getl16 (buffer);
-
-      /* Check for an extend opcode followed by an extend opcode.  */
-      if ((insn & 0xf800) == 0xf000)
-	{
-	  (*info->fprintf_func) (info->stream, "extend 0x%x",
-				 (unsigned int) extend);
-	  info->insn_type = dis_noninsn;
-	  return length;
-	}
-
-      length += 2;
-    }
-
-  /* FIXME: Should probably use a hash table on the major opcode here.  */
-
-  opend = mips16_opcodes + bfd_mips16_num_opcodes;
-  for (op = mips16_opcodes; op < opend; op++)
-    {
-      if (op->pinfo != INSN_MACRO
-	  && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
-	  && (insn & op->mask) == op->match)
-	{
-	  const char *s;
-
-	  if (strchr (op->args, 'a') != NULL)
-	    {
-	      if (use_extend)
-		{
-		  (*info->fprintf_func) (info->stream, "extend 0x%x",
-					 (unsigned int) extend);
-		  info->insn_type = dis_noninsn;
-		  return length - 2;
-		}
-
-	      use_extend = FALSE;
-
-	      memaddr += 2;
-
-	      status = (*info->read_memory_func) (memaddr, buffer, 2,
-						  info);
-	      if (status == 0)
-		{
-		  use_extend = TRUE;
-		  if (info->endian == BFD_ENDIAN_BIG)
-		    extend = bfd_getb16 (buffer);
-		  else
-		    extend = bfd_getl16 (buffer);
-		  length += 2;
-		}
-	    }
-
-	  (*info->fprintf_func) (info->stream, "%s", op->name);
-	  if (op->args[0] != '\0')
-	    (*info->fprintf_func) (info->stream, "\t");
-
-	  for (s = op->args; *s != '\0'; s++)
-	    {
-	      if (*s == ','
-		  && s[1] == 'w'
-		  && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
-		      == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
-		{
-		  /* Skip the register and the comma.  */
-		  ++s;
-		  continue;
-		}
-	      if (*s == ','
-		  && s[1] == 'v'
-		  && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
-		      == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
-		{
-		  /* Skip the register and the comma.  */
-		  ++s;
-		  continue;
-		}
-	      print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
-				     info);
-	    }
-
-	  if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
-	    {
-	      info->branch_delay_insns = 1;
-	      if (info->insn_type != dis_jsr)
-		info->insn_type = dis_branch;
-	    }
-
-	  return length;
-	}
-    }
-
-  if (use_extend)
-    (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
-  (*info->fprintf_func) (info->stream, "0x%x", insn);
-  info->insn_type = dis_noninsn;
-
-  return length;
-}
-
 /* Disassemble an operand for a mips16 instruction.  */
 
 static void
-print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
-     char type;
-     const struct mips_opcode *op;
-     int l;
-     bfd_boolean use_extend;
-     int extend;
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_mips16_insn_arg (char type,
+		       const struct mips_opcode *op,
+		       int l,
+		       bfd_boolean use_extend,
+		       int extend,
+		       bfd_vma memaddr,
+		       struct disassemble_info *info)
 {
   switch (type)
     {
@@ -1796,9 +1550,228 @@ print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
     }
 }
 
+/* Disassemble mips16 instructions.  */
+
+static int
+print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
+{
+  int status;
+  bfd_byte buffer[2];
+  int length;
+  int insn;
+  bfd_boolean use_extend;
+  int extend = 0;
+  const struct mips_opcode *op, *opend;
+
+  info->bytes_per_chunk = 2;
+  info->display_endian = info->endian;
+  info->insn_info_valid = 1;
+  info->branch_delay_insns = 0;
+  info->data_size = 0;
+  info->insn_type = dis_nonbranch;
+  info->target = 0;
+  info->target2 = 0;
+
+  status = (*info->read_memory_func) (memaddr, buffer, 2, info);
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, memaddr, info);
+      return -1;
+    }
+
+  length = 2;
+
+  if (info->endian == BFD_ENDIAN_BIG)
+    insn = bfd_getb16 (buffer);
+  else
+    insn = bfd_getl16 (buffer);
+
+  /* Handle the extend opcode specially.  */
+  use_extend = FALSE;
+  if ((insn & 0xf800) == 0xf000)
+    {
+      use_extend = TRUE;
+      extend = insn & 0x7ff;
+
+      memaddr += 2;
+
+      status = (*info->read_memory_func) (memaddr, buffer, 2, info);
+      if (status != 0)
+	{
+	  (*info->fprintf_func) (info->stream, "extend 0x%x",
+				 (unsigned int) extend);
+	  (*info->memory_error_func) (status, memaddr, info);
+	  return -1;
+	}
+
+      if (info->endian == BFD_ENDIAN_BIG)
+	insn = bfd_getb16 (buffer);
+      else
+	insn = bfd_getl16 (buffer);
+
+      /* Check for an extend opcode followed by an extend opcode.  */
+      if ((insn & 0xf800) == 0xf000)
+	{
+	  (*info->fprintf_func) (info->stream, "extend 0x%x",
+				 (unsigned int) extend);
+	  info->insn_type = dis_noninsn;
+	  return length;
+	}
+
+      length += 2;
+    }
+
+  /* FIXME: Should probably use a hash table on the major opcode here.  */
+
+  opend = mips16_opcodes + bfd_mips16_num_opcodes;
+  for (op = mips16_opcodes; op < opend; op++)
+    {
+      if (op->pinfo != INSN_MACRO
+	  && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
+	  && (insn & op->mask) == op->match)
+	{
+	  const char *s;
+
+	  if (strchr (op->args, 'a') != NULL)
+	    {
+	      if (use_extend)
+		{
+		  (*info->fprintf_func) (info->stream, "extend 0x%x",
+					 (unsigned int) extend);
+		  info->insn_type = dis_noninsn;
+		  return length - 2;
+		}
+
+	      use_extend = FALSE;
+
+	      memaddr += 2;
+
+	      status = (*info->read_memory_func) (memaddr, buffer, 2,
+						  info);
+	      if (status == 0)
+		{
+		  use_extend = TRUE;
+		  if (info->endian == BFD_ENDIAN_BIG)
+		    extend = bfd_getb16 (buffer);
+		  else
+		    extend = bfd_getl16 (buffer);
+		  length += 2;
+		}
+	    }
+
+	  (*info->fprintf_func) (info->stream, "%s", op->name);
+	  if (op->args[0] != '\0')
+	    (*info->fprintf_func) (info->stream, "\t");
+
+	  for (s = op->args; *s != '\0'; s++)
+	    {
+	      if (*s == ','
+		  && s[1] == 'w'
+		  && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
+		      == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
+		{
+		  /* Skip the register and the comma.  */
+		  ++s;
+		  continue;
+		}
+	      if (*s == ','
+		  && s[1] == 'v'
+		  && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
+		      == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
+		{
+		  /* Skip the register and the comma.  */
+		  ++s;
+		  continue;
+		}
+	      print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
+				     info);
+	    }
+
+	  if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
+	    {
+	      info->branch_delay_insns = 1;
+	      if (info->insn_type != dis_jsr)
+		info->insn_type = dis_branch;
+	    }
+
+	  return length;
+	}
+    }
+
+  if (use_extend)
+    (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
+  (*info->fprintf_func) (info->stream, "0x%x", insn);
+  info->insn_type = dis_noninsn;
+
+  return length;
+}
+
+/* In an environment where we do not know the symbol type of the
+   instruction we are forced to assume that the low order bit of the
+   instructions' address may mark it as a mips16 instruction.  If we
+   are single stepping, or the pc is within the disassembled function,
+   this works.  Otherwise, we need a clue.  Sometimes.  */
+
+static int
+_print_insn_mips (bfd_vma memaddr,
+		  struct disassemble_info *info,
+		  enum bfd_endian endianness)
+{
+  bfd_byte buffer[INSNLEN];
+  int status;
+
+  set_default_mips_dis_options (info);
+  parse_mips_dis_options (info->disassembler_options);
+
+#if 1
+  /* FIXME: If odd address, this is CLEARLY a mips 16 instruction.  */
+  /* Only a few tools will work this way.  */
+  if (memaddr & 0x01)
+    return print_insn_mips16 (memaddr, info);
+#endif
+
+#if SYMTAB_AVAILABLE
+  if (info->mach == bfd_mach_mips16
+      || (info->flavour == bfd_target_elf_flavour
+	  && info->symbols != NULL
+	  && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
+	      == STO_MIPS16)))
+    return print_insn_mips16 (memaddr, info);
+#endif
+
+  status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
+  if (status == 0)
+    {
+      unsigned long insn;
+
+      if (endianness == BFD_ENDIAN_BIG)
+	insn = (unsigned long) bfd_getb32 (buffer);
+      else
+	insn = (unsigned long) bfd_getl32 (buffer);
+
+      return print_insn_mips (memaddr, insn, info);
+    }
+  else
+    {
+      (*info->memory_error_func) (status, memaddr, info);
+      return -1;
+    }
+}
+
+int
+print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
+{
+  return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
+}
+
+int
+print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
+{
+  return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
+}
+
 void
-print_mips_disassembler_options (stream)
-     FILE *stream;
+print_mips_disassembler_options (FILE *stream)
 {
   unsigned int i;
 
diff --git a/opcodes/mmix-dis.c b/opcodes/mmix-dis.c
index 73c7743..d723b6b 100644
--- a/opcodes/mmix-dis.c
+++ b/opcodes/mmix-dis.c
@@ -2,21 +2,22 @@
    Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
    Written by Hans-Peter Nilsson (hp@bitrange.com)
 
-This file is part of GDB and the GNU binutils.
+   This file is part of GDB and the GNU binutils.
 
-GDB and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version 2,
-or (at your option) any later version.
+   GDB and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 2,
+   or (at your option) any later version.
 
-GDB and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
-the GNU General Public License for more details.
+   GDB and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING.  If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include <string.h>
@@ -37,14 +38,14 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
    }						\
  while (0)
 
-#define FATAL_DEBUG								\
- do										\
-   {										\
-     fprintf (stderr,								\
-	      _("Internal: Non-debugged code (test-case missing): %s:%d"),	\
-	      __FILE__, __LINE__);						\
-     abort ();									\
-   }						\
+#define FATAL_DEBUG							\
+ do									\
+   {									\
+     fprintf (stderr,							\
+	      _("Internal: Non-debugged code (test-case missing): %s:%d"),\
+	      __FILE__, __LINE__);					\
+     abort ();								\
+   }									\
  while (0)
 
 #define ROUND_MODE(n)					\
@@ -66,17 +67,10 @@ struct mmix_dis_info
    char basic_reg_name[256][sizeof ("$255")];
  };
 
-static bfd_boolean initialize_mmix_dis_info
-  PARAMS ((struct disassemble_info *));
-static const struct mmix_opcode *get_opcode
-  PARAMS ((unsigned long));
-
-
 /* Initialize a target-specific array in INFO.  */
 
 static bfd_boolean
-initialize_mmix_dis_info (info)
-     struct disassemble_info *info;
+initialize_mmix_dis_info (struct disassemble_info *info)
 {
   struct mmix_dis_info *minfop = malloc (sizeof (struct mmix_dis_info));
   int i;
@@ -107,7 +101,8 @@ initialize_mmix_dis_info (info)
 	  long i;
 
 	  if (syms == NULL)
-	    { FATAL_DEBUG;
+	    {
+	      FATAL_DEBUG;
 	      free (minfop);
 	      return FALSE;
 	    }
@@ -138,7 +133,7 @@ initialize_mmix_dis_info (info)
   for (i = 0; mmix_spec_regs[i].name != NULL; i++)
     minfop->spec_reg_name[mmix_spec_regs[i].number] = mmix_spec_regs[i].name;
 
-  info->private_data = (PTR) minfop;
+  info->private_data = (void *) minfop;
   return TRUE;
 }
 
@@ -150,12 +145,12 @@ initialize_mmix_dis_info (info)
    "further entry" will just show that there was no other match.  */
 
 static const struct mmix_opcode *
-get_opcode (insn)
-     unsigned long insn;
+get_opcode (unsigned long insn)
 {
   static const struct mmix_opcode **opcodes = NULL;
   const struct mmix_opcode *opcodep = mmix_opcodes;
   unsigned int opcode_part = (insn >> 24) & 255;
+
   if (opcodes == NULL)
     opcodes = xcalloc (256, sizeof (struct mmix_opcode *));
 
@@ -213,6 +208,7 @@ get_opcode (insn)
 	case mmix_operands_roundregs:
 	  {
 	    int midbyte = (insn >> 8) & 255;
+
 	    if (midbyte <= 4)
 	      return opcodep;
 	  }
@@ -248,9 +244,7 @@ get_opcode (insn)
 /* The main disassembly function.  */
 
 int
-print_insn_mmix (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_mmix (bfd_vma memaddr, struct disassemble_info *info)
 {
   unsigned char buffer[4];
   unsigned long insn;
diff --git a/opcodes/ms1-asm.c b/opcodes/ms1-asm.c
index 0b65226..7647c1b 100644
--- a/opcodes/ms1-asm.c
+++ b/opcodes/ms1-asm.c
@@ -1,26 +1,27 @@
 /* Assembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-asm.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-asm.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -380,7 +381,7 @@ parse_type (CGEN_CPU_DESC cd,
 /* -- dis.c */
 
 const char * ms1_cgen_parse_operand
-  PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
 
 /* Main entry point for operand parsing.
 
@@ -396,11 +397,10 @@ const char * ms1_cgen_parse_operand
    the handlers.  */
 
 const char *
-ms1_cgen_parse_operand (cd, opindex, strp, fields)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     const char ** strp;
-     CGEN_FIELDS * fields;
+ms1_cgen_parse_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   const char ** strp,
+			   CGEN_FIELDS * fields)
 {
   const char * errmsg = NULL;
   /* Used by scalar operands that still need to be parsed.  */
@@ -565,8 +565,7 @@ cgen_parse_fn * const ms1_cgen_parse_handlers[] =
 };
 
 void
-ms1_cgen_init_asm (cd)
-     CGEN_CPU_DESC cd;
+ms1_cgen_init_asm (CGEN_CPU_DESC cd)
 {
   ms1_cgen_init_opcode_table (cd);
   ms1_cgen_init_ibld_table (cd);
@@ -949,30 +948,3 @@ ms1_cgen_assemble_insn (CGEN_CPU_DESC cd,
     return NULL;
   }
 }
-
-#if 0 /* This calls back to GAS which we can't do without care.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   This lets GAS parse registers for us.
-   ??? Interesting idea but not currently used.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   FIXME: Not currently used.  */
-
-void
-ms1_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
-{
-  CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
-  const CGEN_KEYWORD_ENTRY * ke;
-
-  while ((ke = cgen_keyword_search_next (& search)) != NULL)
-    {
-#if 0 /* Unnecessary, should be done in the search routine.  */
-      if (! ms1_cgen_opval_supported (ke))
-	continue;
-#endif
-      cgen_asm_record_register (cd, ke->name, ke->value);
-    }
-}
-
-#endif /* 0 */
diff --git a/opcodes/ms1-desc.c b/opcodes/ms1-desc.c
index 2108fd4..8428c6c 100644
--- a/opcodes/ms1-desc.c
+++ b/opcodes/ms1-desc.c
@@ -919,27 +919,23 @@ static const CGEN_IBASE ms1_cgen_insn_table[MAX_INSNS] =
 #undef A
 
 /* Initialize anything needed to be done once, before any cpu_open call.  */
-static void init_tables PARAMS ((void));
 
 static void
-init_tables ()
+init_tables (void)
 {
 }
 
-static const CGEN_MACH * lookup_mach_via_bfd_name
-  PARAMS ((const CGEN_MACH *, const char *));
-static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
-static void ms1_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
+static void build_hw_table      (CGEN_CPU_TABLE *);
+static void build_ifield_table  (CGEN_CPU_TABLE *);
+static void build_operand_table (CGEN_CPU_TABLE *);
+static void build_insn_table    (CGEN_CPU_TABLE *);
+static void ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *);
 
 /* Subroutine of ms1_cgen_cpu_open to look up a mach via its bfd name.  */
 
 static const CGEN_MACH *
-lookup_mach_via_bfd_name (table, name)
-     const CGEN_MACH *table;
-     const char *name;
+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
 {
   while (table->name)
     {
@@ -953,8 +949,7 @@ lookup_mach_via_bfd_name (table, name)
 /* Subroutine of ms1_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_hw_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_hw_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -980,8 +975,7 @@ build_hw_table (cd)
 /* Subroutine of ms1_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_ifield_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_ifield_table (CGEN_CPU_TABLE *cd)
 {
   cd->ifld_table = & ms1_cgen_ifld_table[0];
 }
@@ -989,8 +983,7 @@ build_ifield_table (cd)
 /* Subroutine of ms1_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_operand_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_operand_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -998,8 +991,7 @@ build_operand_table (cd)
   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
      However each entry is indexed by it's enum so there can be holes in
      the table.  */
-  const CGEN_OPERAND **selected =
-    (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
 
   cd->operand_table.init_entries = init;
   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@@ -1022,12 +1014,11 @@ build_operand_table (cd)
    operand elements to be in the table [which they mightn't be].  */
 
 static void
-build_insn_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_insn_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   const CGEN_IBASE *ib = & ms1_cgen_insn_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
 
   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
   for (i = 0; i < MAX_INSNS; ++i)
@@ -1040,8 +1031,7 @@ build_insn_table (cd)
 /* Subroutine of ms1_cgen_cpu_open to rebuild the tables.  */
 
 static void
-ms1_cgen_rebuild_tables (cd)
-     CGEN_CPU_TABLE *cd;
+ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
   unsigned int isas = cd->isas;
@@ -1053,7 +1043,7 @@ ms1_cgen_rebuild_tables (cd)
 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
   cd->default_insn_bitsize = UNSET;
   cd->base_insn_bitsize = UNSET;
-  cd->min_insn_bitsize = 65535; /* some ridiculously big number */
+  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
     if (((1 << i) & isas) != 0)
@@ -1065,7 +1055,7 @@ ms1_cgen_rebuild_tables (cd)
 	if (cd->default_insn_bitsize == UNSET)
 	  cd->default_insn_bitsize = isa->default_insn_bitsize;
 	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -1074,7 +1064,7 @@ ms1_cgen_rebuild_tables (cd)
 	if (cd->base_insn_bitsize == UNSET)
 	  cd->base_insn_bitsize = isa->base_insn_bitsize;
 	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -1186,12 +1176,12 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     }
   va_end (ap);
 
-  /* mach unspecified means "all" */
+  /* Mach unspecified means "all".  */
   if (machs == 0)
     machs = (1 << MAX_MACHS) - 1;
-  /* base mach is always selected */
+  /* Base mach is always selected.  */
   machs |= 1;
-  /* isa unspecified means "all" */
+  /* ISA unspecified means "all".  */
   if (isas == 0)
     isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
@@ -1224,9 +1214,7 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
    MACH_NAME is the bfd name of the mach.  */
 
 CGEN_CPU_DESC
-ms1_cgen_cpu_open_1 (mach_name, endian)
-     const char *mach_name;
-     enum cgen_endian endian;
+ms1_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
 {
   return ms1_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
 			       CGEN_CPU_OPEN_ENDIAN, endian,
@@ -1239,8 +1227,7 @@ ms1_cgen_cpu_open_1 (mach_name, endian)
    place as some simulator ports use this but they don't use libopcodes.  */
 
 void
-ms1_cgen_cpu_close (cd)
-     CGEN_CPU_DESC cd;
+ms1_cgen_cpu_close (CGEN_CPU_DESC cd)
 {
   unsigned int i;
   const CGEN_INSN *insns;
@@ -1249,23 +1236,17 @@ ms1_cgen_cpu_close (cd)
     {
       insns = cd->macro_insn_table.init_entries;
       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX ((insns)))
-	    regfree (CGEN_INSN_RX (insns));
-	}
+	if (CGEN_INSN_RX ((insns)))
+	  regfree (CGEN_INSN_RX (insns));
     }
 
   if (cd->insn_table.init_entries)
     {
       insns = cd->insn_table.init_entries;
       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX (insns))
-	    regfree (CGEN_INSN_RX (insns));
-	}
-    }
-
-  
+	if (CGEN_INSN_RX (insns))
+	  regfree (CGEN_INSN_RX (insns));
+    }  
 
   if (cd->macro_insn_table.init_entries)
     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
diff --git a/opcodes/ms1-dis.c b/opcodes/ms1-dis.c
index 0dd5101..ba8fde2 100644
--- a/opcodes/ms1-dis.c
+++ b/opcodes/ms1-dis.c
@@ -1,27 +1,27 @@
 /* Disassembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-dis.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-dis.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
-Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -56,7 +56,7 @@ static int read_insn
   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
    unsigned long *);
 
-/* -- disassembler routines inserted here */
+/* -- disassembler routines inserted here.  */
 
 /* -- dis.c */
 static void print_dollarhex (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
@@ -81,8 +81,7 @@ print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 /* -- */
 
 void ms1_cgen_print_operand
-  PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
-           void const *, bfd_vma, int));
+  (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
 
 /* Main entry point for printing operands.
    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@@ -100,16 +99,15 @@ void ms1_cgen_print_operand
    the handlers.  */
 
 void
-ms1_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     PTR xinfo;
-     CGEN_FIELDS *fields;
-     void const *attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     int length;
+ms1_cgen_print_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   void * xinfo,
+			   CGEN_FIELDS *fields,
+			   void const *attrs ATTRIBUTE_UNUSED,
+			   bfd_vma pc,
+			   int length)
 {
- disassemble_info *info = (disassemble_info *) xinfo;
+  disassemble_info *info = (disassemble_info *) xinfo;
 
   switch (opindex)
     {
@@ -270,8 +268,7 @@ cgen_print_fn * const ms1_cgen_print_handlers[] =
 
 
 void
-ms1_cgen_init_dis (cd)
-     CGEN_CPU_DESC cd;
+ms1_cgen_init_dis (CGEN_CPU_DESC cd)
 {
   ms1_cgen_init_opcode_table (cd);
   ms1_cgen_init_ibld_table (cd);
@@ -323,7 +320,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 
   /* Print the operand as directed by the attributes.  */
   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
-    ; /* nothing to do */
+    ; /* Nothing to do.  */
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
     (*info->print_address_func) (value, info);
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@@ -405,6 +402,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
+
   if (status != 0)
     {
       (*info->memory_error_func) (status, pc, info);
@@ -509,13 +507,13 @@ print_insn (CGEN_CPU_DESC cd,
 	    length = CGEN_EXTRACT_FN (cd, insn)
 	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 
-	  /* length < 0 -> error */
+	  /* Length < 0 -> error.  */
 	  if (length < 0)
 	    return length;
 	  if (length > 0)
 	    {
 	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
-	      /* length is in bits, result is in bytes */
+	      /* Length is in bits, result is in bytes.  */
 	      return length / 8;
 	    }
 	}
@@ -565,7 +563,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
    Print one instruction from PC on INFO->STREAM.
    Return the size of the instruction (in bytes).  */
 
-typedef struct cpu_desc_list {
+typedef struct cpu_desc_list
+{
   struct cpu_desc_list *next;
   int isa;
   int mach;
@@ -650,7 +649,7 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info)
       if (!cd)
 	abort ();
 
-      /* save this away for future reference */
+      /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
       cl->isa = isa;
diff --git a/opcodes/ms1-ibld.c b/opcodes/ms1-ibld.c
index fc84860..3ffbd84 100644
--- a/opcodes/ms1-ibld.c
+++ b/opcodes/ms1-ibld.c
@@ -1,25 +1,26 @@
 /* Instruction building/extraction support for ms1. -*- C -*-
 
-THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
-- the resultant file is machine generated, cgen-ibld.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+   - the resultant file is machine generated, cgen-ibld.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #include "opintl.h"
 #include "safe-ctype.h"
 
-#undef min
+#undef  min
 #define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
+#undef  max
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 /* Used by the ifield rtx function.  */
@@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
   if (length == 0)
     return NULL;
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
 
 #if CGEN_INT_INSN_P
 /* Cover function to store an insn value into an integral insn.  Must go here
- because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
+   because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
       int shift = insn_length - length;
       /* Written this way to avoid undefined behaviour.  */
       CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
       *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
     }
 }
@@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
 {
   unsigned long x;
   int shift;
-#if 0
-  int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
-#endif
+
   x = cgen_get_insn_value (cd, bufp, word_length);
 
   if (CGEN_INSN_LSB0_P)
@@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
       return 1;
     }
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
   return CGEN_INSN_BITSIZE (insn);
 }
 
-/* machine generated code added here */
+/* Machine generated code added here.  */
 
 const char * ms1_cgen_insert_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 
 /* Main entry point for operand insertion.
 
@@ -559,12 +547,11 @@ const char * ms1_cgen_insert_operand
    resolved during parsing.  */
 
 const char *
-ms1_cgen_insert_operand (cd, opindex, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+ms1_cgen_insert_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     CGEN_INSN_BYTES_PTR buffer,
+			     bfd_vma pc ATTRIBUTE_UNUSED)
 {
   const char * errmsg = NULL;
   unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@@ -732,8 +719,7 @@ ms1_cgen_insert_operand (cd, opindex, fields, buffer, pc)
 }
 
 int ms1_cgen_extract_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-           CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 
 /* Main entry point for operand extraction.
    The result is <= 0 for error, >0 for success.
@@ -751,13 +737,12 @@ int ms1_cgen_extract_operand
    the handlers.  */
 
 int
-ms1_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS * fields;
-     bfd_vma pc;
+ms1_cgen_extract_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_EXTRACT_INFO *ex_info,
+			     CGEN_INSN_INT insn_value,
+			     CGEN_FIELDS * fields,
+			     bfd_vma pc)
 {
   /* Assume success (for those operands that are nops).  */
   int length = 1;
@@ -937,10 +922,8 @@ cgen_extract_fn * const ms1_cgen_extract_handlers[] =
   extract_insn_normal,
 };
 
-int ms1_cgen_get_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
-bfd_vma ms1_cgen_get_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+int ms1_cgen_get_int_operand     (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+bfd_vma ms1_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
 
 /* Getting values from cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they return.
@@ -948,10 +931,9 @@ bfd_vma ms1_cgen_get_vma_operand
    not appropriate.  */
 
 int
-ms1_cgen_get_int_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+ms1_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   int value;
 
@@ -1110,10 +1092,9 @@ ms1_cgen_get_int_operand (cd, opindex, fields)
 }
 
 bfd_vma
-ms1_cgen_get_vma_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+ms1_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   bfd_vma value;
 
@@ -1271,10 +1252,8 @@ ms1_cgen_get_vma_operand (cd, opindex, fields)
   return value;
 }
 
-void ms1_cgen_set_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
-void ms1_cgen_set_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+void ms1_cgen_set_int_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
+void ms1_cgen_set_vma_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
 
 /* Stuffing values in cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they accept.
@@ -1282,11 +1261,10 @@ void ms1_cgen_set_vma_operand
    not appropriate.  */
 
 void
-ms1_cgen_set_int_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     int value;
+ms1_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     int value)
 {
   switch (opindex)
     {
@@ -1441,11 +1419,10 @@ ms1_cgen_set_int_operand (cd, opindex, fields, value)
 }
 
 void
-ms1_cgen_set_vma_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     bfd_vma value;
+ms1_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     bfd_vma value)
 {
   switch (opindex)
     {
@@ -1602,8 +1579,7 @@ ms1_cgen_set_vma_operand (cd, opindex, fields, value)
 /* Function to call before using the instruction builder tables.  */
 
 void
-ms1_cgen_init_ibld_table (cd)
-     CGEN_CPU_DESC cd;
+ms1_cgen_init_ibld_table (CGEN_CPU_DESC cd)
 {
   cd->insert_handlers = & ms1_cgen_insert_handlers[0];
   cd->extract_handlers = & ms1_cgen_extract_handlers[0];
diff --git a/opcodes/ms1-opc.c b/opcodes/ms1-opc.c
index d7c57be..4b9a05c 100644
--- a/opcodes/ms1-opc.c
+++ b/opcodes/ms1-opc.c
@@ -69,10 +69,10 @@ ms1_asm_hash (const char* insn)
 /* The hash functions are recorded here to help keep assembler code out of
    the disassembler and vice versa.  */
 
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static int asm_hash_insn_p        (const CGEN_INSN *);
+static unsigned int asm_hash_insn (const char *);
+static int dis_hash_insn_p        (const CGEN_INSN *);
+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
 
 /* Instruction formats.  */
 
@@ -839,14 +839,10 @@ dis_hash_insn (buf, value)
   return CGEN_DIS_HASH (buf, value);
 }
 
-static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
-
 /* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
 
 static void
-set_fields_bitsize (fields, size)
-     CGEN_FIELDS *fields;
-     int size;
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
 {
   CGEN_FIELDS_BITSIZE (fields) = size;
 }
@@ -855,15 +851,15 @@ set_fields_bitsize (fields, size)
    This plugs the opcode entries and macro instructions into the cpu table.  */
 
 void
-ms1_cgen_init_opcode_table (cd)
-     CGEN_CPU_DESC cd;
+ms1_cgen_init_opcode_table (CGEN_CPU_DESC cd)
 {
   int i;
   int num_macros = (sizeof (ms1_cgen_macro_insn_table) /
 		    sizeof (ms1_cgen_macro_insn_table[0]));
   const CGEN_IBASE *ib = & ms1_cgen_macro_insn_table[0];
   const CGEN_OPCODE *oc = & ms1_cgen_macro_insn_opcode_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
+
   memset (insns, 0, num_macros * sizeof (CGEN_INSN));
   for (i = 0; i < num_macros; ++i)
     {
diff --git a/opcodes/msp430-dis.c b/opcodes/msp430-dis.c
index 3563cac..0f61665 100644
--- a/opcodes/msp430-dis.c
+++ b/opcodes/msp430-dis.c
@@ -1,5 +1,5 @@
 /* Disassemble MSP430 instructions.
-   Copyright (C) 2002, 2004 Free Software Foundation, Inc.
+   Copyright (C) 2002, 2004, 2005 Free Software Foundation, Inc.
    
    Contributed by Dmitry Diky <diwil@mail.ru>
         
@@ -15,7 +15,8 @@
    
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include <ctype.h>
@@ -31,28 +32,10 @@
 #undef DASM_SECTION
 
 
-static unsigned short msp430dis_opcode
-  PARAMS ((bfd_vma, disassemble_info *));
-int print_insn_msp430
-  PARAMS ((bfd_vma, disassemble_info *));
-int msp430_nooperands
-  PARAMS ((struct msp430_opcode_s *, bfd_vma, unsigned short, char *, int *));
-int msp430_singleoperand
-  PARAMS ((disassemble_info *, struct msp430_opcode_s *, bfd_vma, unsigned short,
-	   char *, char *, int *));
-int msp430_doubleoperand
-  PARAMS ((disassemble_info *, struct msp430_opcode_s *, bfd_vma, unsigned short,
-	   char *, char *, char *, char *, int *));
-int msp430_branchinstr
-  PARAMS ((disassemble_info *, struct msp430_opcode_s *, bfd_vma, unsigned short,
-	   char *, char *, int *));
-
 #define PS(x)   (0xffff & (x))
 
 static unsigned short
-msp430dis_opcode (addr, info)
-     bfd_vma addr;
-     disassemble_info *info;
+msp430dis_opcode (bfd_vma addr, disassemble_info *info)
 {
   bfd_byte buffer[2];
   int status;
@@ -66,138 +49,12 @@ msp430dis_opcode (addr, info)
   return bfd_getl16 (buffer);
 }
 
-int
-print_insn_msp430 (addr, info)
-     bfd_vma addr;
-     disassemble_info *info;
-{
-  void *stream = info->stream;
-  fprintf_ftype prin = info->fprintf_func;
-  struct msp430_opcode_s *opcode;
-  char op1[32], op2[32], comm1[64], comm2[64];
-  int cmd_len = 0;
-  unsigned short insn;
-  int cycles = 0;
-  char *bc = "";
-  char dinfo[32];		/* Debug purposes.  */
-
-  insn = msp430dis_opcode (addr, info);
-  sprintf (dinfo, "0x%04x", insn);
-
-  if (((int) addr & 0xffff) > 0xffdf)
-    {
-      (*prin) (stream, "interrupt service routine at 0x%04x", 0xffff & insn);
-      return 2;
-    }
-
-  *comm1 = 0;
-  *comm2 = 0;
-
-  for (opcode = msp430_opcodes; opcode->name; opcode++)
-    {
-      if ((insn & opcode->bin_mask) == opcode->bin_opcode
-	  && opcode->bin_opcode != 0x9300)
-	{
-	  *op1 = 0;
-	  *op2 = 0;
-	  *comm1 = 0;
-	  *comm2 = 0;
-
-	  /* r0 as destination. Ad should be zero.  */
-	  if (opcode->insn_opnumb == 3 && (insn & 0x000f) == 0
-	      && (0x0080 & insn) == 0)
-	    {
-	      cmd_len =
-		msp430_branchinstr (info, opcode, addr, insn, op1, comm1,
-				    &cycles);
-	      if (cmd_len)
-		break;
-	    }
-
-	  switch (opcode->insn_opnumb)
-	    {
-	    case 0:
-	      cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles);
-	      break;
-	    case 2:
-	      cmd_len =
-		msp430_doubleoperand (info, opcode, addr, insn, op1, op2,
-				      comm1, comm2, &cycles);
-	      if (insn & BYTE_OPERATION)
-		bc = ".b";
-	      break;
-	    case 1:
-	      cmd_len =
-		msp430_singleoperand (info, opcode, addr, insn, op1, comm1,
-				      &cycles);
-	      if (insn & BYTE_OPERATION && opcode->fmt != 3)
-		bc = ".b";
-	      break;
-	    default:
-	      break;
-	    }
-	}
-
-      if (cmd_len)
-	break;
-    }
-
-  dinfo[5] = 0;
-
-  if (cmd_len < 1)
-    {
-      /* Unknown opcode, or invalid combination of operands.  */
-      (*prin) (stream, ".word	0x%04x;	????", PS (insn));
-      return 2;
-    }
-
-  (*prin) (stream, "%s%s", opcode->name, bc);
-
-  if (*op1)
-    (*prin) (stream, "\t%s", op1);
-  if (*op2)
-    (*prin) (stream, ",");
-
-  if (strlen (op1) < 7)
-    (*prin) (stream, "\t");
-  if (!strlen (op1))
-    (*prin) (stream, "\t");
-
-  if (*op2)
-    (*prin) (stream, "%s", op2);
-  if (strlen (op2) < 8)
-    (*prin) (stream, "\t");
-
-  if (*comm1 || *comm2)
-    (*prin) (stream, ";");
-  else if (cycles)
-    {
-      if (*op2)
-	(*prin) (stream, ";");
-      else
-	{
-	  if (strlen (op1) < 7)
-	    (*prin) (stream, ";");
-	  else
-	    (*prin) (stream, "\t;");
-	}
-    }
-  if (*comm1)
-    (*prin) (stream, "%s", comm1);
-  if (*comm1 && *comm2)
-    (*prin) (stream, ",");
-  if (*comm2)
-    (*prin) (stream, " %s", comm2);
-  return cmd_len;
-}
-
-int
-msp430_nooperands (opcode, addr, insn, comm, cycles)
-     struct msp430_opcode_s *opcode;
-     bfd_vma addr ATTRIBUTE_UNUSED;
-     unsigned short insn ATTRIBUTE_UNUSED;
-     char *comm;
-     int *cycles;
+static int
+msp430_nooperands (struct msp430_opcode_s *opcode,
+		   bfd_vma addr ATTRIBUTE_UNUSED,
+		   unsigned short insn ATTRIBUTE_UNUSED,
+		   char *comm,
+		   int *cycles)
 {
   /* Pop with constant.  */
   if (insn == 0x43b2)
@@ -222,16 +79,14 @@ msp430_nooperands (opcode, addr, insn, comm, cycles)
   return 2;
 }
 
-
-int
-msp430_singleoperand (info, opcode, addr, insn, op, comm, cycles)
-     disassemble_info *info;
-     struct msp430_opcode_s *opcode;
-     bfd_vma addr;
-     unsigned short insn;
-     char *op;
-     char *comm;
-     int *cycles;
+static int
+msp430_singleoperand (disassemble_info *info,
+		      struct msp430_opcode_s *opcode,
+		      bfd_vma addr,
+		      unsigned short insn,
+		      char *op,
+		      char *comm,
+		      int *cycles)
 {
   int regs = 0, regd = 0;
   int ad = 0, as = 0;
@@ -277,7 +132,7 @@ msp430_singleoperand (info, opcode, addr, insn, op, comm, cycles)
 	  else
 	    sprintf (op, "r%d", regd);
 	}
-      else			/* ad == 1 msp430dis_opcode.  */
+      else	/* ad == 1 msp430dis_opcode.  */
 	{
 	  if (regd == 0)
 	    {
@@ -308,7 +163,6 @@ msp430_singleoperand (info, opcode, addr, insn, op, comm, cycles)
       break;
 
     case 2:	/* rrc, push, call, swpb, rra, sxt, push, call, reti etc...  */
-
       if (as == 0)
 	{
 	  if (regd == 3)
@@ -427,15 +281,16 @@ msp430_singleoperand (info, opcode, addr, insn, op, comm, cycles)
   return cmd_len;
 }
 
-int
-msp430_doubleoperand (info, opcode, addr, insn, op1, op2, comm1, comm2, cycles)
-     disassemble_info *info;
-     struct msp430_opcode_s *opcode;
-     bfd_vma addr;
-     unsigned short insn;
-     char *op1, *op2;
-     char *comm1, *comm2;
-     int *cycles;
+static int
+msp430_doubleoperand (disassemble_info *info,
+		      struct msp430_opcode_s *opcode,
+		      bfd_vma addr,
+		      unsigned short insn,
+		      char *op1,
+		      char *op2,
+		      char *comm1,
+		      char *comm2,
+		      int *cycles)
 {
   int regs = 0, regd = 0;
   int ad = 0, as = 0;
@@ -467,7 +322,7 @@ msp430_doubleoperand (info, opcode, addr, insn, op1, op2, comm1, comm2, cycles)
 	  /* Register mode.  */
 	  if (regd == 3)
 	    {
-	      strcpy (comm1, "Illegal as emulation instr");
+	      strcpy (comm1, _("Illegal as emulation instr"));
 	      return -1;
 	    }
 
@@ -518,7 +373,7 @@ msp430_doubleoperand (info, opcode, addr, insn, op1, op2, comm1, comm2, cycles)
   if (ad == 0 && regd == 3)
     {
       /* R2/R3 are illegal as dest: may be data section.  */
-      strcpy (comm1, "Illegal as 2-op instr");
+      strcpy (comm1, _("Illegal as 2-op instr"));
       return -1;
     }
 
@@ -579,7 +434,7 @@ msp430_doubleoperand (info, opcode, addr, insn, op1, op2, comm1, comm2, cycles)
       else if (regs == 0)
 	{
 	  *cycles = 3;
-	  /* Absolute. @pc+  */
+	  /* Absolute. @pc+.  */
 	  dst = msp430dis_opcode (addr + 2, info);
 	  cmd_len += 2;
 	  sprintf (op1, "#%d", dst);
@@ -647,7 +502,7 @@ msp430_doubleoperand (info, opcode, addr, insn, op1, op2, comm1, comm2, cycles)
       else
 	sprintf (op2, "r%d", regd);
     }
-  else				/* ad == 1.  */
+  else	/* ad == 1.  */
     {
       * cycles += 3;
 
@@ -679,16 +534,14 @@ msp430_doubleoperand (info, opcode, addr, insn, op1, op2, comm1, comm2, cycles)
   return cmd_len;
 }
 
-
-int
-msp430_branchinstr (info, opcode, addr, insn, op1, comm1, cycles)
-     disassemble_info *info;
-     struct msp430_opcode_s *opcode ATTRIBUTE_UNUSED;
-     bfd_vma addr ATTRIBUTE_UNUSED;
-     unsigned short insn;
-     char *op1;
-     char *comm1;
-     int *cycles;
+static int
+msp430_branchinstr (disassemble_info *info,
+		    struct msp430_opcode_s *opcode ATTRIBUTE_UNUSED,
+		    bfd_vma addr ATTRIBUTE_UNUSED,
+		    unsigned short insn,
+		    char *op1,
+		    char *comm1,
+		    int *cycles)
 {
   int regs = 0, regd = 0;
   int ad = 0, as = 0;
@@ -807,3 +660,126 @@ msp430_branchinstr (info, opcode, addr, insn, op1, comm1, cycles)
 
   return cmd_len;
 }
+
+int
+print_insn_msp430 (bfd_vma addr, disassemble_info *info)
+{
+  void *stream = info->stream;
+  fprintf_ftype prin = info->fprintf_func;
+  struct msp430_opcode_s *opcode;
+  char op1[32], op2[32], comm1[64], comm2[64];
+  int cmd_len = 0;
+  unsigned short insn;
+  int cycles = 0;
+  char *bc = "";
+  char dinfo[32];		/* Debug purposes.  */
+
+  insn = msp430dis_opcode (addr, info);
+  sprintf (dinfo, "0x%04x", insn);
+
+  if (((int) addr & 0xffff) > 0xffdf)
+    {
+      (*prin) (stream, "interrupt service routine at 0x%04x", 0xffff & insn);
+      return 2;
+    }
+
+  *comm1 = 0;
+  *comm2 = 0;
+
+  for (opcode = msp430_opcodes; opcode->name; opcode++)
+    {
+      if ((insn & opcode->bin_mask) == opcode->bin_opcode
+	  && opcode->bin_opcode != 0x9300)
+	{
+	  *op1 = 0;
+	  *op2 = 0;
+	  *comm1 = 0;
+	  *comm2 = 0;
+
+	  /* r0 as destination. Ad should be zero.  */
+	  if (opcode->insn_opnumb == 3 && (insn & 0x000f) == 0
+	      && (0x0080 & insn) == 0)
+	    {
+	      cmd_len =
+		msp430_branchinstr (info, opcode, addr, insn, op1, comm1,
+				    &cycles);
+	      if (cmd_len)
+		break;
+	    }
+
+	  switch (opcode->insn_opnumb)
+	    {
+	    case 0:
+	      cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles);
+	      break;
+	    case 2:
+	      cmd_len =
+		msp430_doubleoperand (info, opcode, addr, insn, op1, op2,
+				      comm1, comm2, &cycles);
+	      if (insn & BYTE_OPERATION)
+		bc = ".b";
+	      break;
+	    case 1:
+	      cmd_len =
+		msp430_singleoperand (info, opcode, addr, insn, op1, comm1,
+				      &cycles);
+	      if (insn & BYTE_OPERATION && opcode->fmt != 3)
+		bc = ".b";
+	      break;
+	    default:
+	      break;
+	    }
+	}
+
+      if (cmd_len)
+	break;
+    }
+
+  dinfo[5] = 0;
+
+  if (cmd_len < 1)
+    {
+      /* Unknown opcode, or invalid combination of operands.  */
+      (*prin) (stream, ".word	0x%04x;	????", PS (insn));
+      return 2;
+    }
+
+  (*prin) (stream, "%s%s", opcode->name, bc);
+
+  if (*op1)
+    (*prin) (stream, "\t%s", op1);
+  if (*op2)
+    (*prin) (stream, ",");
+
+  if (strlen (op1) < 7)
+    (*prin) (stream, "\t");
+  if (!strlen (op1))
+    (*prin) (stream, "\t");
+
+  if (*op2)
+    (*prin) (stream, "%s", op2);
+  if (strlen (op2) < 8)
+    (*prin) (stream, "\t");
+
+  if (*comm1 || *comm2)
+    (*prin) (stream, ";");
+  else if (cycles)
+    {
+      if (*op2)
+	(*prin) (stream, ";");
+      else
+	{
+	  if (strlen (op1) < 7)
+	    (*prin) (stream, ";");
+	  else
+	    (*prin) (stream, "\t;");
+	}
+    }
+  if (*comm1)
+    (*prin) (stream, "%s", comm1);
+  if (*comm1 && *comm2)
+    (*prin) (stream, ",");
+  if (*comm2)
+    (*prin) (stream, " %s", comm2);
+  return cmd_len;
+}
diff --git a/opcodes/ns32k-dis.c b/opcodes/ns32k-dis.c
index a7bcbc4..7ed4ab2 100644
--- a/opcodes/ns32k-dis.c
+++ b/opcodes/ns32k-dis.c
@@ -2,21 +2,22 @@
    Copyright 1986, 1988, 1991, 1992, 1994, 1998, 2001, 2002, 2005
    Free Software Foundation, Inc.
 
-This file is part of opcodes library.
+   This file is part of opcodes library.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 
 #include "bfd.h"
@@ -30,43 +31,26 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 static disassemble_info *dis_info;
 
-/*
- * Hacks to get it to compile <= READ THESE AS FIXES NEEDED
- */
-#define INVALID_FLOAT(val, size) invalid_float((bfd_byte *)val, size)
-
-static int print_insn_arg
-  PARAMS ((int, int, int *, bfd_byte *, bfd_vma, char *, int));
-static int get_displacement PARAMS ((bfd_byte *, int *));
-static int invalid_float PARAMS ((bfd_byte *, int));
-static long int read_memory_integer PARAMS ((unsigned char *, int));
-static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *));
-struct ns32k_option;
-static void optlist PARAMS ((int, const struct ns32k_option *, char *));
-static void list_search PARAMS ((int, const struct ns32k_option *, char *));
-static int bit_extract PARAMS ((bfd_byte *, int, int));
-static int bit_extract_simple PARAMS ((bfd_byte *, int, int));
-static void bit_copy PARAMS ((bfd_byte *, int, int, char *));
-static int sign_extend PARAMS ((int, int));
-static void flip_bytes PARAMS ((char *, int));
-
-static long read_memory_integer(addr, nr)
-     unsigned char *addr;
-     int nr;
+/* Hacks to get it to compile <= READ THESE AS FIXES NEEDED.  */
+#define INVALID_FLOAT(val, size) invalid_float ((bfd_byte *) val, size)
+
+static long
+read_memory_integer (unsigned char * addr, int nr)
 {
   long val;
   int i;
-  for (val = 0, i = nr - 1; i >= 0; i--) {
-    val =  (val << 8);
-    val |= (0xff & *(addr + i));
-  }
+
+  for (val = 0, i = nr - 1; i >= 0; i--)
+    {
+      val =  (val << 8);
+      val |= (0xff & *(addr + i));
+    }
   return val;
 }
 
 /* 32000 instructions are never longer than this.  */
 #define MAXLEN 62
 
-
 #include <setjmp.h>
 
 struct private
@@ -87,12 +71,10 @@ struct private
    ? 1 : fetch_data ((info), (addr)))
 
 static int
-fetch_data (info, addr)
-     struct disassemble_info *info;
-     bfd_byte *addr;
+fetch_data (struct disassemble_info *info, bfd_byte *addr)
 {
   int status;
-  struct private *priv = (struct private *)info->private_data;
+  struct private *priv = (struct private *) info->private_data;
   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 
   status = (*info->read_memory_func) (start,
@@ -108,20 +90,22 @@ fetch_data (info, addr)
     priv->max_fetched = addr;
   return 1;
 }
+
 /* Number of elements in the opcode table.  */
 #define NOPCODES (sizeof ns32k_opcodes / sizeof ns32k_opcodes[0])
 
 #define NEXT_IS_ADDR	'|'
 
 
-struct ns32k_option {
-  char *pattern;		/* the option itself */
-  unsigned long value;		/* binary value of the option */
-  unsigned long match;		/* these bits must match */
+struct ns32k_option
+{
+  char *pattern;		/* The option itself.  */
+  unsigned long value;		/* Binary value of the option.  */
+  unsigned long match;		/* These bits must match.  */
 };
 
 
-static const struct ns32k_option opt_u[]= /* restore, exit */
+static const struct ns32k_option opt_u[]= /* Restore, exit.  */
 {
   { "r0",	0x80,	0x80	},
   { "r1",	0x40,	0x40	},
@@ -134,7 +118,7 @@ static const struct ns32k_option opt_u[]= /* restore, exit */
   {  0 ,	0x00,	0x00	}
 };
 
-static const struct ns32k_option opt_U[]= /* save, enter */
+static const struct ns32k_option opt_U[]= /* Save, enter.  */
 {
   { "r0",	0x01,	0x01	},
   { "r1",	0x02,	0x02	},
@@ -147,7 +131,7 @@ static const struct ns32k_option opt_U[]= /* save, enter */
   {  0 ,	0x00,	0x00	}
 };
 
-static const struct ns32k_option opt_O[]= /* setcfg */
+static const struct ns32k_option opt_O[]= /* Setcfg.  */
 {
   { "c",	0x8,	0x8	},
   { "m",	0x4,	0x4	},
@@ -156,7 +140,7 @@ static const struct ns32k_option opt_O[]= /* setcfg */
   {  0 ,	0x0,	0x0	}
 };
 
-static const struct ns32k_option opt_C[]= /* cinv */
+static const struct ns32k_option opt_C[]= /* Cinv.  */
 {
   { "a",	0x4,	0x4	},
   { "i",	0x2,	0x2	},
@@ -164,7 +148,7 @@ static const struct ns32k_option opt_C[]= /* cinv */
   {  0 ,	0x0,	0x0	}
 };
 
-static const struct ns32k_option opt_S[]= /* string inst */
+static const struct ns32k_option opt_S[]= /* String inst.  */
 {
   { "b",	0x1,	0x1	},
   { "u",	0x6,	0x6	},
@@ -172,7 +156,7 @@ static const struct ns32k_option opt_S[]= /* string inst */
   {  0 ,	0x0,	0x0	}
 };
 
-static const struct ns32k_option list_P532[]= /* lpr spr */
+static const struct ns32k_option list_P532[]= /* Lpr spr.  */
 {
   { "us",	0x0,	0xf	},
   { "dcr",	0x1,	0xf	},
@@ -190,7 +174,7 @@ static const struct ns32k_option list_P532[]= /* lpr spr */
   {  0 ,	0x00,	0xf	}
 };
 
-static const struct ns32k_option list_M532[]= /* lmr smr */
+static const struct ns32k_option list_M532[]= /* Lmr smr.  */
 {
   { "mcr",	0x9,	0xf	},
   { "msr",	0xa,	0xf	},
@@ -202,7 +186,7 @@ static const struct ns32k_option list_M532[]= /* lmr smr */
   {  0 ,	0x0,	0xf	}
 };
 
-static const struct ns32k_option list_P032[]= /* lpr spr */
+static const struct ns32k_option list_P032[]= /* Lpr spr.  */
 {
   { "upsr",	0x0,	0xf	},
   { "fp",	0x8,	0xf	},
@@ -214,7 +198,7 @@ static const struct ns32k_option list_P032[]= /* lpr spr */
   {  0 ,	0x0,	0xf	}
 };
 
-static const struct ns32k_option list_M032[]= /* lmr smr */
+static const struct ns32k_option list_M032[]= /* Lmr smr.  */
 {
   { "bpr0",	0x0,	0xf	},
   { "bpr1",	0x1,	0xf	},
@@ -230,61 +214,55 @@ static const struct ns32k_option list_M032[]= /* lmr smr */
 };
 
 
-/*
- * figure out which options are present
- */
+/* Figure out which options are present.   */
+
 static void
-optlist(options, optionP, result)
-     int options;
-     const struct ns32k_option *optionP;
-     char *result;
+optlist (int options, const struct ns32k_option * optionP, char * result)
 {
-    if (options == 0) {
-	sprintf(result, "[]");
-	return;
+  if (options == 0)
+    {
+      sprintf (result, "[]");
+      return;
     }
-    sprintf(result, "[");
-
-    for (; (options != 0) && optionP->pattern; optionP++) {
-	if ((options & optionP->match) == optionP->value) {
-	    /* we found a match, update result and options */
-	    strcat(result, optionP->pattern);
-	    options &= ~optionP->value;
-	    if (options != 0)	/* more options to come */
-		strcat(result, ",");
+
+  sprintf (result, "[");
+
+  for (; (options != 0) && optionP->pattern; optionP++)
+    {
+      if ((options & optionP->match) == optionP->value)
+	{
+	  /* We found a match, update result and options.  */
+	  strcat (result, optionP->pattern);
+	  options &= ~optionP->value;
+	  if (options != 0)	/* More options to come.  */
+	    strcat (result, ",");
 	}
     }
-    if (options != 0)
-	strcat(result, "undefined");
 
-    strcat(result, "]");
+  if (options != 0)
+    strcat (result, "undefined");
+
+  strcat (result, "]");
 }
 
 static void
-list_search (reg_value, optionP, result)
-     int reg_value;
-     const struct ns32k_option *optionP;
-     char *result;
+list_search (int reg_value, const struct ns32k_option *optionP, char *result)
 {
-    for (; optionP->pattern; optionP++) {
-	if ((reg_value & optionP->match) == optionP->value) {
-	    sprintf(result, "%s", optionP->pattern);
-	    return;
+  for (; optionP->pattern; optionP++)
+    {
+      if ((reg_value & optionP->match) == optionP->value)
+	{
+	  sprintf (result, "%s", optionP->pattern);
+	  return;
 	}
     }
-    sprintf(result, "undefined");
+  sprintf (result, "undefined");
 }
 
-/*
- * extract "count" bits starting "offset" bits
- * into buffer
- */
+/* Extract "count" bits starting "offset" bits into buffer.  */
 
 static int
-bit_extract (buffer, offset, count)
-     bfd_byte *buffer;
-     int offset;
-     int count;
+bit_extract (bfd_byte *buffer, int offset, int count)
 {
   int result;
   int bit;
@@ -295,7 +273,7 @@ bit_extract (buffer, offset, count)
   result = 0;
   while (count--)
     {
-      FETCH_DATA(dis_info, buffer + 1);
+      FETCH_DATA (dis_info, buffer + 1);
       if ((*buffer & (1 << offset)))
 	result |= bit;
       if (++offset == 8)
@@ -308,14 +286,10 @@ bit_extract (buffer, offset, count)
   return result;
 }
 
-/* Like bit extract but the buffer is valid and doen't need to be
- * fetched
- */
+/* Like bit extract but the buffer is valid and doen't need to be fetched.  */
+
 static int
-bit_extract_simple (buffer, offset, count)
-     bfd_byte *buffer;
-     int offset;
-     int count;
+bit_extract_simple (bfd_byte *buffer, int offset, int count)
 {
   int result;
   int bit;
@@ -339,40 +313,32 @@ bit_extract_simple (buffer, offset, count)
 }
 
 static void
-bit_copy (buffer, offset, count, to)
-     bfd_byte *buffer;
-     int offset;
-     int count;
-     char *to;
+bit_copy (bfd_byte *buffer, int offset, int count, char *to)
 {
-  for(; count > 8; count -= 8, to++, offset += 8)
+  for (; count > 8; count -= 8, to++, offset += 8)
     *to = bit_extract (buffer, offset, 8);
   *to = bit_extract (buffer, offset, count);
 }
 
-
 static int
-sign_extend (value, bits)
-     int value, bits;
+sign_extend (int value, int bits)
 {
   value = value & ((1 << bits) - 1);
-  return (value & (1 << (bits-1))
+  return (value & (1 << (bits - 1))
 	  ? value | (~((1 << bits) - 1))
 	  : value);
 }
 
 static void
-flip_bytes (ptr, count)
-     char *ptr;
-     int count;
+flip_bytes (char *ptr, int count)
 {
   char tmp;
 
   while (count > 0)
     {
       tmp = ptr[0];
-      ptr[0] = ptr[count-1];
-      ptr[count-1] = tmp;
+      ptr[0] = ptr[count - 1];
+      ptr[count - 1] = tmp;
       ptr++;
       count -= 2;
     }
@@ -384,158 +350,94 @@ flip_bytes (ptr, count)
    || (c) == 'W' || (c) == 'D' || (c) == 'A' || (c) == 'I' || (c) == 'Z')
 
 /* Adressing modes.  */
-#define Adrmod_index_byte 0x1c
-#define Adrmod_index_word 0x1d
-#define Adrmod_index_doubleword 0x1e
-#define Adrmod_index_quadword 0x1f
+#define Adrmod_index_byte        0x1c
+#define Adrmod_index_word        0x1d
+#define Adrmod_index_doubleword  0x1e
+#define Adrmod_index_quadword    0x1f
 
 /* Is MODE an indexed addressing mode?  */
 #define Adrmod_is_index(mode) \
-  (mode == Adrmod_index_byte \
+  (   mode == Adrmod_index_byte \
    || mode == Adrmod_index_word \
    || mode == Adrmod_index_doubleword \
    || mode == Adrmod_index_quadword)
 
 
-/* Print the 32000 instruction at address MEMADDR in debugged memory,
-   on STREAM.  Returns length of the instruction, in bytes.  */
-
-int
-print_insn_ns32k (memaddr, info)
-     bfd_vma memaddr;
-     disassemble_info *info;
+static int
+get_displacement (bfd_byte *buffer, int *aoffsetp)
 {
-  unsigned int i;
-  const char *d;
-  unsigned short first_word;
-  int ioffset;		/* bits into instruction */
-  int aoffset;		/* bits into arguments */
-  char arg_bufs[MAX_ARGS+1][ARG_LEN];
-  int argnum;
-  int maxarg;
-  struct private priv;
-  bfd_byte *buffer = priv.the_buffer;
-  dis_info = info;
-
-  info->private_data = (PTR) &priv;
-  priv.max_fetched = priv.the_buffer;
-  priv.insn_start = memaddr;
-  if (setjmp (priv.bailout) != 0)
-    /* Error return.  */
-    return -1;
-
-  /* Look for 8bit opcodes first. Other wise, fetching two bytes could take
-   * us over the end of accessible data unnecessarilly
-   */
-  FETCH_DATA(info, buffer + 1);
-  for (i = 0; i < NOPCODES; i++)
-    if (ns32k_opcodes[i].opcode_id_size <= 8
-	&& ((buffer[0]
-	     & (((unsigned long) 1 << ns32k_opcodes[i].opcode_id_size) - 1))
-	    == ns32k_opcodes[i].opcode_seed))
-      break;
-  if (i == NOPCODES) {
-    /* Maybe it is 9 to 16 bits big */
-    FETCH_DATA(info, buffer + 2);
-    first_word = read_memory_integer(buffer, 2);
-
-    for (i = 0; i < NOPCODES; i++)
-      if ((first_word
-	   & (((unsigned long) 1 << ns32k_opcodes[i].opcode_id_size) - 1))
-	  == ns32k_opcodes[i].opcode_seed)
-	break;
-
-    /* Handle undefined instructions.  */
-    if (i == NOPCODES)
-      {
-	(*dis_info->fprintf_func)(dis_info->stream, "0%o", buffer[0]);
-	return 1;
-      }
-  }
-
-  (*dis_info->fprintf_func)(dis_info->stream, "%s", ns32k_opcodes[i].name);
-
-  ioffset = ns32k_opcodes[i].opcode_size;
-  aoffset = ns32k_opcodes[i].opcode_size;
-  d = ns32k_opcodes[i].operands;
+  int Ivalue;
+  short Ivalue2;
 
-  if (*d)
+  Ivalue = bit_extract (buffer, *aoffsetp, 8);
+  switch (Ivalue & 0xc0)
     {
-      /* Offset in bits of the first thing beyond each index byte.
-	 Element 0 is for operand A and element 1 is for operand B.
-	 The rest are irrelevant, but we put them here so we don't
-	 index outside the array.  */
-      int index_offset[MAX_ARGS];
-
-      /* 0 for operand A, 1 for operand B, greater for other args.  */
-      int whicharg = 0;
-      
-      (*dis_info->fprintf_func)(dis_info->stream, "\t");
-
-      maxarg = 0;
-
-      /* First we have to find and keep track of the index bytes,
-	 if we are using scaled indexed addressing mode, since the index
-	 bytes occur right after the basic instruction, not as part
-	 of the addressing extension.  */
-      if (Is_gen(d[1]))
-	{
-	  int addr_mode = bit_extract (buffer, ioffset - 5, 5);
+    case 0x00:
+    case 0x40:
+      Ivalue = sign_extend (Ivalue, 7);
+      *aoffsetp += 8;
+      break;
+    case 0x80:
+      Ivalue2 = bit_extract (buffer, *aoffsetp, 16);
+      flip_bytes ((char *) & Ivalue2, 2);
+      Ivalue = sign_extend (Ivalue2, 14);
+      *aoffsetp += 16;
+      break;
+    case 0xc0:
+      Ivalue = bit_extract (buffer, *aoffsetp, 32);
+      flip_bytes ((char *) & Ivalue, 4);
+      Ivalue = sign_extend (Ivalue, 30);
+      *aoffsetp += 32;
+      break;
+    }
+  return Ivalue;
+}
 
-	  if (Adrmod_is_index (addr_mode))
-	    {
-	      aoffset += 8;
-	      index_offset[0] = aoffset;
-	    }
-	}
-      if (d[2] && Is_gen(d[3]))
-	{
-	  int addr_mode = bit_extract (buffer, ioffset - 10, 5);
+#if 1 /* A version that should work on ns32k f's&d's on any machine.  */
+static int
+invalid_float (bfd_byte *p, int len)
+{
+  int val;
+
+  if (len == 4)
+    val = (bit_extract_simple (p, 23, 8)/*exponent*/ == 0xff
+	   || (bit_extract_simple (p, 23, 8)/*exponent*/ == 0
+	       && bit_extract_simple (p, 0, 23)/*mantisa*/ != 0));
+  else if (len == 8)
+    val = (bit_extract_simple (p, 52, 11)/*exponent*/ == 0x7ff
+	   || (bit_extract_simple (p, 52, 11)/*exponent*/ == 0
+	       && (bit_extract_simple (p, 0, 32)/*low mantisa*/ != 0
+		   || bit_extract_simple (p, 32, 20)/*high mantisa*/ != 0)));
+  else
+    val = 1;
+  return (val);
+}
+#else
+/* Assumes the bytes have been swapped to local order.  */
+typedef union
+{ 
+  double d;
+  float f;
+  struct { unsigned m:23, e:8, :1;} sf;
+  struct { unsigned lm; unsigned m:20, e:11, :1;} sd;
+} float_type_u;
 
-	  if (Adrmod_is_index (addr_mode))
-	    {
-	      aoffset += 8;
-	      index_offset[1] = aoffset;
-	    }
-	}
+static int
+invalid_float (float_type_u *p, int len)
+{
+  int val;
 
-      while (*d)
-	{
-	  argnum = *d - '1';
-	  d++;
-	  if (argnum > maxarg && argnum < MAX_ARGS)
-	    maxarg = argnum;
-	  ioffset = print_insn_arg (*d, ioffset, &aoffset, buffer,
-				    memaddr, arg_bufs[argnum],
-				    index_offset[whicharg]);
-	  d++;
-	  whicharg++;
-	}
-      for (argnum = 0; argnum <= maxarg; argnum++)
-	{
-	  bfd_vma addr;
-	  char *ch;
-	  for (ch = arg_bufs[argnum]; *ch;)
-	    {
-	      if (*ch == NEXT_IS_ADDR)
-		{
-		  ++ch;
-		  addr = bfd_scan_vma (ch, NULL, 16);
-		  (*dis_info->print_address_func) (addr, dis_info);
-		  while (*ch && *ch != NEXT_IS_ADDR)
-		    ++ch;
-		  if (*ch)
-		    ++ch;
-		}
-	      else
-		(*dis_info->fprintf_func)(dis_info->stream, "%c", *ch++);
-	    }
-	  if (argnum < maxarg)
-	    (*dis_info->fprintf_func)(dis_info->stream, ", ");
-	}
-    }
-  return aoffset / 8;
+  if (len == sizeof (float))
+    val = (p->sf.e == 0xff
+	   || (p->sf.e == 0 && p->sf.m != 0));
+  else if (len == sizeof (double))
+    val = (p->sd.e == 0x7ff
+	   || (p->sd.e == 0 && (p->sd.m != 0 || p->sd.lm != 0)));
+  else
+    val = 1;
+  return val;
 }
+#endif
 
 /* Print an instruction operand of category given by d.  IOFFSET is
    the bit position below which small (<1 byte) parts of the operand can
@@ -548,15 +450,16 @@ print_insn_ns32k (memaddr, info)
    general operand using scaled indexed addressing mode).  */
 
 static int
-print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset)
-     int d;
-     int ioffset, *aoffsetp;
-     bfd_byte *buffer;
-     bfd_vma addr;
-     char *result;
-     int index_offset;
+print_insn_arg (int d,
+		int ioffset,
+		int *aoffsetp,
+		bfd_byte *buffer,
+		bfd_vma addr,
+		char *result,
+		int index_offset)
 {
-  union {
+  union
+  {
     float f;
     double d;
     int i[2];
@@ -570,7 +473,7 @@ print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset)
   switch (d)
     {
     case 'f':
-      /* a "gen" operand but 5 bits from the end of instruction */
+      /* A "gen" operand but 5 bits from the end of instruction.  */
       ioffset -= 5;
     case 'Z':
     case 'F':
@@ -580,13 +483,13 @@ print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset)
     case 'W':
     case 'D':
     case 'A':
-      addr_mode = bit_extract (buffer, ioffset-5, 5);
+      addr_mode = bit_extract (buffer, ioffset - 5, 5);
       ioffset -= 5;
       switch (addr_mode)
 	{
 	case 0x0: case 0x1: case 0x2: case 0x3:
 	case 0x4: case 0x5: case 0x6: case 0x7:
-	  /* register mode R0 -- R7 */
+	  /* Register mode R0 -- R7.  */
 	  switch (d)
 	    {
 	    case 'F':
@@ -600,34 +503,35 @@ print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset)
 	  break;
 	case 0x8: case 0x9: case 0xa: case 0xb:
 	case 0xc: case 0xd: case 0xe: case 0xf:
-	  /* Register relative disp(R0 -- R7) */
+	  /* Register relative disp(R0 -- R7).  */
 	  disp1 = get_displacement (buffer, aoffsetp);
 	  sprintf (result, "%d(r%d)", disp1, addr_mode & 7);
 	  break;
 	case 0x10:
 	case 0x11:
 	case 0x12:
-	  /* Memory relative disp2(disp1(FP, SP, SB)) */
+	  /* Memory relative disp2(disp1(FP, SP, SB)).  */
 	  disp1 = get_displacement (buffer, aoffsetp);
 	  disp2 = get_displacement (buffer, aoffsetp);
 	  sprintf (result, "%d(%d(%s))", disp2, disp1,
-		   addr_mode==0x10?"fp":addr_mode==0x11?"sp":"sb");
+		   addr_mode == 0x10 ? "fp" : addr_mode == 0x11 ? "sp" : "sb");
 	  break;
 	case 0x13:
-	  /* reserved */
+	  /* Reserved.  */
 	  sprintf (result, "reserved");
 	  break;
 	case 0x14:
-	  /* Immediate */
+	  /* Immediate.  */
 	  switch (d)
 	    {
-	    case 'I': case 'Z': case 'A':
+	    case 'I':
+	    case 'Z':
+	    case 'A':
 	      /* I and Z are output operands and can`t be immediate
-	       * A is an address and we can`t have the address of
-	       * an immediate either. We don't know how much to increase
-	       * aoffsetp by since whatever generated this is broken
-	       * anyway!
-	       */
+	         A is an address and we can`t have the address of
+	         an immediate either. We don't know how much to increase
+	         aoffsetp by since whatever generated this is broken
+	         anyway!  */
 	      sprintf (result, _("$<undefined>"));
 	      break;
 	    case 'B':
@@ -655,7 +559,7 @@ print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset)
 	      *aoffsetp += 32;
 	      if (INVALID_FLOAT (&value.f, 4))
 		sprintf (result, "<<invalid float 0x%.8x>>", value.i[0]);
-	      else /* assume host has ieee float */
+	      else /* Assume host has ieee float.  */
 		sprintf (result, "$%g", value.f);
 	      break;
 	    case 'L':
@@ -665,43 +569,43 @@ print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset)
 	      if (INVALID_FLOAT (&value.d, 8))
 		sprintf (result, "<<invalid double 0x%.8x%.8x>>",
 			 value.i[1], value.i[0]);
-	      else /* assume host has ieee float */
+	      else /* Assume host has ieee float.  */
 		sprintf (result, "$%g", value.d);
 	      break;
 	    }
 	  break;
 	case 0x15:
-	  /* Absolute @disp */
+	  /* Absolute @disp.  */
 	  disp1 = get_displacement (buffer, aoffsetp);
 	  sprintf (result, "@|%d|", disp1);
 	  break;
 	case 0x16:
-	  /* External EXT(disp1) + disp2 (Mod table stuff) */
+	  /* External EXT(disp1) + disp2 (Mod table stuff).  */
 	  disp1 = get_displacement (buffer, aoffsetp);
 	  disp2 = get_displacement (buffer, aoffsetp);
 	  sprintf (result, "EXT(%d) + %d", disp1, disp2);
 	  break;
 	case 0x17:
-	  /* Top of stack tos */
+	  /* Top of stack tos.  */
 	  sprintf (result, "tos");
 	  break;
 	case 0x18:
-	  /* Memory space disp(FP) */
+	  /* Memory space disp(FP).  */
 	  disp1 = get_displacement (buffer, aoffsetp);
 	  sprintf (result, "%d(fp)", disp1);
 	  break;
 	case 0x19:
-	  /* Memory space disp(SP) */
+	  /* Memory space disp(SP).  */
 	  disp1 = get_displacement (buffer, aoffsetp);
 	  sprintf (result, "%d(sp)", disp1);
 	  break;
 	case 0x1a:
-	  /* Memory space disp(SB) */
+	  /* Memory space disp(SB).  */
 	  disp1 = get_displacement (buffer, aoffsetp);
 	  sprintf (result, "%d(sb)", disp1);
 	  break;
 	case 0x1b:
-	  /* Memory space disp(PC) */
+	  /* Memory space disp(PC).  */
 	  disp1 = get_displacement (buffer, aoffsetp);
 	  *result++ = NEXT_IS_ADDR;
 	  sprintf_vma (result, addr + disp1);
@@ -713,7 +617,7 @@ print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset)
 	case 0x1d:
 	case 0x1e:
 	case 0x1f:
-	  /* Scaled index basemode[R0 -- R7:B,W,D,Q] */
+	  /* Scaled index basemode[R0 -- R7:B,W,D,Q].  */
 	  index = bit_extract (buffer, index_offset - 8, 3);
 	  print_insn_arg (d, index_offset, aoffsetp, buffer, addr,
 			  result, 0);
@@ -745,22 +649,19 @@ print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset)
       break;
     case 'b':
       Ivalue = get_displacement (buffer, aoffsetp);
-      /*
-       * Warning!!  HACK ALERT!
-       * Operand type 'b' is only used by the cmp{b,w,d} and
-       * movm{b,w,d} instructions; we need to know whether
-       * it's a `b' or `w' or `d' instruction; and for both
-       * cmpm and movm it's stored at the same place so we
-       * just grab two bits of the opcode and look at it...
-       * 
-       */
+      /* Warning!!  HACK ALERT!
+         Operand type 'b' is only used by the cmp{b,w,d} and
+         movm{b,w,d} instructions; we need to know whether
+         it's a `b' or `w' or `d' instruction; and for both
+         cmpm and movm it's stored at the same place so we
+         just grab two bits of the opcode and look at it...  */
       size = bit_extract(buffer, ioffset-6, 2);
-      if (size == 0)		/* 00 => b */
+      if (size == 0)		/* 00 => b.  */
 	size = 1;
-      else if (size == 1)	/* 01 => w */
+      else if (size == 1)	/* 01 => w.  */
 	size = 2;
       else
-	size = 4;		/* 11 => d */
+	size = 4;		/* 11 => d.  */
 
       sprintf (result, "%d", (Ivalue / size) + 1);
       break;
@@ -778,130 +679,190 @@ print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset)
       break;
     case 'u':
       Ivalue = bit_extract (buffer, *aoffsetp, 8);
-      optlist(Ivalue, opt_u, result);
+      optlist (Ivalue, opt_u, result);
       *aoffsetp += 8;
       break;
     case 'U':
-      Ivalue = bit_extract(buffer, *aoffsetp, 8);
-      optlist(Ivalue, opt_U, result);
+      Ivalue = bit_extract (buffer, *aoffsetp, 8);
+      optlist (Ivalue, opt_U, result);
       *aoffsetp += 8;
       break;
     case 'O':
-      Ivalue = bit_extract(buffer, ioffset-9, 9);
-      optlist(Ivalue, opt_O, result);
+      Ivalue = bit_extract (buffer, ioffset - 9, 9);
+      optlist (Ivalue, opt_O, result);
       ioffset -= 9;
       break;
     case 'C':
-      Ivalue = bit_extract(buffer, ioffset-4, 4);
-      optlist(Ivalue, opt_C, result);
+      Ivalue = bit_extract (buffer, ioffset - 4, 4);
+      optlist (Ivalue, opt_C, result);
       ioffset -= 4;
       break;
     case 'S':
-      Ivalue = bit_extract(buffer, ioffset - 8, 8);
-      optlist(Ivalue, opt_S, result);
+      Ivalue = bit_extract (buffer, ioffset - 8, 8);
+      optlist (Ivalue, opt_S, result);
       ioffset -= 8;
       break;
     case 'M':
-      Ivalue = bit_extract(buffer, ioffset-4, 4);
-      list_search(Ivalue, 0 ? list_M032 : list_M532, result);
+      Ivalue = bit_extract (buffer, ioffset - 4, 4);
+      list_search (Ivalue, 0 ? list_M032 : list_M532, result);
       ioffset -= 4;
       break;
     case 'P':
-      Ivalue = bit_extract(buffer, ioffset-4, 4);
-      list_search(Ivalue, 0 ? list_P032 : list_P532, result);
+      Ivalue = bit_extract (buffer, ioffset - 4, 4);
+      list_search (Ivalue, 0 ? list_P032 : list_P532, result);
       ioffset -= 4;
       break;
     case 'g':
-      Ivalue = bit_extract(buffer, *aoffsetp, 3);
-      sprintf(result, "%d", Ivalue);
+      Ivalue = bit_extract (buffer, *aoffsetp, 3);
+      sprintf (result, "%d", Ivalue);
       *aoffsetp += 3;
       break;
     case 'G':
       Ivalue = bit_extract(buffer, *aoffsetp, 5);
-      sprintf(result, "%d", Ivalue + 1);
+      sprintf (result, "%d", Ivalue + 1);
       *aoffsetp += 5;
       break;
     }
   return ioffset;
 }
 
-static int
-get_displacement (buffer, aoffsetp)
-     bfd_byte *buffer;
-     int *aoffsetp;
+
+/* Print the 32000 instruction at address MEMADDR in debugged memory,
+   on STREAM.  Returns length of the instruction, in bytes.  */
+
+int
+print_insn_ns32k (bfd_vma memaddr, disassemble_info *info)
 {
-  int Ivalue;
-  short Ivalue2;
+  unsigned int i;
+  const char *d;
+  unsigned short first_word;
+  int ioffset;		/* Bits into instruction.  */
+  int aoffset;		/* Bits into arguments.  */
+  char arg_bufs[MAX_ARGS+1][ARG_LEN];
+  int argnum;
+  int maxarg;
+  struct private priv;
+  bfd_byte *buffer = priv.the_buffer;
+  dis_info = info;
 
-  Ivalue = bit_extract (buffer, *aoffsetp, 8);
-  switch (Ivalue & 0xc0)
-    {
-    case 0x00:
-    case 0x40:
-      Ivalue = sign_extend (Ivalue, 7);
-      *aoffsetp += 8;
-      break;
-    case 0x80:
-      Ivalue2 = bit_extract (buffer, *aoffsetp, 16);
-      flip_bytes ((char *) & Ivalue2, 2);
-      Ivalue = sign_extend (Ivalue2, 14);
-      *aoffsetp += 16;
-      break;
-    case 0xc0:
-      Ivalue = bit_extract (buffer, *aoffsetp, 32);
-      flip_bytes ((char *) & Ivalue, 4);
-      Ivalue = sign_extend (Ivalue, 30);
-      *aoffsetp += 32;
+  info->private_data = & priv;
+  priv.max_fetched = priv.the_buffer;
+  priv.insn_start = memaddr;
+  if (setjmp (priv.bailout) != 0)
+    /* Error return.  */
+    return -1;
+
+  /* Look for 8bit opcodes first. Other wise, fetching two bytes could take
+     us over the end of accessible data unnecessarilly.  */
+  FETCH_DATA (info, buffer + 1);
+  for (i = 0; i < NOPCODES; i++)
+    if (ns32k_opcodes[i].opcode_id_size <= 8
+	&& ((buffer[0]
+	     & (((unsigned long) 1 << ns32k_opcodes[i].opcode_id_size) - 1))
+	    == ns32k_opcodes[i].opcode_seed))
       break;
+  if (i == NOPCODES)
+    {
+      /* Maybe it is 9 to 16 bits big.  */
+      FETCH_DATA (info, buffer + 2);
+      first_word = read_memory_integer(buffer, 2);
+
+      for (i = 0; i < NOPCODES; i++)
+	if ((first_word
+	     & (((unsigned long) 1 << ns32k_opcodes[i].opcode_id_size) - 1))
+	    == ns32k_opcodes[i].opcode_seed)
+	  break;
+
+      /* Handle undefined instructions.  */
+      if (i == NOPCODES)
+	{
+	  (*dis_info->fprintf_func)(dis_info->stream, "0%o", buffer[0]);
+	  return 1;
+	}
     }
-  return Ivalue;
-}
-
 
-#if 1 /* a version that should work on ns32k f's&d's on any machine */
-static int
-invalid_float (p, len)
-     register bfd_byte *p;
-     register int len;
-{
-  register int val;
-
-  if ( len == 4 )
-    val = (bit_extract_simple(p, 23, 8)/*exponent*/ == 0xff
-	   || (bit_extract_simple(p, 23, 8)/*exponent*/ == 0 &&
-	       bit_extract_simple(p, 0, 23)/*mantisa*/ != 0));
-  else if ( len == 8 )
-    val = (bit_extract_simple(p, 52, 11)/*exponent*/ == 0x7ff
-	   || (bit_extract_simple(p, 52, 11)/*exponent*/ == 0
-	       && (bit_extract_simple(p, 0, 32)/*low mantisa*/ != 0
-		   || bit_extract_simple(p, 32, 20)/*high mantisa*/ != 0)));
-  else
-    val = 1;
-  return (val);
-}
-#else
+  (*dis_info->fprintf_func)(dis_info->stream, "%s", ns32k_opcodes[i].name);
 
-/* assumes the bytes have been swapped to local order */
-typedef union { double d;
-		float f;
-		struct { unsigned m:23, e:8, :1;} sf;
-		struct { unsigned lm; unsigned m:20, e:11, :1;} sd;
-	      } float_type_u;
+  ioffset = ns32k_opcodes[i].opcode_size;
+  aoffset = ns32k_opcodes[i].opcode_size;
+  d = ns32k_opcodes[i].operands;
 
-static int
-invalid_float (p, len)
-     register float_type_u *p;
-     register int len;
-{
-  register int val;
-  if ( len == sizeof (float) )
-    val = (p->sf.e == 0xff
-	   || (p->sf.e == 0 && p->sf.m != 0));
-  else if ( len == sizeof (double) )
-    val = (p->sd.e == 0x7ff
-	   || (p->sd.e == 0 && (p->sd.m != 0 || p->sd.lm != 0)));
-  else
-    val = 1;
-  return (val);
+  if (*d)
+    {
+      /* Offset in bits of the first thing beyond each index byte.
+	 Element 0 is for operand A and element 1 is for operand B.
+	 The rest are irrelevant, but we put them here so we don't
+	 index outside the array.  */
+      int index_offset[MAX_ARGS];
+
+      /* 0 for operand A, 1 for operand B, greater for other args.  */
+      int whicharg = 0;
+      
+      (*dis_info->fprintf_func)(dis_info->stream, "\t");
+
+      maxarg = 0;
+
+      /* First we have to find and keep track of the index bytes,
+	 if we are using scaled indexed addressing mode, since the index
+	 bytes occur right after the basic instruction, not as part
+	 of the addressing extension.  */
+      if (Is_gen(d[1]))
+	{
+	  int addr_mode = bit_extract (buffer, ioffset - 5, 5);
+
+	  if (Adrmod_is_index (addr_mode))
+	    {
+	      aoffset += 8;
+	      index_offset[0] = aoffset;
+	    }
+	}
+
+      if (d[2] && Is_gen(d[3]))
+	{
+	  int addr_mode = bit_extract (buffer, ioffset - 10, 5);
+
+	  if (Adrmod_is_index (addr_mode))
+	    {
+	      aoffset += 8;
+	      index_offset[1] = aoffset;
+	    }
+	}
+
+      while (*d)
+	{
+	  argnum = *d - '1';
+	  d++;
+	  if (argnum > maxarg && argnum < MAX_ARGS)
+	    maxarg = argnum;
+	  ioffset = print_insn_arg (*d, ioffset, &aoffset, buffer,
+				    memaddr, arg_bufs[argnum],
+				    index_offset[whicharg]);
+	  d++;
+	  whicharg++;
+	}
+      for (argnum = 0; argnum <= maxarg; argnum++)
+	{
+	  bfd_vma addr;
+	  char *ch;
+
+	  for (ch = arg_bufs[argnum]; *ch;)
+	    {
+	      if (*ch == NEXT_IS_ADDR)
+		{
+		  ++ch;
+		  addr = bfd_scan_vma (ch, NULL, 16);
+		  (*dis_info->print_address_func) (addr, dis_info);
+		  while (*ch && *ch != NEXT_IS_ADDR)
+		    ++ch;
+		  if (*ch)
+		    ++ch;
+		}
+	      else
+		(*dis_info->fprintf_func)(dis_info->stream, "%c", *ch++);
+	    }
+	  if (argnum < maxarg)
+	    (*dis_info->fprintf_func)(dis_info->stream, ", ");
+	}
+    }
+  return aoffset / 8;
 }
-#endif
diff --git a/opcodes/openrisc-asm.c b/opcodes/openrisc-asm.c
index a534074..0b67e98 100644
--- a/opcodes/openrisc-asm.c
+++ b/opcodes/openrisc-asm.c
@@ -1,26 +1,27 @@
 /* Assembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-asm.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-asm.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -49,16 +50,12 @@ static const char * parse_insn_normal
 
 /* -- asm.c */
 
-#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
 
-static const char * parse_hi16
-  PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
-static const char * parse_lo16
-  PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
 
 long
-openrisc_sign_extend_16bit (value)
-     long value;
+openrisc_sign_extend_16bit (long value)
 {
   return ((value & 0xffff) ^ 0x8000) - 0x8000;
 }
@@ -66,11 +63,7 @@ openrisc_sign_extend_16bit (value)
 /* Handle hi().  */
 
 static const char *
-parse_hi16 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     long *valuep;
+parse_hi16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
@@ -85,9 +78,9 @@ parse_hi16 (cd, strp, opindex, valuep)
 
       *strp += 3;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
-                                     &result_type, &value);
+				   & result_type, & value);
       if (**strp != ')')
-        return _("missing `)'");
+        return MISSING_CLOSING_PARENTHESIS;
 
       ++*strp;
       if (errmsg == NULL
@@ -120,11 +113,7 @@ parse_hi16 (cd, strp, opindex, valuep)
 /* Handle lo().  */
 
 static const char *
-parse_lo16 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     long *valuep;
+parse_lo16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
@@ -139,9 +128,9 @@ parse_lo16 (cd, strp, opindex, valuep)
 
       *strp += 3;
       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
-				   &result_type, &value);
+				   & result_type, & value);
       if (**strp != ')')
-        return _("missing `)'");
+        return MISSING_CLOSING_PARENTHESIS;
 
       ++*strp;
       ret = value;
@@ -171,7 +160,7 @@ parse_lo16 (cd, strp, opindex, valuep)
 /* -- */
 
 const char * openrisc_cgen_parse_operand
-  PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
 
 /* Main entry point for operand parsing.
 
@@ -187,11 +176,10 @@ const char * openrisc_cgen_parse_operand
    the handlers.  */
 
 const char *
-openrisc_cgen_parse_operand (cd, opindex, strp, fields)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     const char ** strp;
-     CGEN_FIELDS * fields;
+openrisc_cgen_parse_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   const char ** strp,
+			   CGEN_FIELDS * fields)
 {
   const char * errmsg = NULL;
   /* Used by scalar operands that still need to be parsed.  */
@@ -262,8 +250,7 @@ cgen_parse_fn * const openrisc_cgen_parse_handlers[] =
 };
 
 void
-openrisc_cgen_init_asm (cd)
-     CGEN_CPU_DESC cd;
+openrisc_cgen_init_asm (CGEN_CPU_DESC cd)
 {
   openrisc_cgen_init_opcode_table (cd);
   openrisc_cgen_init_ibld_table (cd);
@@ -646,30 +633,3 @@ openrisc_cgen_assemble_insn (CGEN_CPU_DESC cd,
     return NULL;
   }
 }
-
-#if 0 /* This calls back to GAS which we can't do without care.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   This lets GAS parse registers for us.
-   ??? Interesting idea but not currently used.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   FIXME: Not currently used.  */
-
-void
-openrisc_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
-{
-  CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
-  const CGEN_KEYWORD_ENTRY * ke;
-
-  while ((ke = cgen_keyword_search_next (& search)) != NULL)
-    {
-#if 0 /* Unnecessary, should be done in the search routine.  */
-      if (! openrisc_cgen_opval_supported (ke))
-	continue;
-#endif
-      cgen_asm_record_register (cd, ke->name, ke->value);
-    }
-}
-
-#endif /* 0 */
diff --git a/opcodes/openrisc-desc.c b/opcodes/openrisc-desc.c
index dfd10f2..c469694 100644
--- a/opcodes/openrisc-desc.c
+++ b/opcodes/openrisc-desc.c
@@ -699,27 +699,23 @@ static const CGEN_IBASE openrisc_cgen_insn_table[MAX_INSNS] =
 #undef A
 
 /* Initialize anything needed to be done once, before any cpu_open call.  */
-static void init_tables PARAMS ((void));
 
 static void
-init_tables ()
+init_tables (void)
 {
 }
 
-static const CGEN_MACH * lookup_mach_via_bfd_name
-  PARAMS ((const CGEN_MACH *, const char *));
-static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
-static void openrisc_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
+static void build_hw_table      (CGEN_CPU_TABLE *);
+static void build_ifield_table  (CGEN_CPU_TABLE *);
+static void build_operand_table (CGEN_CPU_TABLE *);
+static void build_insn_table    (CGEN_CPU_TABLE *);
+static void openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *);
 
 /* Subroutine of openrisc_cgen_cpu_open to look up a mach via its bfd name.  */
 
 static const CGEN_MACH *
-lookup_mach_via_bfd_name (table, name)
-     const CGEN_MACH *table;
-     const char *name;
+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
 {
   while (table->name)
     {
@@ -733,8 +729,7 @@ lookup_mach_via_bfd_name (table, name)
 /* Subroutine of openrisc_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_hw_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_hw_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -760,8 +755,7 @@ build_hw_table (cd)
 /* Subroutine of openrisc_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_ifield_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_ifield_table (CGEN_CPU_TABLE *cd)
 {
   cd->ifld_table = & openrisc_cgen_ifld_table[0];
 }
@@ -769,8 +763,7 @@ build_ifield_table (cd)
 /* Subroutine of openrisc_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_operand_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_operand_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -778,8 +771,7 @@ build_operand_table (cd)
   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
      However each entry is indexed by it's enum so there can be holes in
      the table.  */
-  const CGEN_OPERAND **selected =
-    (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
 
   cd->operand_table.init_entries = init;
   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@@ -802,12 +794,11 @@ build_operand_table (cd)
    operand elements to be in the table [which they mightn't be].  */
 
 static void
-build_insn_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_insn_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   const CGEN_IBASE *ib = & openrisc_cgen_insn_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
 
   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
   for (i = 0; i < MAX_INSNS; ++i)
@@ -820,8 +811,7 @@ build_insn_table (cd)
 /* Subroutine of openrisc_cgen_cpu_open to rebuild the tables.  */
 
 static void
-openrisc_cgen_rebuild_tables (cd)
-     CGEN_CPU_TABLE *cd;
+openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
   unsigned int isas = cd->isas;
@@ -833,7 +823,7 @@ openrisc_cgen_rebuild_tables (cd)
 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
   cd->default_insn_bitsize = UNSET;
   cd->base_insn_bitsize = UNSET;
-  cd->min_insn_bitsize = 65535; /* some ridiculously big number */
+  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
     if (((1 << i) & isas) != 0)
@@ -845,7 +835,7 @@ openrisc_cgen_rebuild_tables (cd)
 	if (cd->default_insn_bitsize == UNSET)
 	  cd->default_insn_bitsize = isa->default_insn_bitsize;
 	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -854,7 +844,7 @@ openrisc_cgen_rebuild_tables (cd)
 	if (cd->base_insn_bitsize == UNSET)
 	  cd->base_insn_bitsize = isa->base_insn_bitsize;
 	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -966,12 +956,12 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     }
   va_end (ap);
 
-  /* mach unspecified means "all" */
+  /* Mach unspecified means "all".  */
   if (machs == 0)
     machs = (1 << MAX_MACHS) - 1;
-  /* base mach is always selected */
+  /* Base mach is always selected.  */
   machs |= 1;
-  /* isa unspecified means "all" */
+  /* ISA unspecified means "all".  */
   if (isas == 0)
     isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
@@ -1004,9 +994,7 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
    MACH_NAME is the bfd name of the mach.  */
 
 CGEN_CPU_DESC
-openrisc_cgen_cpu_open_1 (mach_name, endian)
-     const char *mach_name;
-     enum cgen_endian endian;
+openrisc_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
 {
   return openrisc_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
 			       CGEN_CPU_OPEN_ENDIAN, endian,
@@ -1019,8 +1007,7 @@ openrisc_cgen_cpu_open_1 (mach_name, endian)
    place as some simulator ports use this but they don't use libopcodes.  */
 
 void
-openrisc_cgen_cpu_close (cd)
-     CGEN_CPU_DESC cd;
+openrisc_cgen_cpu_close (CGEN_CPU_DESC cd)
 {
   unsigned int i;
   const CGEN_INSN *insns;
@@ -1029,23 +1016,17 @@ openrisc_cgen_cpu_close (cd)
     {
       insns = cd->macro_insn_table.init_entries;
       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX ((insns)))
-	    regfree (CGEN_INSN_RX (insns));
-	}
+	if (CGEN_INSN_RX ((insns)))
+	  regfree (CGEN_INSN_RX (insns));
     }
 
   if (cd->insn_table.init_entries)
     {
       insns = cd->insn_table.init_entries;
       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX (insns))
-	    regfree (CGEN_INSN_RX (insns));
-	}
-    }
-
-  
+	if (CGEN_INSN_RX (insns))
+	  regfree (CGEN_INSN_RX (insns));
+    }  
 
   if (cd->macro_insn_table.init_entries)
     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
diff --git a/opcodes/openrisc-dis.c b/opcodes/openrisc-dis.c
index 668ff8e..cb3f99b 100644
--- a/opcodes/openrisc-dis.c
+++ b/opcodes/openrisc-dis.c
@@ -1,27 +1,27 @@
 /* Disassembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-dis.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-dis.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
-Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -56,12 +56,11 @@ static int read_insn
   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
    unsigned long *);
 
-/* -- disassembler routines inserted here */
+/* -- disassembler routines inserted here.  */
 
 
 void openrisc_cgen_print_operand
-  PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
-           void const *, bfd_vma, int));
+  (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
 
 /* Main entry point for printing operands.
    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@@ -79,16 +78,15 @@ void openrisc_cgen_print_operand
    the handlers.  */
 
 void
-openrisc_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     PTR xinfo;
-     CGEN_FIELDS *fields;
-     void const *attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     int length;
+openrisc_cgen_print_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   void * xinfo,
+			   CGEN_FIELDS *fields,
+			   void const *attrs ATTRIBUTE_UNUSED,
+			   bfd_vma pc,
+			   int length)
 {
- disassemble_info *info = (disassemble_info *) xinfo;
+  disassemble_info *info = (disassemble_info *) xinfo;
 
   switch (opindex)
     {
@@ -147,8 +145,7 @@ cgen_print_fn * const openrisc_cgen_print_handlers[] =
 
 
 void
-openrisc_cgen_init_dis (cd)
-     CGEN_CPU_DESC cd;
+openrisc_cgen_init_dis (CGEN_CPU_DESC cd)
 {
   openrisc_cgen_init_opcode_table (cd);
   openrisc_cgen_init_ibld_table (cd);
@@ -200,7 +197,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 
   /* Print the operand as directed by the attributes.  */
   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
-    ; /* nothing to do */
+    ; /* Nothing to do.  */
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
     (*info->print_address_func) (value, info);
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@@ -282,6 +279,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
+
   if (status != 0)
     {
       (*info->memory_error_func) (status, pc, info);
@@ -386,13 +384,13 @@ print_insn (CGEN_CPU_DESC cd,
 	    length = CGEN_EXTRACT_FN (cd, insn)
 	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 
-	  /* length < 0 -> error */
+	  /* Length < 0 -> error.  */
 	  if (length < 0)
 	    return length;
 	  if (length > 0)
 	    {
 	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
-	      /* length is in bits, result is in bytes */
+	      /* Length is in bits, result is in bytes.  */
 	      return length / 8;
 	    }
 	}
@@ -442,7 +440,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
    Print one instruction from PC on INFO->STREAM.
    Return the size of the instruction (in bytes).  */
 
-typedef struct cpu_desc_list {
+typedef struct cpu_desc_list
+{
   struct cpu_desc_list *next;
   int isa;
   int mach;
@@ -527,7 +526,7 @@ print_insn_openrisc (bfd_vma pc, disassemble_info *info)
       if (!cd)
 	abort ();
 
-      /* save this away for future reference */
+      /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
       cl->isa = isa;
diff --git a/opcodes/openrisc-ibld.c b/opcodes/openrisc-ibld.c
index 3636f3b..035f438 100644
--- a/opcodes/openrisc-ibld.c
+++ b/opcodes/openrisc-ibld.c
@@ -1,25 +1,26 @@
 /* Instruction building/extraction support for openrisc. -*- C -*-
 
-THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
-- the resultant file is machine generated, cgen-ibld.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+   - the resultant file is machine generated, cgen-ibld.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #include "opintl.h"
 #include "safe-ctype.h"
 
-#undef min
+#undef  min
 #define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
+#undef  max
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 /* Used by the ifield rtx function.  */
@@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
   if (length == 0)
     return NULL;
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
 
 #if CGEN_INT_INSN_P
 /* Cover function to store an insn value into an integral insn.  Must go here
- because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
+   because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
       int shift = insn_length - length;
       /* Written this way to avoid undefined behaviour.  */
       CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
       *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
     }
 }
@@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
 {
   unsigned long x;
   int shift;
-#if 0
-  int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
-#endif
+
   x = cgen_get_insn_value (cd, bufp, word_length);
 
   if (CGEN_INSN_LSB0_P)
@@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
       return 1;
     }
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
   return CGEN_INSN_BITSIZE (insn);
 }
 
-/* machine generated code added here */
+/* Machine generated code added here.  */
 
 const char * openrisc_cgen_insert_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 
 /* Main entry point for operand insertion.
 
@@ -559,12 +547,11 @@ const char * openrisc_cgen_insert_operand
    resolved during parsing.  */
 
 const char *
-openrisc_cgen_insert_operand (cd, opindex, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+openrisc_cgen_insert_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     CGEN_INSN_BYTES_PTR buffer,
+			     bfd_vma pc ATTRIBUTE_UNUSED)
 {
   const char * errmsg = NULL;
   unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@@ -641,8 +628,7 @@ openrisc_cgen_insert_operand (cd, opindex, fields, buffer, pc)
 }
 
 int openrisc_cgen_extract_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-           CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 
 /* Main entry point for operand extraction.
    The result is <= 0 for error, >0 for success.
@@ -660,13 +646,12 @@ int openrisc_cgen_extract_operand
    the handlers.  */
 
 int
-openrisc_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS * fields;
-     bfd_vma pc;
+openrisc_cgen_extract_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_EXTRACT_INFO *ex_info,
+			     CGEN_INSN_INT insn_value,
+			     CGEN_FIELDS * fields,
+			     bfd_vma pc)
 {
   /* Assume success (for those operands that are nops).  */
   int length = 1;
@@ -752,10 +737,8 @@ cgen_extract_fn * const openrisc_cgen_extract_handlers[] =
   extract_insn_normal,
 };
 
-int openrisc_cgen_get_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
-bfd_vma openrisc_cgen_get_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+int openrisc_cgen_get_int_operand     (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+bfd_vma openrisc_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
 
 /* Getting values from cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they return.
@@ -763,10 +746,9 @@ bfd_vma openrisc_cgen_get_vma_operand
    not appropriate.  */
 
 int
-openrisc_cgen_get_int_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+openrisc_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   int value;
 
@@ -823,10 +805,9 @@ openrisc_cgen_get_int_operand (cd, opindex, fields)
 }
 
 bfd_vma
-openrisc_cgen_get_vma_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+openrisc_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   bfd_vma value;
 
@@ -882,10 +863,8 @@ openrisc_cgen_get_vma_operand (cd, opindex, fields)
   return value;
 }
 
-void openrisc_cgen_set_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
-void openrisc_cgen_set_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+void openrisc_cgen_set_int_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
+void openrisc_cgen_set_vma_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
 
 /* Stuffing values in cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they accept.
@@ -893,11 +872,10 @@ void openrisc_cgen_set_vma_operand
    not appropriate.  */
 
 void
-openrisc_cgen_set_int_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     int value;
+openrisc_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     int value)
 {
   switch (opindex)
     {
@@ -950,11 +928,10 @@ openrisc_cgen_set_int_operand (cd, opindex, fields, value)
 }
 
 void
-openrisc_cgen_set_vma_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     bfd_vma value;
+openrisc_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     bfd_vma value)
 {
   switch (opindex)
     {
@@ -1009,8 +986,7 @@ openrisc_cgen_set_vma_operand (cd, opindex, fields, value)
 /* Function to call before using the instruction builder tables.  */
 
 void
-openrisc_cgen_init_ibld_table (cd)
-     CGEN_CPU_DESC cd;
+openrisc_cgen_init_ibld_table (CGEN_CPU_DESC cd)
 {
   cd->insert_handlers = & openrisc_cgen_insert_handlers[0];
   cd->extract_handlers = & openrisc_cgen_extract_handlers[0];
diff --git a/opcodes/openrisc-opc.c b/opcodes/openrisc-opc.c
index 9ae1534..58aed98 100644
--- a/opcodes/openrisc-opc.c
+++ b/opcodes/openrisc-opc.c
@@ -35,10 +35,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* The hash functions are recorded here to help keep assembler code out of
    the disassembler and vice versa.  */
 
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static int asm_hash_insn_p        (const CGEN_INSN *);
+static unsigned int asm_hash_insn (const char *);
+static int dis_hash_insn_p        (const CGEN_INSN *);
+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
 
 /* Instruction formats.  */
 
@@ -650,14 +650,10 @@ dis_hash_insn (buf, value)
   return CGEN_DIS_HASH (buf, value);
 }
 
-static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
-
 /* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
 
 static void
-set_fields_bitsize (fields, size)
-     CGEN_FIELDS *fields;
-     int size;
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
 {
   CGEN_FIELDS_BITSIZE (fields) = size;
 }
@@ -666,15 +662,15 @@ set_fields_bitsize (fields, size)
    This plugs the opcode entries and macro instructions into the cpu table.  */
 
 void
-openrisc_cgen_init_opcode_table (cd)
-     CGEN_CPU_DESC cd;
+openrisc_cgen_init_opcode_table (CGEN_CPU_DESC cd)
 {
   int i;
   int num_macros = (sizeof (openrisc_cgen_macro_insn_table) /
 		    sizeof (openrisc_cgen_macro_insn_table[0]));
   const CGEN_IBASE *ib = & openrisc_cgen_macro_insn_table[0];
   const CGEN_OPCODE *oc = & openrisc_cgen_macro_insn_opcode_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
+
   memset (insns, 0, num_macros * sizeof (CGEN_INSN));
   for (i = 0; i < num_macros; ++i)
     {
diff --git a/opcodes/openrisc-opc.h b/opcodes/openrisc-opc.h
index 4b2b8d4..bac3b18 100644
--- a/opcodes/openrisc-opc.h
+++ b/opcodes/openrisc-opc.h
@@ -31,7 +31,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #undef  CGEN_DIS_HASH
 #define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2)
 
-extern long openrisc_sign_extend_16bit PARAMS ((long));
+extern long openrisc_sign_extend_16bit (long);
 /* -- */
 /* Enum declaration for openrisc instruction types.  */
 typedef enum cgen_insn_type {
diff --git a/opcodes/or32-dis.c b/opcodes/or32-dis.c
index 890bb18..2555e87 100644
--- a/opcodes/or32-dis.c
+++ b/opcodes/or32-dis.c
@@ -1,5 +1,5 @@
 /* Instruction printing code for the OpenRISC 1000
-   Copyright (C) 2002 Free Software Foundation, Inc.
+   Copyright (C) 2002, 2005 Free Software Foundation, Inc.
    Contributed by Damjan Lampret <lampret@opencores.org>.
    Modified from a29k port.
 
@@ -17,7 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #define DEBUG 0
 
@@ -29,20 +30,10 @@
 
 #define EXTEND29(x) ((x) & (unsigned long) 0x10000000 ? ((x) | (unsigned long) 0xf0000000) : ((x)))
 
-static void          find_bytes_big       PARAMS ((unsigned char *, unsigned long *));
-static void          find_bytes_little    PARAMS ((unsigned char *, unsigned long *));
-static unsigned long or32_extract         PARAMS ((char, char *, unsigned long));
-static int           or32_opcode_match    PARAMS ((unsigned long, char *));
-static void          or32_print_register  PARAMS ((char, char *, unsigned long, struct disassemble_info *));
-static void          or32_print_immediate PARAMS ((char, char *, unsigned long, struct disassemble_info *));
-static int           print_insn           PARAMS ((bfd_vma, struct disassemble_info *));
-
 /* Now find the four bytes of INSN_CH and put them in *INSN.  */
 
 static void
-find_bytes_big (insn_ch, insn)
-     unsigned char *insn_ch;
-     unsigned long *insn;
+find_bytes_big (unsigned char *insn_ch, unsigned long *insn)
 {
   *insn =
     ((unsigned long) insn_ch[0] << 24) +
@@ -55,9 +46,7 @@ find_bytes_big (insn_ch, insn)
 }
 
 static void
-find_bytes_little (insn_ch, insn)
-     unsigned char *insn_ch;
-     unsigned long *insn;
+find_bytes_little (unsigned char *insn_ch, unsigned long *insn)
 {
   *insn =
     ((unsigned long) insn_ch[3] << 24) +
@@ -66,14 +55,10 @@ find_bytes_little (insn_ch, insn)
     ((unsigned long) insn_ch[0]);
 }
 
-typedef void (*find_byte_func_type)
-     PARAMS ((unsigned char *, unsigned long *));
+typedef void (*find_byte_func_type) (unsigned char *, unsigned long *);
 
 static unsigned long
-or32_extract (param_ch, enc_initial, insn)
-     char param_ch;
-     char *enc_initial;
-     unsigned long insn;
+or32_extract (char param_ch, char *enc_initial, unsigned long insn)
 {
   char *enc;
   unsigned long ret = 0;
@@ -162,9 +147,7 @@ or32_extract (param_ch, enc_initial, insn)
 }
 
 static int
-or32_opcode_match (insn, encoding)
-     unsigned long insn;
-     char *encoding;
+or32_opcode_match (unsigned long insn, char *encoding)
 {
   unsigned long ones, zeros;
 
@@ -203,11 +186,10 @@ or32_opcode_match (insn, encoding)
 /* Print register to INFO->STREAM. Used only by print_insn.  */
 
 static void
-or32_print_register (param_ch, encoding, insn, info)
-     char param_ch;
-     char *encoding;
-     unsigned long insn;
-     struct disassemble_info *info;
+or32_print_register (char param_ch,
+		     char *encoding,
+		     unsigned long insn,
+		     struct disassemble_info *info)
 {
   int regnum = or32_extract (param_ch, encoding, insn);
   
@@ -231,11 +213,10 @@ or32_print_register (param_ch, encoding, insn, info)
 /* Print immediate to INFO->STREAM. Used only by print_insn.  */
 
 static void
-or32_print_immediate (param_ch, encoding, insn, info)
-     char param_ch;
-     char *encoding;
-     unsigned long insn;
-     struct disassemble_info *info;
+or32_print_immediate (char param_ch,
+		      char *encoding,
+		      unsigned long insn,
+		      struct disassemble_info *info)
 {
   int imm = or32_extract(param_ch, encoding, insn);
   
@@ -250,9 +231,7 @@ or32_print_immediate (param_ch, encoding, insn, info)
    Return the size of the instruction (always 4 on or32).  */
 
 static int
-print_insn (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn (bfd_vma memaddr, struct disassemble_info *info)
 {
   /* The raw instruction.  */
   unsigned char insn_ch[4];
@@ -260,7 +239,7 @@ print_insn (memaddr, info)
   unsigned long addr;
   /* The four bytes of the instruction.  */
   unsigned long insn;
-  find_byte_func_type find_byte_func = (find_byte_func_type)info->private_data;
+  find_byte_func_type find_byte_func = (find_byte_func_type) info->private_data;
   struct or32_opcode const * opcode;
 
   {
@@ -328,21 +307,18 @@ print_insn (memaddr, info)
 /* Disassemble a big-endian or32 instruction.  */
 
 int
-print_insn_big_or32 (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_big_or32 (bfd_vma memaddr, struct disassemble_info *info)
 {
-  info->private_data = (PTR) find_bytes_big;
+  info->private_data = find_bytes_big;
+
   return print_insn (memaddr, info);
 }
 
 /* Disassemble a little-endian or32 instruction.  */
 
 int
-print_insn_little_or32 (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_little_or32 (bfd_vma memaddr, struct disassemble_info *info)
 {
-  info->private_data = (PTR) find_bytes_little;
+  info->private_data = find_bytes_little;
   return print_insn (memaddr, info);
 }
diff --git a/opcodes/or32-opc.c b/opcodes/or32-opc.c
index a29453e..ae4a03c 100644
--- a/opcodes/or32-opc.c
+++ b/opcodes/or32-opc.c
@@ -1,5 +1,5 @@
 /* Table of opcodes for the OpenRISC 1000 ISA.
-   Copyright 2002, 2004 Free Software Foundation, Inc.
+   Copyright 2002, 2004, 2005 Free Software Foundation, Inc.
    Contributed by Damjan Lampret (lampret@opencores.org).
    
    This file is part of gen_or1k_isa, or1k, GDB and GAS.
@@ -16,7 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 /* We treat all letters the same in encode/decode routines so
    we need to assign some characteristics to them like signess etc.  */
@@ -30,27 +31,18 @@
 #endif
 #include "opcode/or32.h"
 
-static unsigned long           insn_extract         PARAMS ((char, char *));
-static unsigned long *         cover_insn           PARAMS ((unsigned long *, int, unsigned int));
-static int                     num_ones             PARAMS ((unsigned long));
-static struct insn_op_struct * parse_params         PARAMS ((const struct or32_opcode *, struct insn_op_struct *));
-static unsigned long           or32_extract         PARAMS ((char, char *, unsigned long));
-static void                    or32_print_register  PARAMS ((char, char *, unsigned long));
-static void                    or32_print_immediate PARAMS ((char, char *, unsigned long));
-static unsigned long           extend_imm           PARAMS ((unsigned long, char));
-
 const struct or32_letter or32_letters[] =
-  {
-    { 'A', NUM_UNSIGNED },
-    { 'B', NUM_UNSIGNED },
-    { 'D', NUM_UNSIGNED },
-    { 'I', NUM_SIGNED },
-    { 'K', NUM_UNSIGNED },
-    { 'L', NUM_UNSIGNED },
-    { 'N', NUM_SIGNED },
-    { '0', NUM_UNSIGNED },
-    { '\0', 0 }     /* Dummy entry.  */
-  };
+{
+  { 'A', NUM_UNSIGNED },
+  { 'B', NUM_UNSIGNED },
+  { 'D', NUM_UNSIGNED },
+  { 'I', NUM_SIGNED },
+  { 'K', NUM_UNSIGNED },
+  { 'L', NUM_UNSIGNED },
+  { 'N', NUM_SIGNED },
+  { '0', NUM_UNSIGNED },
+  { '\0', 0 }     /* Dummy entry.  */
+};
 
 /* Opcode encoding:
    machine[31:30]: first two bits of opcode
@@ -76,263 +68,263 @@ const struct or32_letter or32_letters[] =
 #endif /* HAS_EXECUTION */
 
 const struct or32_opcode or32_opcodes[] =
-  {
-    { "l.j",       "N",            "00 0x0  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY },
-    { "l.jal",     "N",            "00 0x1  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY },
-    { "l.bnf",     "N",            "00 0x3  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG},
-    { "l.bf",      "N",            "00 0x4  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG },
-    { "l.nop",     "K",            "00 0x5  01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0 },
-    { "l.movhi",   "rD,K",         "00 0x6  DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0 }, /*MM*/
-    { "l.macrc",   "rD",           "00 0x6  DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0 }, /*MM*/
-
-    { "l.sys",     "K",            "00 0x8  00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0 },
-    { "l.trap",    "K",            "00 0x8  01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0 }, /* CZ 21/06/01 */
-    { "l.msync",   "",             "00 0x8  10000 00000 0000 0000 0000 0000", EFN, 0 },
-    { "l.psync",   "",             "00 0x8  10100 00000 0000 0000 0000 0000", EFN, 0 },
-    { "l.csync",   "",             "00 0x8  11000 00000 0000 0000 0000 0000", EFN, 0 },
-    { "l.rfe",     "",             "00 0x9  ----- ----- ---- ---- ---- ----", EF(l_rfe), OR32_IF_DELAY },
-
-    { "lv.all_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
-    { "lv.all_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
-    { "lv.all_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
-    { "lv.all_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
-    { "lv.all_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
-    { "lv.all_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
-    { "lv.all_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
-    { "lv.all_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
-    { "lv.all_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
-    { "lv.all_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
-    { "lv.all_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
-    { "lv.all_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
-    { "lv.any_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0 },
-    { "lv.any_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0 },
-    { "lv.any_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0 },
-    { "lv.any_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0 },
-    { "lv.any_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0 },
-    { "lv.any_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0 },
-    { "lv.any_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0 },
-    { "lv.any_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0 },
-    { "lv.any_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0 },
-    { "lv.any_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0 },
-    { "lv.any_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0 },
-    { "lv.any_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0 },
-    { "lv.add.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0 },
-    { "lv.add.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0 },
-    { "lv.adds.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0 },
-    { "lv.adds.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0 },
-    { "lv.addu.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0 },
-    { "lv.addu.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0 },
-    { "lv.addus.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0 },
-    { "lv.addus.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0 },
-    { "lv.and",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0 },
-    { "lv.avg.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0 },
-    { "lv.avg.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0 },
-    { "lv.cmp_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0 },
-    { "lv.cmp_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0 },
-    { "lv.cmp_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0 },
-    { "lv.cmp_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0 },
-    { "lv.cmp_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0 },
-    { "lv.cmp_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0 },
-    { "lv.cmp_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0 },
-    { "lv.cmp_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0 },
-    { "lv.cmp_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0 },
-    { "lv.cmp_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0 },
-    { "lv.cmp_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0 },
-    { "lv.cmp_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0 },
-    { "lv.madds.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0 },
-    { "lv.max.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0 },
-    { "lv.max.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0 },
-    { "lv.merge.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0 },
-    { "lv.merge.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0 },
-    { "lv.min.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0 },
-    { "lv.min.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0 },
-    { "lv.msubs.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0 },
-    { "lv.muls.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0 },
-    { "lv.nand",   "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0 },
-    { "lv.nor",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0 },
-    { "lv.or",     "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0 },
-    { "lv.pack.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0 },
-    { "lv.pack.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0 },
-    { "lv.packs.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0 },
-    { "lv.packs.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0 },
-    { "lv.packus.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0 },
-    { "lv.packus.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0 },
-    { "lv.perm.n", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0 },
-    { "lv.rl.b",   "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0 },
-    { "lv.rl.h",   "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0 },
-    { "lv.sll.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0 },
-    { "lv.sll.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0 },
-    { "lv.sll",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0 },
-    { "lv.srl.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0 },
-    { "lv.srl.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0 },
-    { "lv.sra.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0 },
-    { "lv.sra.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0 },
-    { "lv.srl",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0 },
-    { "lv.sub.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0 },
-    { "lv.sub.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0 },
-    { "lv.subs.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0 },
-    { "lv.subs.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0 },
-    { "lv.subu.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0 },
-    { "lv.subu.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0 },
-    { "lv.subus.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0 },
-    { "lv.subus.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0 },
-    { "lv.unpack.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0 },
-    { "lv.unpack.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0 },
-    { "lv.xor",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0 },
-    { "lv.cust1",  "",	       "00 0xA  ----- ----- ---- ---- 0xC ----", EFI, 0 },
-    { "lv.cust2",  "",	       "00 0xA  ----- ----- ---- ---- 0xD ----", EFI, 0 },
-    { "lv.cust3",  "",	       "00 0xA  ----- ----- ---- ---- 0xE ----", EFI, 0 },
-    { "lv.cust4",  "",	       "00 0xA  ----- ----- ---- ---- 0xF ----", EFI, 0 },
-
-    { "lf.add.s",   "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
-    { "lf.sub.s",   "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
-    { "lf.mul.s",   "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
-    { "lf.div.s",   "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
-    { "lf.itof.s",  "rD,rA",       "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
-    { "lf.ftoi.s",  "rD,rA",       "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
-    { "lf.rem.s",   "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
-    { "lf.madd.s",  "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
-    { "lf.sfeq.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
-    { "lf.sfne.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
-    { "lf.sfgt.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
-    { "lf.sfge.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
-    { "lf.sflt.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
-    { "lf.sfle.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
-    { "lf.cust1.s", "",	       "00 0xB  ----- ----- ---- ---- 0xE ----", EFI, 0 },
-
-    { "lf.add.d",   "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
-    { "lf.sub.d",   "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
-    { "lf.mul.d",   "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
-    { "lf.div.d",   "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
-    { "lf.itof.d",  "rD,rA",       "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
-    { "lf.ftoi.d",  "rD,rA",       "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
-    { "lf.rem.d",   "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
-    { "lf.madd.d",  "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
-    { "lf.sfeq.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
-    { "lf.sfne.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
-    { "lf.sfgt.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
-    { "lf.sfge.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
-    { "lf.sflt.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
-    { "lf.sfle.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
-    { "lf.cust1.d", "",	       "00 0xC  ----- ----- ---- ---- 0xE ----", EFI, 0 },
-
-    { "lvf.ld",     "rD,0(rA)",    "00 0xD  DDDDD AAAAA ---- ---- 0x0 0x0", EFI, 0 },
-    { "lvf.lw",     "rD,0(rA)",    "00 0xD  DDDDD AAAAA ---- ---- 0x0 0x1", EFI, 0 },
-    { "lvf.sd",     "0(rA),rB",    "00 0xD  ----- AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
-    { "lvf.sw",     "0(rA),rB",    "00 0xD  ----- AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
-
-    { "l.jr",      "rB",           "01 0x1  ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY },
-    { "l.jalr",    "rB",           "01 0x2  ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY },
-    { "l.maci",    "rB,I",         "01 0x3  IIIII ----- BBBB BIII IIII IIII", EF(l_mac), 0 },
-    { "l.cust1",   "",	       "01 0xC  ----- ----- ---- ---- ---- ----", EF(l_cust1), 0 },
-    { "l.cust2",   "",	       "01 0xD  ----- ----- ---- ---- ---- ----", EF(l_cust2), 0 },
-    { "l.cust3",   "",	       "01 0xE  ----- ----- ---- ---- ---- ----", EF(l_cust3), 0 },
-    { "l.cust4",   "",	       "01 0xF  ----- ----- ---- ---- ---- ----", EF(l_cust4), 0 },
-
-    { "l.ld",      "rD,I(rA)",     "10 0x0  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
-    { "l.lwz",     "rD,I(rA)",     "10 0x1  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0 },
-    { "l.lws",     "rD,I(rA)",     "10 0x2  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
-    { "l.lbz",     "rD,I(rA)",     "10 0x3  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0 },
-    { "l.lbs",     "rD,I(rA)",     "10 0x4  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0 },
-    { "l.lhz",     "rD,I(rA)",     "10 0x5  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0 },
-    { "l.lhs",     "rD,I(rA)",     "10 0x6  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0 },
-
-    { "l.addi",    "rD,rA,I",      "10 0x7  DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), 0 },
-    { "l.addic",   "rD,rA,I",      "10 0x8  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
-    { "l.andi",    "rD,rA,K",      "10 0x9  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), 0 },
-    { "l.ori",     "rD,rA,K",      "10 0xA  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0  },
-    { "l.xori",    "rD,rA,I",      "10 0xB  DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0 },
-    { "l.muli",    "rD,rA,I",      "10 0xC  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
-    { "l.mfspr",   "rD,rA,K",      "10 0xD  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0 },
-    { "l.slli",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0 },
-    { "l.srli",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0 },
-    { "l.srai",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0 },
-    { "l.rori",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0 },
-
-    { "l.sfeqi",   "rA,I",         "10 0xF  00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG },
-    { "l.sfnei",   "rA,I",         "10 0xF  00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG },
-    { "l.sfgtui",  "rA,I",         "10 0xF  00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG },
-    { "l.sfgeui",  "rA,I",         "10 0xF  00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG },
-    { "l.sfltui",  "rA,I",         "10 0xF  00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG },
-    { "l.sfleui",  "rA,I",         "10 0xF  00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG },
-    { "l.sfgtsi",  "rA,I",         "10 0xF  01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG },
-    { "l.sfgesi",  "rA,I",         "10 0xF  01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG },
-    { "l.sfltsi",  "rA,I",         "10 0xF  01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG },
-    { "l.sflesi",  "rA,I",         "10 0xF  01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG },
-
-    { "l.mtspr",   "rA,rB,K",      "11 0x0  KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0 },
-    { "l.mac",     "rA,rB",        "11 0x1  ----- AAAAA BBBB B--- ---- 0x1", EF(l_mac), 0 }, /*MM*/
-    { "l.msb",     "rA,rB",        "11 0x1  ----- AAAAA BBBB B--- ---- 0x2", EF(l_msb), 0 }, /*MM*/
-
-    { "l.sd",      "I(rA),rB",     "11 0x4  IIIII AAAAA BBBB BIII IIII IIII", EFI, 0 },
-    { "l.sw",      "I(rA),rB",     "11 0x5  IIIII AAAAA BBBB BIII IIII IIII", EF(l_sw), 0 },
-    { "l.sb",      "I(rA),rB",     "11 0x6  IIIII AAAAA BBBB BIII IIII IIII", EF(l_sb), 0 },
-    { "l.sh",      "I(rA),rB",     "11 0x7  IIIII AAAAA BBBB BIII IIII IIII", EF(l_sh), 0 },
+{
+  { "l.j",       "N",            "00 0x0  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY },
+  { "l.jal",     "N",            "00 0x1  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY },
+  { "l.bnf",     "N",            "00 0x3  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG},
+  { "l.bf",      "N",            "00 0x4  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG },
+  { "l.nop",     "K",            "00 0x5  01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0 },
+  { "l.movhi",   "rD,K",         "00 0x6  DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0 }, /*MM*/
+  { "l.macrc",   "rD",           "00 0x6  DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0 }, /*MM*/
+
+  { "l.sys",     "K",            "00 0x8  00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0 },
+  { "l.trap",    "K",            "00 0x8  01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0 }, /* CZ 21/06/01 */
+  { "l.msync",   "",             "00 0x8  10000 00000 0000 0000 0000 0000", EFN, 0 },
+  { "l.psync",   "",             "00 0x8  10100 00000 0000 0000 0000 0000", EFN, 0 },
+  { "l.csync",   "",             "00 0x8  11000 00000 0000 0000 0000 0000", EFN, 0 },
+  { "l.rfe",     "",             "00 0x9  ----- ----- ---- ---- ---- ----", EF(l_rfe), OR32_IF_DELAY },
+
+  { "lv.all_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
+  { "lv.all_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
+  { "lv.all_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
+  { "lv.all_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
+  { "lv.all_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
+  { "lv.all_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
+  { "lv.all_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
+  { "lv.all_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
+  { "lv.all_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
+  { "lv.all_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
+  { "lv.all_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
+  { "lv.all_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
+  { "lv.any_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0 },
+  { "lv.any_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0 },
+  { "lv.any_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0 },
+  { "lv.any_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0 },
+  { "lv.any_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0 },
+  { "lv.any_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0 },
+  { "lv.any_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0 },
+  { "lv.any_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0 },
+  { "lv.any_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0 },
+  { "lv.any_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0 },
+  { "lv.any_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0 },
+  { "lv.any_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0 },
+  { "lv.add.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0 },
+  { "lv.add.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0 },
+  { "lv.adds.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0 },
+  { "lv.adds.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0 },
+  { "lv.addu.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0 },
+  { "lv.addu.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0 },
+  { "lv.addus.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0 },
+  { "lv.addus.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0 },
+  { "lv.and",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0 },
+  { "lv.avg.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0 },
+  { "lv.avg.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0 },
+  { "lv.cmp_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0 },
+  { "lv.cmp_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0 },
+  { "lv.cmp_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0 },
+  { "lv.cmp_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0 },
+  { "lv.cmp_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0 },
+  { "lv.cmp_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0 },
+  { "lv.cmp_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0 },
+  { "lv.cmp_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0 },
+  { "lv.cmp_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0 },
+  { "lv.cmp_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0 },
+  { "lv.cmp_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0 },
+  { "lv.cmp_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0 },
+  { "lv.madds.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0 },
+  { "lv.max.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0 },
+  { "lv.max.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0 },
+  { "lv.merge.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0 },
+  { "lv.merge.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0 },
+  { "lv.min.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0 },
+  { "lv.min.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0 },
+  { "lv.msubs.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0 },
+  { "lv.muls.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0 },
+  { "lv.nand",   "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0 },
+  { "lv.nor",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0 },
+  { "lv.or",     "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0 },
+  { "lv.pack.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0 },
+  { "lv.pack.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0 },
+  { "lv.packs.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0 },
+  { "lv.packs.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0 },
+  { "lv.packus.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0 },
+  { "lv.packus.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0 },
+  { "lv.perm.n", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0 },
+  { "lv.rl.b",   "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0 },
+  { "lv.rl.h",   "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0 },
+  { "lv.sll.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0 },
+  { "lv.sll.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0 },
+  { "lv.sll",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0 },
+  { "lv.srl.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0 },
+  { "lv.srl.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0 },
+  { "lv.sra.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0 },
+  { "lv.sra.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0 },
+  { "lv.srl",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0 },
+  { "lv.sub.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0 },
+  { "lv.sub.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0 },
+  { "lv.subs.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0 },
+  { "lv.subs.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0 },
+  { "lv.subu.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0 },
+  { "lv.subu.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0 },
+  { "lv.subus.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0 },
+  { "lv.subus.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0 },
+  { "lv.unpack.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0 },
+  { "lv.unpack.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0 },
+  { "lv.xor",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0 },
+  { "lv.cust1",  "",	       "00 0xA  ----- ----- ---- ---- 0xC ----", EFI, 0 },
+  { "lv.cust2",  "",	       "00 0xA  ----- ----- ---- ---- 0xD ----", EFI, 0 },
+  { "lv.cust3",  "",	       "00 0xA  ----- ----- ---- ---- 0xE ----", EFI, 0 },
+  { "lv.cust4",  "",	       "00 0xA  ----- ----- ---- ---- 0xF ----", EFI, 0 },
+  
+  { "lf.add.s",   "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
+  { "lf.sub.s",   "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
+  { "lf.mul.s",   "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
+  { "lf.div.s",   "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
+  { "lf.itof.s",  "rD,rA",       "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
+  { "lf.ftoi.s",  "rD,rA",       "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
+  { "lf.rem.s",   "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
+  { "lf.madd.s",  "rD,rA,rB",    "00 0xB  DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
+  { "lf.sfeq.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
+  { "lf.sfne.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
+  { "lf.sfgt.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
+  { "lf.sfge.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
+  { "lf.sflt.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
+  { "lf.sfle.s",  "rA,rB",       "00 0xB  ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
+  { "lf.cust1.s", "",	       "00 0xB  ----- ----- ---- ---- 0xE ----", EFI, 0 },
+
+  { "lf.add.d",   "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
+  { "lf.sub.d",   "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
+  { "lf.mul.d",   "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
+  { "lf.div.d",   "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
+  { "lf.itof.d",  "rD,rA",       "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
+  { "lf.ftoi.d",  "rD,rA",       "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
+  { "lf.rem.d",   "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
+  { "lf.madd.d",  "rD,rA,rB",    "00 0xC  DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
+  { "lf.sfeq.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
+  { "lf.sfne.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
+  { "lf.sfgt.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
+  { "lf.sfge.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
+  { "lf.sflt.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
+  { "lf.sfle.d",  "rA,rB",       "00 0xC  ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
+  { "lf.cust1.d", "",	       "00 0xC  ----- ----- ---- ---- 0xE ----", EFI, 0 },
+
+  { "lvf.ld",     "rD,0(rA)",    "00 0xD  DDDDD AAAAA ---- ---- 0x0 0x0", EFI, 0 },
+  { "lvf.lw",     "rD,0(rA)",    "00 0xD  DDDDD AAAAA ---- ---- 0x0 0x1", EFI, 0 },
+  { "lvf.sd",     "0(rA),rB",    "00 0xD  ----- AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
+  { "lvf.sw",     "0(rA),rB",    "00 0xD  ----- AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
+
+  { "l.jr",      "rB",           "01 0x1  ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY },
+  { "l.jalr",    "rB",           "01 0x2  ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY },
+  { "l.maci",    "rB,I",         "01 0x3  IIIII ----- BBBB BIII IIII IIII", EF(l_mac), 0 },
+  { "l.cust1",   "",	       "01 0xC  ----- ----- ---- ---- ---- ----", EF(l_cust1), 0 },
+  { "l.cust2",   "",	       "01 0xD  ----- ----- ---- ---- ---- ----", EF(l_cust2), 0 },
+  { "l.cust3",   "",	       "01 0xE  ----- ----- ---- ---- ---- ----", EF(l_cust3), 0 },
+  { "l.cust4",   "",	       "01 0xF  ----- ----- ---- ---- ---- ----", EF(l_cust4), 0 },
+
+  { "l.ld",      "rD,I(rA)",     "10 0x0  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
+  { "l.lwz",     "rD,I(rA)",     "10 0x1  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0 },
+  { "l.lws",     "rD,I(rA)",     "10 0x2  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
+  { "l.lbz",     "rD,I(rA)",     "10 0x3  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0 },
+  { "l.lbs",     "rD,I(rA)",     "10 0x4  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0 },
+  { "l.lhz",     "rD,I(rA)",     "10 0x5  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0 },
+  { "l.lhs",     "rD,I(rA)",     "10 0x6  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0 },
+
+  { "l.addi",    "rD,rA,I",      "10 0x7  DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), 0 },
+  { "l.addic",   "rD,rA,I",      "10 0x8  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
+  { "l.andi",    "rD,rA,K",      "10 0x9  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), 0 },
+  { "l.ori",     "rD,rA,K",      "10 0xA  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0  },
+  { "l.xori",    "rD,rA,I",      "10 0xB  DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0 },
+  { "l.muli",    "rD,rA,I",      "10 0xC  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
+  { "l.mfspr",   "rD,rA,K",      "10 0xD  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0 },
+  { "l.slli",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0 },
+  { "l.srli",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0 },
+  { "l.srai",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0 },
+  { "l.rori",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0 },
+
+  { "l.sfeqi",   "rA,I",         "10 0xF  00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG },
+  { "l.sfnei",   "rA,I",         "10 0xF  00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG },
+  { "l.sfgtui",  "rA,I",         "10 0xF  00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG },
+  { "l.sfgeui",  "rA,I",         "10 0xF  00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG },
+  { "l.sfltui",  "rA,I",         "10 0xF  00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG },
+  { "l.sfleui",  "rA,I",         "10 0xF  00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG },
+  { "l.sfgtsi",  "rA,I",         "10 0xF  01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG },
+  { "l.sfgesi",  "rA,I",         "10 0xF  01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG },
+  { "l.sfltsi",  "rA,I",         "10 0xF  01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG },
+  { "l.sflesi",  "rA,I",         "10 0xF  01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG },
+
+  { "l.mtspr",   "rA,rB,K",      "11 0x0  KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0 },
+  { "l.mac",     "rA,rB",        "11 0x1  ----- AAAAA BBBB B--- ---- 0x1", EF(l_mac), 0 }, /*MM*/
+  { "l.msb",     "rA,rB",        "11 0x1  ----- AAAAA BBBB B--- ---- 0x2", EF(l_msb), 0 }, /*MM*/
+
+  { "l.sd",      "I(rA),rB",     "11 0x4  IIIII AAAAA BBBB BIII IIII IIII", EFI, 0 },
+  { "l.sw",      "I(rA),rB",     "11 0x5  IIIII AAAAA BBBB BIII IIII IIII", EF(l_sw), 0 },
+  { "l.sb",      "I(rA),rB",     "11 0x6  IIIII AAAAA BBBB BIII IIII IIII", EF(l_sb), 0 },
+  { "l.sh",      "I(rA),rB",     "11 0x7  IIIII AAAAA BBBB BIII IIII IIII", EF(l_sh), 0 },
     
-    { "l.add",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x0", EF(l_add), 0 },
-    { "l.addc",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x1", EFI, 0 },
-    { "l.sub",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x2", EF(l_sub), 0 },
-    { "l.and",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x3", EF(l_and), 0 },
-    { "l.or",      "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x4", EF(l_or), 0 },
-    { "l.xor",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x5", EF(l_xor), 0 },
-    { "l.mul",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0x6", EF(l_mul), 0 },
-
-    { "l.sll",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 00-- 0x8", EF(l_sll), 0 },
-    { "l.srl",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 01-- 0x8", EF(l_srl), 0 },
-    { "l.sra",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 10-- 0x8", EF(l_sra), 0 },
-    { "l.ror",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, 0 },
-    { "l.div",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x9", EF(l_div), 0 },
-    { "l.divu",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0xA", EF(l_divu), 0 },
-    { "l.mulu",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0xB", EFI, 0 },
-    { "l.exths",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 00-- 0xC", EFI, 0 },
-    { "l.extbs",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 01-- 0xC", EFI, 0 },
-    { "l.exthz",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 10-- 0xC", EFI, 0 },
-    { "l.extbz",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 11-- 0xC", EFI, 0 },
-    { "l.extws",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 00-- 0xD", EFI, 0 },
-    { "l.extwz",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 01-- 0xD", EFI, 0 },
-    { "l.cmov",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0xE", EFI, 0 },
-    { "l.ff1",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0xF", EFI, 0 },
-
-    { "l.sfeq",    "rA,rB",        "11 0x9  00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG },
-    { "l.sfne",    "rA,rB",        "11 0x9  00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG },
-    { "l.sfgtu",   "rA,rB",        "11 0x9  00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG },
-    { "l.sfgeu",   "rA,rB",        "11 0x9  00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG },
-    { "l.sfltu",   "rA,rB",        "11 0x9  00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG },
-    { "l.sfleu",   "rA,rB",        "11 0x9  00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG },
-    { "l.sfgts",   "rA,rB",        "11 0x9  01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG },
-    { "l.sfges",   "rA,rB",        "11 0x9  01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG },
-    { "l.sflts",   "rA,rB",        "11 0x9  01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG },
-    { "l.sfles",   "rA,rB",        "11 0x9  01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG },
-
-    { "l.cust5",   "",	       "11 0xC  ----- ----- ---- ---- ---- ----", EFI, 0 },
-    { "l.cust6",   "",	       "11 0xD  ----- ----- ---- ---- ---- ----", EFI, 0 },
-    { "l.cust7",   "",	       "11 0xE  ----- ----- ---- ---- ---- ----", EFI, 0 },
-    { "l.cust8",   "",	       "11 0xF  ----- ----- ---- ---- ---- ----", EFI, 0 },
-
-    /* This section should not be defined in or1ksim, since it contains duplicates,
-       which would cause machine builder to complain.  */
+  { "l.add",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x0", EF(l_add), 0 },
+  { "l.addc",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x1", EFI, 0 },
+  { "l.sub",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x2", EF(l_sub), 0 },
+  { "l.and",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x3", EF(l_and), 0 },
+  { "l.or",      "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x4", EF(l_or), 0 },
+  { "l.xor",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x5", EF(l_xor), 0 },
+  { "l.mul",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0x6", EF(l_mul), 0 },
+
+  { "l.sll",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 00-- 0x8", EF(l_sll), 0 },
+  { "l.srl",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 01-- 0x8", EF(l_srl), 0 },
+  { "l.sra",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 10-- 0x8", EF(l_sra), 0 },
+  { "l.ror",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, 0 },
+  { "l.div",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x9", EF(l_div), 0 },
+  { "l.divu",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0xA", EF(l_divu), 0 },
+  { "l.mulu",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0xB", EFI, 0 },
+  { "l.exths",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 00-- 0xC", EFI, 0 },
+  { "l.extbs",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 01-- 0xC", EFI, 0 },
+  { "l.exthz",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 10-- 0xC", EFI, 0 },
+  { "l.extbz",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 11-- 0xC", EFI, 0 },
+  { "l.extws",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 00-- 0xD", EFI, 0 },
+  { "l.extwz",   "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 01-- 0xD", EFI, 0 },
+  { "l.cmov",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0xE", EFI, 0 },
+  { "l.ff1",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0xF", EFI, 0 },
+
+  { "l.sfeq",    "rA,rB",        "11 0x9  00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG },
+  { "l.sfne",    "rA,rB",        "11 0x9  00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG },
+  { "l.sfgtu",   "rA,rB",        "11 0x9  00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG },
+  { "l.sfgeu",   "rA,rB",        "11 0x9  00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG },
+  { "l.sfltu",   "rA,rB",        "11 0x9  00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG },
+  { "l.sfleu",   "rA,rB",        "11 0x9  00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG },
+  { "l.sfgts",   "rA,rB",        "11 0x9  01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG },
+  { "l.sfges",   "rA,rB",        "11 0x9  01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG },
+  { "l.sflts",   "rA,rB",        "11 0x9  01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG },
+  { "l.sfles",   "rA,rB",        "11 0x9  01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG },
+
+  { "l.cust5",   "",	       "11 0xC  ----- ----- ---- ---- ---- ----", EFI, 0 },
+  { "l.cust6",   "",	       "11 0xD  ----- ----- ---- ---- ---- ----", EFI, 0 },
+  { "l.cust7",   "",	       "11 0xE  ----- ----- ---- ---- ---- ----", EFI, 0 },
+  { "l.cust8",   "",	       "11 0xF  ----- ----- ---- ---- ---- ----", EFI, 0 },
+
+  /* This section should not be defined in or1ksim, since it contains duplicates,
+     which would cause machine builder to complain.  */
 #ifdef HAS_CUST
-    { "l.cust5_1",   "rD",	       "11 0xC  DDDDD ----- ---- ---- ---- ----", EFI, 0 },
-    { "l.cust5_2",   "rD,rA"   ,   "11 0xC  DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
-    { "l.cust5_3",   "rD,rA,rB",   "11 0xC  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
+  { "l.cust5_1",   "rD",	       "11 0xC  DDDDD ----- ---- ---- ---- ----", EFI, 0 },
+  { "l.cust5_2",   "rD,rA"   ,   "11 0xC  DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
+  { "l.cust5_3",   "rD,rA,rB",   "11 0xC  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
 
-    { "l.cust6_1",   "rD",	       "11 0xD  DDDDD ----- ---- ---- ---- ----", EFI, 0 },
-    { "l.cust6_2",   "rD,rA"   ,   "11 0xD  DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
-    { "l.cust6_3",   "rD,rA,rB",   "11 0xD  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
+  { "l.cust6_1",   "rD",	       "11 0xD  DDDDD ----- ---- ---- ---- ----", EFI, 0 },
+  { "l.cust6_2",   "rD,rA"   ,   "11 0xD  DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
+  { "l.cust6_3",   "rD,rA,rB",   "11 0xD  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
 
-    { "l.cust7_1",   "rD",	       "11 0xE  DDDDD ----- ---- ---- ---- ----", EFI, 0 },
-    { "l.cust7_2",   "rD,rA"   ,   "11 0xE  DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
-    { "l.cust7_3",   "rD,rA,rB",   "11 0xE  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
+  { "l.cust7_1",   "rD",	       "11 0xE  DDDDD ----- ---- ---- ---- ----", EFI, 0 },
+  { "l.cust7_2",   "rD,rA"   ,   "11 0xE  DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
+  { "l.cust7_3",   "rD,rA,rB",   "11 0xE  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
 
-    { "l.cust8_1",   "rD",	       "11 0xF  DDDDD ----- ---- ---- ---- ----", EFI, 0 },
-    { "l.cust8_2",   "rD,rA"   ,   "11 0xF  DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
-    { "l.cust8_3",   "rD,rA,rB",   "11 0xF  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
+  { "l.cust8_1",   "rD",	       "11 0xF  DDDDD ----- ---- ---- ---- ----", EFI, 0 },
+  { "l.cust8_2",   "rD,rA"   ,   "11 0xF  DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
+  { "l.cust8_3",   "rD,rA,rB",   "11 0xF  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
 #endif
 
-    /* Dummy entry, not included in num_opcodes.  This
-       lets code examine entry i+1 without checking
-       if we've run off the end of the table.  */
-    { "", "", "", EFI, 0 }
+  /* Dummy entry, not included in num_opcodes.  This
+     lets code examine entry i+1 without checking
+     if we've run off the end of the table.  */
+  { "", "", "", EFI, 0 }
 };
 
 #undef EFI
@@ -342,8 +334,6 @@ const struct or32_opcode or32_opcodes[] =
 /* Define dummy, if debug is not defined.  */
 
 #if !defined HAS_DEBUG
-static void debug PARAMS ((int, const char *, ...));
-
 static void
 debug (int level ATTRIBUTE_UNUSED, const char *format ATTRIBUTE_UNUSED, ...)
 {
@@ -355,8 +345,7 @@ const unsigned int or32_num_opcodes = ((sizeof(or32_opcodes)) / (sizeof(struct o
 /* Calculates instruction length in bytes. Always 4 for OR32.  */
 
 int
-insn_len (insn_index)
-     int insn_index ATTRIBUTE_UNUSED;
+insn_len (int insn_index ATTRIBUTE_UNUSED)
 {
   return 4;
 }
@@ -364,8 +353,7 @@ insn_len (insn_index)
 /* Is individual insn's operand signed or unsigned?  */
 
 int
-letter_signed (l)
-     char l;
+letter_signed (char l)
 {
   const struct or32_letter *pletter;
   
@@ -380,19 +368,18 @@ letter_signed (l)
 /* Number of letters in the individual lettered operand.  */
 
 int
-letter_range (l)
-     char l;
+letter_range (char l)
 {
   const struct or32_opcode *pinsn;
   char *enc;
   int range = 0;
   
-  for (pinsn = or32_opcodes; strlen(pinsn->name); pinsn++)
+  for (pinsn = or32_opcodes; strlen (pinsn->name); pinsn ++)
     {
       if (strchr (pinsn->encoding,l))
 	{
-	  for (enc = pinsn->encoding; *enc != '\0'; enc++)
-	    if ((*enc == '0') && (*(enc+1) == 'x'))
+	  for (enc = pinsn->encoding; *enc != '\0'; enc ++)
+	    if ((*enc == '0') && (*(enc + 1) == 'x'))
 	      enc += 2;
 	    else if (*enc == l)
 	      range++;
@@ -422,8 +409,7 @@ insn_index (char *insn)
 }
 
 const char *
-insn_name (index)
-     int index;
+insn_name (int index)
 {
   if (index >= 0 && index < (int) or32_num_opcodes)
     return or32_opcodes[index].name;
@@ -432,17 +418,16 @@ insn_name (index)
 }
 
 void
-l_none ()
+l_none (void)
 {
 }
 
 /* Finite automata for instruction decoding building code.  */
 
 /* Find simbols in encoding.  */
+
 static unsigned long
-insn_extract (param_ch, enc_initial)
-     char param_ch;
-     char *enc_initial;
+insn_extract (char param_ch, char *enc_initial)
 {
   char *enc;
   unsigned long ret = 0;
@@ -475,13 +460,13 @@ insn_extract (param_ch, enc_initial)
   return ret;
 }
 
-#define MAX_AUTOMATA_SIZE (1200)
-#define MAX_OP_TABLE_SIZE (1200)
-#define LEAF_FLAG         (0x80000000)
-#define MAX_LEN           (8)
+#define MAX_AUTOMATA_SIZE  1200
+#define MAX_OP_TABLE_SIZE  1200
+#define LEAF_FLAG          0x80000000
+#define MAX_LEN            8
 
 #ifndef MIN
-# define MIN(x,y)          ((x) < (y) ? (x) : (y))
+#define MIN(x, y)          ((x) < (y) ? (x) : (y))
 #endif
 
 unsigned long *automata;
@@ -501,10 +486,7 @@ struct insn_op_struct *op_data, **op_start;
 /* Recursive utility function used to find best match and to build automata.  */
 
 static unsigned long *
-cover_insn (cur, pass, mask)
-     unsigned long * cur;
-     int pass;
-     unsigned int mask;
+cover_insn (unsigned long * cur, int pass, unsigned int mask)
 {
   int best_first = 0, last_match = -1, ninstr = 0;
   unsigned int best_len = 0;
@@ -544,13 +526,13 @@ cover_insn (cur, pass, mask)
 
 	  for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++)
 	    {
-	      unsigned long m = (1UL << ((unsigned long)len)) - 1;
+	      unsigned long m = (1UL << ((unsigned long) len)) - 1;
 
 	      debug (9, " (%i(%08X & %08X>>%i = %08X, %08X)",
 		     len,m, cur_mask, i, (cur_mask >> (unsigned)i),
-		     (cur_mask >> (unsigned)i) & m);
+		     (cur_mask >> (unsigned) i) & m);
 
-	      if ((m & (cur_mask >> (unsigned)i)) == m)
+	      if ((m & (cur_mask >> (unsigned) i)) == m)
 		{
 		  best_len = len;
 		  best_first = i;
@@ -586,7 +568,7 @@ cover_insn (cur, pass, mask)
 
       /* Allocate space for pointers.  */
       cur += 1 << best_len;
-      cur_mask = (1 << (unsigned long)best_len) - 1;
+      cur_mask = (1 << (unsigned long) best_len) - 1;
       
       for (i = 0; i < ((unsigned) 1 << best_len); i++)
 	{
@@ -622,8 +604,7 @@ cover_insn (cur, pass, mask)
 /* Returns number of nonzero bits.  */
 
 static int
-num_ones (value)
-     unsigned long value;
+num_ones (unsigned long value)
 {
   int c = 0;
 
@@ -636,13 +617,12 @@ num_ones (value)
   return c;
 }
 
-/* Utility function, which converts parameters from or32_opcode format to more binary form.  
-   Parameters are stored in ti struct.  */
+/* Utility function, which converts parameters from or32_opcode
+   format to more binary form.  Parameters are stored in ti struct.  */
 
 static struct insn_op_struct *
-parse_params (opcode, cur)
-     const struct or32_opcode * opcode;
-     struct insn_op_struct * cur;
+parse_params (const struct or32_opcode * opcode,
+	      struct insn_op_struct * cur)
 {
   char *args = opcode->args;
   int i, type;
@@ -705,7 +685,8 @@ parse_params (opcode, cur)
 	}
       else if (*args == '(')
 	{
-	  /* Next param is displacement.  Later we will treat them as one operand.  */
+	  /* Next param is displacement.
+	     Later we will treat them as one operand.  */
 	  cur--;
 	  cur->type = type | cur->type | OPTYPE_DIS | OPTYPE_OP;
 	  debug (9, ">%08X %08X\n", cur->type, cur->data);
@@ -754,14 +735,14 @@ parse_params (opcode, cur)
 /* Constructs new automata based on or32_opcodes array.  */
 
 void
-build_automata ()
+build_automata (void)
 {
   unsigned int i;
   unsigned long *end;
   struct insn_op_struct *cur;
   
-  automata = (unsigned long *) malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
-  ti = (struct temp_insn_struct *) malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes);
+  automata = malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
+  ti = malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes);
 
   nuncovered = or32_num_opcodes;
   printf ("Building automata... ");
@@ -794,8 +775,8 @@ build_automata ()
   printf ("done, num uncovered: %i/%i.\n", nuncovered, or32_num_opcodes);
   printf ("Parsing operands data... ");
 
-  op_data = (struct insn_op_struct *) malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct));
-  op_start = (struct insn_op_struct **) malloc (or32_num_opcodes * sizeof (struct insn_op_struct *));
+  op_data = malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct));
+  op_start = malloc (or32_num_opcodes * sizeof (struct insn_op_struct *));
   cur = op_data;
 
   for (i = 0; i < or32_num_opcodes; i++)
@@ -813,7 +794,7 @@ build_automata ()
 }
 
 void
-destruct_automata ()
+destruct_automata (void)
 {
   free (ti);
   free (automata);
@@ -824,8 +805,7 @@ destruct_automata ()
 /* Decodes instruction and returns instruction index.  */
 
 int
-insn_decode (insn)
-     unsigned int insn;
+insn_decode (unsigned int insn)
 {
   unsigned long *a = automata;
   int i;
@@ -869,9 +849,7 @@ char *disassembled = &disassembled_str[0];
    is proper is figured out from letter description.  */
    
 static unsigned long
-extend_imm (imm, l)
-     unsigned long imm;
-     char l;
+extend_imm (unsigned long imm, char l)
 {
   unsigned long mask;
   int letter_bits;
@@ -890,10 +868,7 @@ extend_imm (imm, l)
 }
 
 static unsigned long
-or32_extract (param_ch, enc_initial, insn)
-     char param_ch;
-     char *enc_initial;
-     unsigned long insn;
+or32_extract (char param_ch, char *enc_initial, unsigned long insn)
 {
   char *enc;
   unsigned long ret = 0;
@@ -972,10 +947,7 @@ or32_extract (param_ch, enc_initial, insn)
 /* Print register. Used only by print_insn.  */
 
 static void
-or32_print_register (param_ch, encoding, insn)
-     char param_ch;
-     char *encoding;
-     unsigned long insn;
+or32_print_register (char param_ch, char *encoding, unsigned long insn)
 {
   int regnum = or32_extract(param_ch, encoding, insn);
   
@@ -985,10 +957,7 @@ or32_print_register (param_ch, encoding, insn)
 /* Print immediate. Used only by print_insn.  */
 
 static void
-or32_print_immediate (param_ch, encoding, insn)
-     char param_ch;
-     char *encoding;
-     unsigned long insn;
+or32_print_immediate (char param_ch, char *encoding, unsigned long insn)
 {
   int imm = or32_extract (param_ch, encoding, insn);
 
@@ -1009,8 +978,7 @@ or32_print_immediate (param_ch, encoding, insn)
    Return the size of the instruction.  */
 
 int
-disassemble_insn (insn)
-     unsigned long insn;
+disassemble_insn (unsigned long insn)
 {
   int index;
   index = insn_decode (insn);
diff --git a/opcodes/pdp11-dis.c b/opcodes/pdp11-dis.c
index 61b00a2..f436e87 100644
--- a/opcodes/pdp11-dis.c
+++ b/opcodes/pdp11-dis.c
@@ -1,19 +1,20 @@
 /* Print DEC PDP-11 instructions.
-   Copyright 2001, 2002, 2004 Free Software Foundation, Inc.
+   Copyright 2001, 2002, 2004, 2005 Free Software Foundation, Inc.
 
-This file is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include "sysdep.h"
 #include "dis-asm.h"
@@ -22,31 +23,17 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 #define AFTER_INSTRUCTION	"\t"
 #define OPERAND_SEPARATOR	", "
 
-#define JUMP	0x1000	/* flag that this operand is used in a jump */
+#define JUMP	0x1000	/* Flag that this operand is used in a jump.  */
 
 #define FPRINTF	(*info->fprintf_func)
 #define F	info->stream
 
-/* sign-extend a 16-bit number in an int */
+/* Sign-extend a 16-bit number in an int.  */
 #define SIGN_BITS	(8 * sizeof (int) - 16)
 #define sign_extend(x) (((x) << SIGN_BITS) >> SIGN_BITS)
 
-static int read_word PARAMS ((bfd_vma memaddr, int *word,
-			      disassemble_info *info));
-static void print_signed_octal PARAMS ((int n, disassemble_info *info));
-static void print_reg PARAMS ((int reg, disassemble_info *info));
-static void print_freg PARAMS ((int freg, disassemble_info *info));
-static int print_operand PARAMS ((bfd_vma *memaddr, int code,
-				  disassemble_info *info));
-static int print_foperand PARAMS ((bfd_vma *memaddr, int code,
-                                   disassemble_info *info));
-int print_insn_pdp11 PARAMS ((bfd_vma memaddr, disassemble_info *info));
-
 static int
-read_word (memaddr, word, info)
-     bfd_vma memaddr;
-     int *word;
-     disassemble_info *info;
+read_word (bfd_vma memaddr, int *word, disassemble_info *info)
 {
   int status;
   bfd_byte x[2];
@@ -60,9 +47,7 @@ read_word (memaddr, word, info)
 }
 
 static void
-print_signed_octal (n, info)
-     int n;
-     disassemble_info *info;
+print_signed_octal (int n, disassemble_info *info)
 {
   if (n < 0)
     FPRINTF (F, "-%o", -n);
@@ -71,11 +56,9 @@ print_signed_octal (n, info)
 }
 
 static void
-print_reg (reg, info)
-     int reg;
-     disassemble_info *info;
+print_reg (int reg, disassemble_info *info)
 {
-  /* mask off the addressing mode, if any */
+  /* Mask off the addressing mode, if any.  */
   reg &= 7;
 
   switch (reg)
@@ -89,18 +72,13 @@ print_reg (reg, info)
 }
 
 static void
-print_freg (freg, info)
-     int freg;
-     disassemble_info *info;
+print_freg (int freg, disassemble_info *info)
 {
   FPRINTF (F, "fr%d", freg);
 }
 
 static int
-print_operand (memaddr, code, info)
-     bfd_vma *memaddr;
-     int code;
-     disassemble_info *info;
+print_operand (bfd_vma *memaddr, int code, disassemble_info *info)
 {
   int mode = (code >> 3) & 7;
   int reg = code & 7;
@@ -120,6 +98,7 @@ print_operand (memaddr, code, info)
       if (reg == 7)
 	{
 	  int data;
+
 	  if (read_word (*memaddr, &data, info) < 0)
 	    return -1;
 	  FPRINTF (F, "$");
@@ -137,6 +116,7 @@ print_operand (memaddr, code, info)
       if (reg == 7)
 	{
 	  int address;
+
 	  if (read_word (*memaddr, &address, info) < 0)
 	    return -1;
 	  FPRINTF (F, "*$%o", address);
@@ -167,6 +147,7 @@ print_operand (memaddr, code, info)
       if (reg == 7)
 	{
 	  bfd_vma address = *memaddr + sign_extend (disp);
+
 	  if (mode == 7)
 	    FPRINTF (F, "*");
 	  if (!(code & JUMP))
@@ -189,10 +170,7 @@ print_operand (memaddr, code, info)
 }
 
 static int
-print_foperand (memaddr, code, info)
-     bfd_vma *memaddr;
-     int code;
-     disassemble_info *info;
+print_foperand (bfd_vma *memaddr, int code, disassemble_info *info)
 {
   int mode = (code >> 3) & 7;
   int reg = code & 7;
@@ -209,9 +187,7 @@ print_foperand (memaddr, code, info)
    on INFO->STREAM.  Returns length of the instruction, in bytes.  */
 
 int
-print_insn_pdp11 (memaddr, info)
-     bfd_vma memaddr;
-     disassemble_info *info;
+print_insn_pdp11 (bfd_vma memaddr, disassemble_info *info)
 {
   bfd_vma start_memaddr = memaddr;
   int opcode;
diff --git a/opcodes/pj-dis.c b/opcodes/pj-dis.c
index 7f918a6..c75644c 100644
--- a/opcodes/pj-dis.c
+++ b/opcodes/pj-dis.c
@@ -1,20 +1,21 @@
 /* pj-dis.c -- Disassemble picoJava instructions.
-   Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2001, 2002, 2005 Free Software Foundation, Inc.
    Contributed by Steve Chamberlain, of Transmeta (sac@pobox.com).
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "sysdep.h"
@@ -23,17 +24,10 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 extern const pj_opc_info_t pj_opc_info[512];
 
-static int get_int PARAMS ((bfd_vma, int *, struct disassemble_info *));
-
-
 static int
-get_int (memaddr, iptr, info)
-     bfd_vma memaddr;
-     int *iptr;
-     struct disassemble_info *info;
+get_int (bfd_vma memaddr, int *iptr, struct disassemble_info *info)
 {
   unsigned char ival[4];
-
   int status = info->read_memory_func (memaddr, ival, 4, info);
 
   *iptr = (ival[0] << 24)
@@ -45,9 +39,7 @@ get_int (memaddr, iptr, info)
 }
 
 int
-print_insn_pj (addr, info)
-     bfd_vma addr;
-     struct disassemble_info *info;
+print_insn_pj (bfd_vma addr, struct disassemble_info *info)
 {
   fprintf_ftype fprintf_fn = info->fprintf_func;
   void *stream = info->stream;
@@ -60,6 +52,7 @@ print_insn_pj (addr, info)
   if (opcode == 0xff)
     {
       unsigned char byte_2;
+
       if ((status = info->read_memory_func (addr + 1, &byte_2, 1, info)))
 	goto fail;
       fprintf_fn (stream, "%s\t", pj_opc_info[opcode + byte_2].u.name);
@@ -71,6 +64,7 @@ print_insn_pj (addr, info)
       int insn_start = addr;
       const pj_opc_info_t *op = &pj_opc_info[opcode];
       int a;
+
       addr++;
       fprintf_fn (stream, "%s", op->u.name);
 
@@ -115,7 +109,6 @@ print_insn_pj (addr, info)
       /* The lookupswitch instruction is followed by the default
 	 address, element count and pairs of values and
 	 addresses.  */
-
       if (strcmp (op->u.name, "lookupswitch") == 0)
 	{
 	  int count;
@@ -149,6 +142,7 @@ print_insn_pj (addr, info)
 	    }
 	  return addr - insn_start;
 	}
+
       for (a = 0; op->arg[a]; a++)
 	{
 	  unsigned char data[4];
diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c
index 240fc56..013c75a 100644
--- a/opcodes/s390-dis.c
+++ b/opcodes/s390-dis.c
@@ -1,5 +1,5 @@
 /* s390-dis.c -- Disassemble S390 instructions
-   Copyright 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+   Copyright 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
    Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
 
    This file is part of GDB, GAS and the GNU binutils.
@@ -29,15 +29,10 @@ static int init_flag = 0;
 static int opc_index[256];
 static int current_arch_mask = 0;
 
-static void init_disasm PARAMS ((struct disassemble_info *));
-static unsigned int s390_extract_operand
-  PARAMS ((unsigned char *, const struct s390_operand *));
-
 /* Set up index table for first opcode byte.  */
 
 static void
-init_disasm (info)
-     struct disassemble_info *info;
+init_disasm (struct disassemble_info *info)
 {
   const struct s390_opcode *opcode;
   const struct s390_opcode *opcode_end;
@@ -68,9 +63,7 @@ init_disasm (info)
 /* Extracts an operand value from an instruction.  */
 
 static inline unsigned int
-s390_extract_operand (insn, operand)
-     unsigned char *insn;
-     const struct s390_operand *operand;
+s390_extract_operand (unsigned char *insn, const struct s390_operand *operand)
 {
   unsigned int val;
   int bits;
@@ -102,7 +95,7 @@ s390_extract_operand (insn, operand)
   if (operand->flags & S390_OPERAND_PCREL)
     val <<= 1;
 
-  /* Length x in an instructions has real length x+1.  */
+  /* Length x in an instructions has real length x + 1.  */
   if (operand->flags & S390_OPERAND_LENGTH)
     val++;
   return val;
@@ -111,9 +104,7 @@ s390_extract_operand (insn, operand)
 /* Print a S390 instruction.  */
 
 int
-print_insn_s390 (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
 {
   bfd_byte buffer[6];
   const struct s390_opcode *opcode;
diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c
index 5381d6a..381fa4d 100644
--- a/opcodes/sh-dis.c
+++ b/opcodes/sh-dis.c
@@ -1,5 +1,5 @@
 /* Disassemble SH instructions.
-   Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004
+   Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
@@ -14,7 +14,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "sysdep.h"
@@ -28,18 +29,12 @@
 #define INCLUDE_SHMEDIA
 #endif
 
-static void print_movxy
-  PARAMS ((const sh_opcode_info *, int, int, fprintf_ftype, void *));
-static void print_insn_ddt PARAMS ((int, struct disassemble_info *));
-static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *));
-static void print_insn_ppi PARAMS ((int, struct disassemble_info *));
-
 static void
-print_movxy (op, rn, rm, fprintf_fn, stream)
-     const sh_opcode_info *op;
-     int rn, rm;
-     fprintf_ftype fprintf_fn;
-     void *stream;
+print_movxy (const sh_opcode_info *op,
+	     int rn,
+	     int rm,
+	     fprintf_ftype fprintf_fn,
+	     void *stream)
 {
   int n;
 
@@ -113,9 +108,7 @@ print_movxy (op, rn, rm, fprintf_fn, stream)
    Return nonzero if a field b of a parallel processing insns follows.  */
 
 static void
-print_insn_ddt (insn, info)
-     int insn;
-     struct disassemble_info *info;
+print_insn_ddt (int insn, struct disassemble_info *info)
 {
   fprintf_ftype fprintf_fn = info->fprintf_func;
   void *stream = info->stream;
@@ -202,10 +195,7 @@ print_insn_ddt (insn, info)
 }
 
 static void
-print_dsp_reg (rm, fprintf_fn, stream)
-     int rm;
-     fprintf_ftype fprintf_fn;
-     void *stream;
+print_dsp_reg (int rm, fprintf_ftype fprintf_fn, void *stream)
 {
   switch (rm)
     {
@@ -246,9 +236,7 @@ print_dsp_reg (rm, fprintf_fn, stream)
 }
 
 static void
-print_insn_ppi (field_b, info)
-     int field_b;
-     struct disassemble_info *info;
+print_insn_ppi (int field_b, struct disassemble_info *info)
 {
   static char *sx_tab[] = { "x0", "x1", "a0", "a1" };
   static char *sy_tab[] = { "y0", "y1", "m0", "m1" };
@@ -275,23 +263,20 @@ print_insn_ppi (field_b, info)
       static char *sg_tab[] = { "m0", "m1", "a0", "a1" };
 
       if (field_b & 0x2000)
-	{
-	  fprintf_fn (stream, "p%s %s,%s,%s\t",
-		      (field_b & 0x1000) ? "add" : "sub",
-		      sx_tab[(field_b >> 6) & 3],
-		      sy_tab[(field_b >> 4) & 3],
-		      du_tab[(field_b >> 0) & 3]);
-	}
+	fprintf_fn (stream, "p%s %s,%s,%s\t",
+		    (field_b & 0x1000) ? "add" : "sub",
+		    sx_tab[(field_b >> 6) & 3],
+		    sy_tab[(field_b >> 4) & 3],
+		    du_tab[(field_b >> 0) & 3]);
+
       else if ((field_b & 0xf0) == 0x10
 	       && info->mach != bfd_mach_sh_dsp
 	       && info->mach != bfd_mach_sh3_dsp)
-	{
-	  fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]);
-	}
+	fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]);
+
       else if ((field_b & 0xf3) != 0)
-	{
-	  fprintf_fn (stream, ".word 0x%x\t", field_b);
-	}
+	fprintf_fn (stream, ".word 0x%x\t", field_b);
+
       fprintf_fn (stream, "pmuls%c%s,%s,%s",
 		  field_b & 0x2000 ? ' ' : '\t',
 		  se_tab[(field_b >> 10) & 3],
@@ -392,10 +377,9 @@ print_insn_ppi (field_b, info)
 
 /* FIXME mvs: movx insns print as ".word 0x%03x", insn & 0xfff
    (ie. the upper nibble is missing).  */
+
 int
-print_insn_sh (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
 {
   fprintf_ftype fprintf_fn = info->fprintf_func;
   void *stream = info->stream;
@@ -648,7 +632,7 @@ print_insn_sh (memaddr, info)
 	    case REG_N_D:
 	      if ((nibs[n] & 1) != 0)
 		goto fail;
-	      /* fall through */
+	      /* Fall through.  */
 	    case REG_N:
 	      rn = nibs[n];
 	      break;
diff --git a/opcodes/sh64-dis.c b/opcodes/sh64-dis.c
index 0835941..0227ab6 100644
--- a/opcodes/sh64-dis.c
+++ b/opcodes/sh64-dis.c
@@ -1,5 +1,5 @@
 /* Disassemble SH64 instructions.
-   Copyright 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+   Copyright 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -21,7 +21,6 @@
 #include "sysdep.h"
 #include "sh64-opc.h"
 #include "libiberty.h"
-
 /* We need to refer to the ELF header structure.  */
 #include "elf-bfd.h"
 #include "elf/sh.h"
@@ -54,18 +53,11 @@ struct sh64_disassemble_info
    Note that some archs have this as a field in the opcode table.  */
 static unsigned long *shmedia_opcode_mask_table;
 
-static void initialize_shmedia_opcode_mask_table PARAMS ((void));
-static int print_insn_shmedia PARAMS ((bfd_vma, disassemble_info *));
-static const char *creg_name PARAMS ((int));
-static bfd_boolean init_sh64_disasm_info PARAMS ((struct disassemble_info *));
-static enum sh64_elf_cr_type sh64_get_contents_type_disasm
-  PARAMS ((bfd_vma, struct disassemble_info *));
-
 /* Initialize the SH64 opcode mask table for each instruction in SHmedia
    mode.  */
 
 static void
-initialize_shmedia_opcode_mask_table ()
+initialize_shmedia_opcode_mask_table (void)
 {
   int n_opc;
   int n;
@@ -163,19 +155,16 @@ initialize_shmedia_opcode_mask_table ()
 
 /* Get a predefined control-register-name, or return NULL.  */
 
-const char *
-creg_name (cregno)
-     int cregno;
+static const char *
+creg_name (int cregno)
 {
   const shmedia_creg_info *cregp;
 
   /* If control register usage is common enough, change this to search a
      hash-table.  */
   for (cregp = shmedia_creg_table; cregp->name != NULL; cregp++)
-    {
-      if (cregp->cregno == cregno)
-	return cregp->name;
-    }
+    if (cregp->cregno == cregno)
+      return cregp->name;
 
   return NULL;
 }
@@ -183,13 +172,10 @@ creg_name (cregno)
 /* Main function to disassemble SHmedia instructions.  */
 
 static int
-print_insn_shmedia (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_shmedia (bfd_vma memaddr, struct disassemble_info *info)
 {
   fprintf_ftype fprintf_fn = info->fprintf_func;
   void *stream = info->stream;
-
   unsigned char insn[4];
   unsigned long instruction;
   int status;
@@ -289,6 +275,7 @@ print_insn_shmedia (memaddr, info)
 	case A_CREG_J:
 	  {
 	    const char *name;
+
 	    r = temp & 0x3f;
 
 	    name = creg_name (r);
@@ -457,9 +444,7 @@ print_insn_shmedia (memaddr, info)
    no section is available.  */
 
 static enum sh64_elf_cr_type
-sh64_get_contents_type_disasm (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+sh64_get_contents_type_disasm (bfd_vma memaddr, struct disassemble_info *info)
 {
   struct sh64_disassemble_info *sh64_infop = info->private_data;
 
@@ -513,8 +498,7 @@ sh64_get_contents_type_disasm (memaddr, info)
 /* Initialize static and dynamic disassembly state.  */
 
 static bfd_boolean
-init_sh64_disasm_info (info)
-     struct disassemble_info *info;
+init_sh64_disasm_info (struct disassemble_info *info)
 {
   struct sh64_disassemble_info *sh64_infop
     = calloc (sizeof (*sh64_infop), 1);
@@ -538,9 +522,7 @@ init_sh64_disasm_info (info)
    use any of the functions further below.  */
 
 int
-print_insn_sh64x_media (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_sh64x_media (bfd_vma memaddr, struct disassemble_info *info)
 {
   if (info->private_data == NULL && ! init_sh64_disasm_info (info))
     return -1;
@@ -556,9 +538,7 @@ print_insn_sh64x_media (memaddr, info)
    If we see an SHcompact instruction, return -2.  */
 
 int
-print_insn_sh64 (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_sh64 (bfd_vma memaddr, struct disassemble_info *info)
 {
   enum bfd_endian endian = info->endian;
   enum sh64_elf_cr_type cr_type;
diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c
index 7f2ede9..1b1748c 100644
--- a/opcodes/sparc-dis.c
+++ b/opcodes/sparc-dis.c
@@ -1,6 +1,6 @@
 /* Print SPARC instructions.
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2002, 2003, 2004 Free Software Foundation, Inc.
+   2000, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -14,7 +14,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <stdio.h>
 
@@ -34,7 +35,7 @@
 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
 
 /* The sorted opcode table.  */
-static const struct sparc_opcode **sorted_opcodes;
+static const sparc_opcode **sorted_opcodes;
 
 /* For faster lookup, after insns are sorted they are hashed.  */
 /* ??? I think there is room for even more improvement.  */
@@ -46,18 +47,13 @@ static const struct sparc_opcode **sorted_opcodes;
 static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
 #define HASH_INSN(INSN) \
   ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
-struct opcode_hash
+typedef struct sparc_opcode_hash
 {
-  struct opcode_hash *next;
-  const struct sparc_opcode *opcode;
-};
-static struct opcode_hash *opcode_hash_table[HASH_SIZE];
+  struct sparc_opcode_hash *next;
+  const sparc_opcode *opcode;
+} sparc_opcode_hash;
 
-static void build_hash_table
-  PARAMS ((const struct sparc_opcode **, struct opcode_hash **, int));
-static int is_delayed_branch PARAMS ((unsigned long));
-static int compare_opcodes PARAMS ((const PTR, const PTR));
-static int compute_arch_mask PARAMS ((unsigned long));
+static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
 
 /* Sign-extend a value which is N bits long.  */
 #define	SEX(value, bits) \
@@ -65,16 +61,16 @@ static int compute_arch_mask PARAMS ((unsigned long));
 			 >> ((8 * sizeof (int)) - bits) )
 
 static  char *reg_names[] =
-{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",	
-  "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",	
-  "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",	
-  "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",	
-  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",	
-  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",	
+{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+  "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
+  "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
+  "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
+  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
-  "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",	
-  "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",	
+  "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
+  "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
   "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
   "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
 /* psr, wim, tbr, fpsr, cpsr are v8 only.  */
@@ -104,21 +100,21 @@ static char *v9a_asr_reg_names[] =
 /* Macros used to extract instruction fields.  Not all fields have
    macros defined here, only those which are actually used.  */
 
-#define X_RD(i) (((i) >> 25) & 0x1f)
-#define X_RS1(i) (((i) >> 14) & 0x1f)
-#define X_LDST_I(i) (((i) >> 13) & 1)
-#define X_ASI(i) (((i) >> 5) & 0xff)
-#define X_RS2(i) (((i) >> 0) & 0x1f)
-#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
-#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
-#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
-#define X_IMM22(i) X_DISP22 (i)
-#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
+#define X_RD(i)      (((i) >> 25) & 0x1f)
+#define X_RS1(i)     (((i) >> 14) & 0x1f)
+#define X_LDST_I(i)  (((i) >> 13) & 1)
+#define X_ASI(i)     (((i) >> 5) & 0xff)
+#define X_RS2(i)     (((i) >> 0) & 0x1f)
+#define X_IMM(i,n)   (((i) >> 0) & ((1 << (n)) - 1))
+#define X_SIMM(i,n)  SEX (X_IMM ((i), (n)), (n))
+#define X_DISP22(i)  (((i) >> 0) & 0x3fffff)
+#define X_IMM22(i)   X_DISP22 (i)
+#define X_DISP30(i)  (((i) >> 0) & 0x3fffffff)
 
 /* These are for v9.  */
-#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
-#define X_DISP19(i) (((i) >> 0) & 0x7ffff)
-#define X_MEMBAR(i) ((i) & 0x7f)
+#define X_DISP16(i)  (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
+#define X_DISP19(i)  (((i) >> 0) & 0x7ffff)
+#define X_MEMBAR(i)  ((i) & 0x7f)
 
 /* Here is the union which was used to extract instruction fields
    before the shift and mask macros were written.
@@ -176,23 +172,22 @@ static char *v9a_asr_reg_names[] =
 	   unsigned int adisp30:30;
 	   #define	disp30	call.adisp30
 	 } call;
-     };
-
-   */
+     };  */
 
 /* Nonzero if INSN is the opcode for a delayed branch.  */
+
 static int
-is_delayed_branch (insn)
-     unsigned long insn;
+is_delayed_branch (unsigned long insn)
 {
-  struct opcode_hash *op;
+  sparc_opcode_hash *op;
 
   for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
     {
-      const struct sparc_opcode *opcode = op->opcode;
+      const sparc_opcode *opcode = op->opcode;
+
       if ((opcode->match & insn) == opcode->match
 	  && (opcode->lose & insn) == 0)
-	return (opcode->flags & F_DELAYED);
+	return opcode->flags & F_DELAYED;
     }
   return 0;
 }
@@ -203,6 +198,236 @@ is_delayed_branch (insn)
    to compare_opcodes.  */
 static unsigned int current_arch_mask;
 
+/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values.  */
+
+static int
+compute_arch_mask (unsigned long mach)
+{
+  switch (mach)
+    {
+    case 0 :
+    case bfd_mach_sparc :
+      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
+    case bfd_mach_sparc_sparclet :
+      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
+    case bfd_mach_sparc_sparclite :
+    case bfd_mach_sparc_sparclite_le :
+      /* sparclites insns are recognized by default (because that's how
+	 they've always been treated, for better or worse).  Kludge this by
+	 indicating generic v8 is also selected.  */
+      return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
+	      | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
+    case bfd_mach_sparc_v8plus :
+    case bfd_mach_sparc_v9 :
+      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
+    case bfd_mach_sparc_v8plusa :
+    case bfd_mach_sparc_v9a :
+      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
+    case bfd_mach_sparc_v8plusb :
+    case bfd_mach_sparc_v9b :
+      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
+    }
+  abort ();
+}
+
+/* Compare opcodes A and B.  */
+
+static int
+compare_opcodes (const void * a, const void * b)
+{
+  sparc_opcode *op0 = * (sparc_opcode **) a;
+  sparc_opcode *op1 = * (sparc_opcode **) b;
+  unsigned long int match0 = op0->match, match1 = op1->match;
+  unsigned long int lose0 = op0->lose, lose1 = op1->lose;
+  register unsigned int i;
+
+  /* If one (and only one) insn isn't supported by the current architecture,
+     prefer the one that is.  If neither are supported, but they're both for
+     the same architecture, continue processing.  Otherwise (both unsupported
+     and for different architectures), prefer lower numbered arch's (fudged
+     by comparing the bitmasks).  */
+  if (op0->architecture & current_arch_mask)
+    {
+      if (! (op1->architecture & current_arch_mask))
+	return -1;
+    }
+  else
+    {
+      if (op1->architecture & current_arch_mask)
+	return 1;
+      else if (op0->architecture != op1->architecture)
+	return op0->architecture - op1->architecture;
+    }
+
+  /* If a bit is set in both match and lose, there is something
+     wrong with the opcode table.  */
+  if (match0 & lose0)
+    {
+      fprintf
+	(stderr,
+	 /* xgettext:c-format */
+	 _("Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
+	 op0->name, match0, lose0);
+      op0->lose &= ~op0->match;
+      lose0 = op0->lose;
+    }
+
+  if (match1 & lose1)
+    {
+      fprintf
+	(stderr,
+	 /* xgettext:c-format */
+	 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
+	 op1->name, match1, lose1);
+      op1->lose &= ~op1->match;
+      lose1 = op1->lose;
+    }
+
+  /* Because the bits that are variable in one opcode are constant in
+     another, it is important to order the opcodes in the right order.  */
+  for (i = 0; i < 32; ++i)
+    {
+      unsigned long int x = 1 << i;
+      int x0 = (match0 & x) != 0;
+      int x1 = (match1 & x) != 0;
+
+      if (x0 != x1)
+	return x1 - x0;
+    }
+
+  for (i = 0; i < 32; ++i)
+    {
+      unsigned long int x = 1 << i;
+      int x0 = (lose0 & x) != 0;
+      int x1 = (lose1 & x) != 0;
+
+      if (x0 != x1)
+	return x1 - x0;
+    }
+
+  /* They are functionally equal.  So as long as the opcode table is
+     valid, we can put whichever one first we want, on aesthetic grounds.  */
+
+  /* Our first aesthetic ground is that aliases defer to real insns.  */
+  {
+    int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
+
+    if (alias_diff != 0)
+      /* Put the one that isn't an alias first.  */
+      return alias_diff;
+  }
+
+  /* Except for aliases, two "identical" instructions had
+     better have the same opcode.  This is a sanity check on the table.  */
+  i = strcmp (op0->name, op1->name);
+  if (i)
+    {
+      if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary.  */
+	return i;
+      else
+	fprintf (stderr,
+		 /* xgettext:c-format */
+		 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
+		 op0->name, op1->name);
+    }
+
+  /* Fewer arguments are preferred.  */
+  {
+    int length_diff = strlen (op0->args) - strlen (op1->args);
+
+    if (length_diff != 0)
+      /* Put the one with fewer arguments first.  */
+      return length_diff;
+  }
+
+  /* Put 1+i before i+1.  */
+  {
+    char *p0 = (char *) strchr (op0->args, '+');
+    char *p1 = (char *) strchr (op1->args, '+');
+
+    if (p0 && p1)
+      {
+	/* There is a plus in both operands.  Note that a plus
+	   sign cannot be the first character in args,
+	   so the following [-1]'s are valid.  */
+	if (p0[-1] == 'i' && p1[1] == 'i')
+	  /* op0 is i+1 and op1 is 1+i, so op1 goes first.  */
+	  return 1;
+	if (p0[1] == 'i' && p1[-1] == 'i')
+	  /* op0 is 1+i and op1 is i+1, so op0 goes first.  */
+	  return -1;
+      }
+  }
+
+  /* Put 1,i before i,1.  */
+  {
+    int i0 = strncmp (op0->args, "i,1", 3) == 0;
+    int i1 = strncmp (op1->args, "i,1", 3) == 0;
+
+    if (i0 ^ i1)
+      return i0 - i1;
+  }
+
+  /* They are, as far as we can tell, identical.
+     Since qsort may have rearranged the table partially, there is
+     no way to tell which one was first in the opcode table as
+     written, so just say there are equal.  */
+  /* ??? This is no longer true now that we sort a vector of pointers,
+     not the table itself.  */
+  return 0;
+}
+
+/* Build a hash table from the opcode table.
+   OPCODE_TABLE is a sorted list of pointers into the opcode table.  */
+
+static void
+build_hash_table (const sparc_opcode **opcode_table,
+		  sparc_opcode_hash **hash_table,
+		  int num_opcodes)
+{
+  int i;
+  int hash_count[HASH_SIZE];
+  static sparc_opcode_hash *hash_buf = NULL;
+
+  /* Start at the end of the table and work backwards so that each
+     chain is sorted.  */
+
+  memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
+  memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
+  if (hash_buf != NULL)
+    free (hash_buf);
+  hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes);
+  for (i = num_opcodes - 1; i >= 0; --i)
+    {
+      int hash = HASH_INSN (opcode_table[i]->match);
+      sparc_opcode_hash *h = &hash_buf[i];
+
+      h->next = hash_table[hash];
+      h->opcode = opcode_table[i];
+      hash_table[hash] = h;
+      ++hash_count[hash];
+    }
+
+#if 0 /* for debugging */
+  {
+    int min_count = num_opcodes, max_count = 0;
+    int total;
+
+    for (i = 0; i < HASH_SIZE; ++i)
+      {
+        if (hash_count[i] < min_count)
+	  min_count = hash_count[i];
+	if (hash_count[i] > max_count)
+	  max_count = hash_count[i];
+	total += hash_count[i];
+      }
+
+    printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
+	    min_count, max_count, (double) total / HASH_SIZE);
+  }
+#endif
+}
+
 /* Print one instruction from MEMADDR on INFO->STREAM.
 
    We suffix the instruction with a comment that gives the absolute
@@ -212,14 +437,12 @@ static unsigned int current_arch_mask;
    on that register.  */
 
 int
-print_insn_sparc (memaddr, info)
-     bfd_vma memaddr;
-     disassemble_info *info;
+print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
 {
   FILE *stream = info->stream;
   bfd_byte buffer[4];
   unsigned long insn;
-  register struct opcode_hash *op;
+  sparc_opcode_hash *op;
   /* Nonzero of opcode table has been initialized.  */
   static int opcodes_initialized = 0;
   /* bfd mach number of last call.  */
@@ -234,8 +457,8 @@ print_insn_sparc (memaddr, info)
       current_arch_mask = compute_arch_mask (info->mach);
 
       if (!opcodes_initialized)
-	sorted_opcodes = (const struct sparc_opcode **)
-	  xmalloc (sparc_num_opcodes * sizeof (struct sparc_opcode *));
+	sorted_opcodes =
+	  xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *));
       /* Reset the sorted table so we can resort it.  */
       for (i = 0; i < sparc_num_opcodes; ++i)
 	sorted_opcodes[i] = &sparc_opcodes[i];
@@ -250,6 +473,7 @@ print_insn_sparc (memaddr, info)
   {
     int status =
       (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
+
     if (status != 0)
       {
 	(*info->memory_error_func) (status, memaddr, info);
@@ -273,7 +497,7 @@ print_insn_sparc (memaddr, info)
 
   for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
     {
-      const struct sparc_opcode *opcode = op->opcode;
+      const sparc_opcode *opcode = op->opcode;
 
       /* If the insn isn't supported by the current architecture, skip it.  */
       if (! (opcode->architecture & current_arch_mask))
@@ -290,7 +514,7 @@ print_insn_sparc (memaddr, info)
 	  /* Nonzero means that we have found a plus sign in the args
 	     field of the opcode table.  */
 	  int found_plus = 0;
-	  
+
 	  /* Nonzero means we have an annulled branch.  */
 	  int is_annulled = 0;
 
@@ -313,7 +537,7 @@ print_insn_sparc (memaddr, info)
 	  (*info->fprintf_func) (stream, opcode->name);
 
 	  {
-	    register const char *s;
+	    const char *s;
 
 	    if (opcode->args[0] != ',')
 	      (*info->fprintf_func) (stream, " ");
@@ -347,13 +571,13 @@ print_insn_sparc (memaddr, info)
 		  }
 
 		(*info->fprintf_func) (stream, " ");
-			
+
 		switch (*s)
 		  {
 		  case '+':
 		    found_plus = 1;
+		    /* Fall through.  */
 
-		    /* note fall-through */
 		  default:
 		    (*info->fprintf_func) (stream, "%c", *s);
 		    break;
@@ -383,24 +607,24 @@ print_insn_sparc (memaddr, info)
 		  case 'e':
 		    freg (X_RS1 (insn));
 		    break;
-		  case 'v':	/* double/even */
-		  case 'V':	/* quad/multiple of 4 */
+		  case 'v':	/* Double/even.  */
+		  case 'V':	/* Quad/multiple of 4.  */
 		    fregx (X_RS1 (insn));
 		    break;
 
 		  case 'f':
 		    freg (X_RS2 (insn));
 		    break;
-		  case 'B':	/* double/even */
-		  case 'R':	/* quad/multiple of 4 */
+		  case 'B':	/* Double/even.  */
+		  case 'R':	/* Quad/multiple of 4.  */
 		    fregx (X_RS2 (insn));
 		    break;
 
 		  case 'g':
 		    freg (X_RD (insn));
 		    break;
-		  case 'H':	/* double/even */
-		  case 'J':	/* quad/multiple of 4 */
+		  case 'H':	/* Double/even.  */
+		  case 'J':	/* Quad/multiple of 4.  */
 		    fregx (X_RD (insn));
 		    break;
 #undef	freg
@@ -426,9 +650,9 @@ print_insn_sparc (memaddr, info)
 					    & ((int) X_IMM22 (insn) << 10)));
 		    break;
 
-		  case 'i':	/* 13 bit immediate */
-		  case 'I':	/* 11 bit immediate */
-		  case 'j':	/* 10 bit immediate */
+		  case 'i':	/* 13 bit immediate.  */
+		  case 'I':	/* 11 bit immediate.  */
+		  case 'j':	/* 10 bit immediate.  */
 		    {
 		      int imm;
 
@@ -448,7 +672,7 @@ print_insn_sparc (memaddr, info)
 			 not before it.  */
 		      if (found_plus)
 			imm_added_to_rs1 = 1;
-		      
+
 		      if (imm <= 9)
 			(*info->fprintf_func) (stream, "%d", imm);
 		      else
@@ -456,8 +680,8 @@ print_insn_sparc (memaddr, info)
 		    }
 		    break;
 
-		  case 'X':	/* 5 bit unsigned immediate */
-		  case 'Y':	/* 6 bit unsigned immediate */
+		  case 'X':	/* 5 bit unsigned immediate.  */
+		  case 'Y':	/* 6 bit unsigned immediate.  */
 		    {
 		      int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
 
@@ -532,7 +756,7 @@ print_insn_sparc (memaddr, info)
 		  case 'o':
 		    (*info->fprintf_func) (stream, "%%asi");
 		    break;
-		    
+
 		  case 'W':
 		    (*info->fprintf_func) (stream, "%%tick");
 		    break;
@@ -585,15 +809,15 @@ print_insn_sparc (memaddr, info)
 			(*info->fprintf_func) (stream, "%d", X_RD (insn));
 		      break;
 		    }
-		    
+
 		  case 'M':
 		    (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
 		    break;
-		    
+
 		  case 'm':
 		    (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
 		    break;
-		    
+
 		  case 'L':
 		    info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
 		    (*info->print_address_func) (info->target, info);
@@ -725,7 +949,7 @@ print_insn_sparc (memaddr, info)
 		      && X_RD (prev_insn) == X_RS1 (insn))
 		    {
 		      (*info->fprintf_func) (stream, "\t! ");
-		      info->target = 
+		      info->target =
 			((unsigned) 0xFFFFFFFF
 			 & ((int) X_IMM22 (prev_insn) << 10));
 		      if (imm_added_to_rs1)
@@ -741,7 +965,7 @@ print_insn_sparc (memaddr, info)
 
 	  if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
 	    {
-		/* FIXME -- check is_annulled flag */
+		/* FIXME -- check is_annulled flag.  */
 	      if (opcode->flags & F_UNBR)
 		info->insn_type = dis_branch;
 	      if (opcode->flags & F_CONDBR)
@@ -760,234 +984,3 @@ print_insn_sparc (memaddr, info)
   (*info->fprintf_func) (stream, _("unknown"));
   return sizeof (buffer);
 }
-
-/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values.  */
-
-static int
-compute_arch_mask (mach)
-     unsigned long mach;
-{
-  switch (mach)
-    {
-    case 0 :
-    case bfd_mach_sparc :
-      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
-    case bfd_mach_sparc_sparclet :
-      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
-    case bfd_mach_sparc_sparclite :
-    case bfd_mach_sparc_sparclite_le :
-      /* sparclites insns are recognized by default (because that's how
-	 they've always been treated, for better or worse).  Kludge this by
-	 indicating generic v8 is also selected.  */
-      return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
-	      | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
-    case bfd_mach_sparc_v8plus :
-    case bfd_mach_sparc_v9 :
-      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
-    case bfd_mach_sparc_v8plusa :
-    case bfd_mach_sparc_v9a :
-      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
-    case bfd_mach_sparc_v8plusb :
-    case bfd_mach_sparc_v9b :
-      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
-    }
-  abort ();
-}
-
-/* Compare opcodes A and B.  */
-
-static int
-compare_opcodes (a, b)
-     const PTR a;
-     const PTR b;
-{
-  struct sparc_opcode *op0 = * (struct sparc_opcode **) a;
-  struct sparc_opcode *op1 = * (struct sparc_opcode **) b;
-  unsigned long int match0 = op0->match, match1 = op1->match;
-  unsigned long int lose0 = op0->lose, lose1 = op1->lose;
-  register unsigned int i;
-
-  /* If one (and only one) insn isn't supported by the current architecture,
-     prefer the one that is.  If neither are supported, but they're both for
-     the same architecture, continue processing.  Otherwise (both unsupported
-     and for different architectures), prefer lower numbered arch's (fudged
-     by comparing the bitmasks).  */
-  if (op0->architecture & current_arch_mask)
-    {
-      if (! (op1->architecture & current_arch_mask))
-	return -1;
-    }
-  else
-    {
-      if (op1->architecture & current_arch_mask)
-	return 1;
-      else if (op0->architecture != op1->architecture)
-	return op0->architecture - op1->architecture;
-    }
-
-  /* If a bit is set in both match and lose, there is something
-     wrong with the opcode table.  */
-  if (match0 & lose0)
-    {
-      fprintf
-	(stderr,
-	 /* xgettext:c-format */
-	 _("Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
-	 op0->name, match0, lose0);
-      op0->lose &= ~op0->match;
-      lose0 = op0->lose;
-    }
-
-  if (match1 & lose1)
-    {
-      fprintf
-	(stderr,
-	 /* xgettext:c-format */
-	 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
-	 op1->name, match1, lose1);
-      op1->lose &= ~op1->match;
-      lose1 = op1->lose;
-    }
-
-  /* Because the bits that are variable in one opcode are constant in
-     another, it is important to order the opcodes in the right order.  */
-  for (i = 0; i < 32; ++i)
-    {
-      unsigned long int x = 1 << i;
-      int x0 = (match0 & x) != 0;
-      int x1 = (match1 & x) != 0;
-
-      if (x0 != x1)
-	return x1 - x0;
-    }
-
-  for (i = 0; i < 32; ++i)
-    {
-      unsigned long int x = 1 << i;
-      int x0 = (lose0 & x) != 0;
-      int x1 = (lose1 & x) != 0;
-
-      if (x0 != x1)
-	return x1 - x0;
-    }
-
-  /* They are functionally equal.  So as long as the opcode table is
-     valid, we can put whichever one first we want, on aesthetic grounds.  */
-
-  /* Our first aesthetic ground is that aliases defer to real insns.  */
-  {
-    int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
-    if (alias_diff != 0)
-      /* Put the one that isn't an alias first.  */
-      return alias_diff;
-  }
-
-  /* Except for aliases, two "identical" instructions had
-     better have the same opcode.  This is a sanity check on the table.  */
-  i = strcmp (op0->name, op1->name);
-  if (i)
-    {
-      if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
-	return i;
-      else
-	fprintf (stderr,
-		 /* xgettext:c-format */
-		 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
-		 op0->name, op1->name);
-    }
-
-  /* Fewer arguments are preferred.  */
-  {
-    int length_diff = strlen (op0->args) - strlen (op1->args);
-    if (length_diff != 0)
-      /* Put the one with fewer arguments first.  */
-      return length_diff;
-  }
-
-  /* Put 1+i before i+1.  */
-  {
-    char *p0 = (char *) strchr (op0->args, '+');
-    char *p1 = (char *) strchr (op1->args, '+');
-
-    if (p0 && p1)
-      {
-	/* There is a plus in both operands.  Note that a plus
-	   sign cannot be the first character in args,
-	   so the following [-1]'s are valid.  */
-	if (p0[-1] == 'i' && p1[1] == 'i')
-	  /* op0 is i+1 and op1 is 1+i, so op1 goes first.  */
-	  return 1;
-	if (p0[1] == 'i' && p1[-1] == 'i')
-	  /* op0 is 1+i and op1 is i+1, so op0 goes first.  */
-	  return -1;
-      }
-  }
-
-  /* Put 1,i before i,1.  */
-  {
-    int i0 = strncmp (op0->args, "i,1", 3) == 0;
-    int i1 = strncmp (op1->args, "i,1", 3) == 0;
-
-    if (i0 ^ i1)
-      return i0 - i1;
-  }
-
-  /* They are, as far as we can tell, identical.
-     Since qsort may have rearranged the table partially, there is
-     no way to tell which one was first in the opcode table as
-     written, so just say there are equal.  */
-  /* ??? This is no longer true now that we sort a vector of pointers,
-     not the table itself.  */
-  return 0;
-}
-
-/* Build a hash table from the opcode table.
-   OPCODE_TABLE is a sorted list of pointers into the opcode table.  */
-
-static void
-build_hash_table (opcode_table, hash_table, num_opcodes)
-     const struct sparc_opcode **opcode_table;
-     struct opcode_hash **hash_table;
-     int num_opcodes;
-{
-  register int i;
-  int hash_count[HASH_SIZE];
-  static struct opcode_hash *hash_buf = NULL;
-
-  /* Start at the end of the table and work backwards so that each
-     chain is sorted.  */
-
-  memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
-  memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
-  if (hash_buf != NULL)
-    free (hash_buf);
-  hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) * num_opcodes);
-  for (i = num_opcodes - 1; i >= 0; --i)
-    {
-      register int hash = HASH_INSN (opcode_table[i]->match);
-      register struct opcode_hash *h = &hash_buf[i];
-      h->next = hash_table[hash];
-      h->opcode = opcode_table[i];
-      hash_table[hash] = h;
-      ++hash_count[hash];
-    }
-
-#if 0 /* for debugging */
-  {
-    int min_count = num_opcodes, max_count = 0;
-    int total;
-
-    for (i = 0; i < HASH_SIZE; ++i)
-      {
-        if (hash_count[i] < min_count)
-	  min_count = hash_count[i];
-	if (hash_count[i] > max_count)
-	  max_count = hash_count[i];
-	total += hash_count[i];
-      }
-
-    printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
-	    min_count, max_count, (double) total / HASH_SIZE);
-  }
-#endif
-}
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 3457ed1..21bfc7e 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -1,24 +1,24 @@
 /* Table of opcodes for the sparc.
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2002, 2004
+   2000, 2002, 2004, 2005
    Free Software Foundation, Inc.
 
-This file is part of the BFD library.
+   This file is part of the BFD library.
 
-BFD is free software; you can redistribute it and/or modify it under
-the terms of the GNU General Public License as published by the Free
-Software Foundation; either version 2, or (at your option) any later
-version.
+   BFD is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 2, or (at your option) any later
+   version.
 
-BFD is distributed in the hope that it will be useful, but WITHOUT ANY
-WARRANTY; without even the implied warranty of MERCHANTABILITY or
-FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-for more details.
+   BFD is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+   for more details.
 
-You should have received a copy of the GNU General Public License
-along with this software; see the file COPYING.  If not, write to
-the Free Software Foundation, 51 Franklin Street - Fifth Floor,
-Boston, MA 02110-1301, USA.	*/
+   You should have received a copy of the GNU General Public License
+   along with this software; see the file COPYING.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.	*/
 
 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
    instruction's name rather than the args.  This would make gas faster, pinsn
@@ -42,7 +42,7 @@ Boston, MA 02110-1301, USA.	*/
 
 #define v6		(MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
 			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
-/* v6 insns not supported on the sparclet */
+/* v6 insns not supported on the sparclet.  */
 #define v6notlet	(MASK_V6 | MASK_V7 | MASK_V8 \
 			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
 #define v7		(MASK_V7 | MASK_V8 | MASK_SPARCLET \
@@ -60,17 +60,18 @@ Boston, MA 02110-1301, USA.	*/
 #define v9		(MASK_V9 | MASK_V9A | MASK_V9B)
 #define v9a		(MASK_V9A | MASK_V9B)
 #define v9b		(MASK_V9B)
-/* v6 insns not supported by v9 */
+/* v6 insns not supported by v9.  */
 #define v6notv9		(MASK_V6 | MASK_V7 | MASK_V8 \
 			 | MASK_SPARCLET | MASK_SPARCLITE)
 /* v9a instructions which would appear to be aliases to v9's impdep's
-   otherwise */
+   otherwise.  */
 #define v9notv9a	(MASK_V9)
 
 /* Table of opcode architectures.
    The order is defined in opcode/sparc.h.  */
 
-const struct sparc_opcode_arch sparc_opcode_archs[] = {
+const struct sparc_opcode_arch sparc_opcode_archs[] =
+{
   { "v6", MASK_V6 },
   { "v7", MASK_V6 | MASK_V7 },
   { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
@@ -88,84 +89,79 @@ const struct sparc_opcode_arch sparc_opcode_archs[] = {
 /* Given NAME, return it's architecture entry.  */
 
 enum sparc_opcode_arch_val
-sparc_opcode_lookup_arch (name)
-     const char *name;
+sparc_opcode_lookup_arch (const char *name)
 {
   const struct sparc_opcode_arch *p;
 
   for (p = &sparc_opcode_archs[0]; p->name; ++p)
-    {
-      if (strcmp (name, p->name) == 0)
-	return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]);
-    }
+    if (strcmp (name, p->name) == 0)
+      return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]);
 
   return SPARC_OPCODE_ARCH_BAD;
 }
 
 /* Branch condition field.  */
-#define COND(x)		(((x)&0xf)<<25)
+#define COND(x)		(((x) & 0xf) << 25)
 
 /* v9: Move (MOVcc and FMOVcc) condition field.  */
-#define MCOND(x,i_or_f)	((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 */
+#define MCOND(x,i_or_f)	((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */
 
 /* v9: Move register (MOVRcc and FMOVRcc) condition field.  */
-#define RCOND(x)	(((x)&0x7)<<10)	/* v9 */
-
-#define CONDA	(COND(0x8))
-#define CONDCC	(COND(0xd))
-#define CONDCS	(COND(0x5))
-#define CONDE	(COND(0x1))
-#define CONDG	(COND(0xa))
-#define CONDGE	(COND(0xb))
-#define CONDGU	(COND(0xc))
-#define CONDL	(COND(0x3))
-#define CONDLE	(COND(0x2))
-#define CONDLEU	(COND(0x4))
-#define CONDN	(COND(0x0))
-#define CONDNE	(COND(0x9))
-#define CONDNEG	(COND(0x6))
-#define CONDPOS	(COND(0xe))
-#define CONDVC	(COND(0xf))
-#define CONDVS	(COND(0x7))
+#define RCOND(x)	(((x) & 0x7) << 10)	/* v9 */
+
+#define CONDA	(COND (0x8))
+#define CONDCC	(COND (0xd))
+#define CONDCS	(COND (0x5))
+#define CONDE	(COND (0x1))
+#define CONDG	(COND (0xa))
+#define CONDGE	(COND (0xb))
+#define CONDGU	(COND (0xc))
+#define CONDL	(COND (0x3))
+#define CONDLE	(COND (0x2))
+#define CONDLEU	(COND (0x4))
+#define CONDN	(COND (0x0))
+#define CONDNE	(COND (0x9))
+#define CONDNEG	(COND (0x6))
+#define CONDPOS	(COND (0xe))
+#define CONDVC	(COND (0xf))
+#define CONDVS	(COND (0x7))
 
 #define CONDNZ	CONDNE
 #define CONDZ	CONDE
 #define CONDGEU	CONDCC
 #define CONDLU	CONDCS
 
-#define FCONDA		(COND(0x8))
-#define FCONDE		(COND(0x9))
-#define FCONDG		(COND(0x6))
-#define FCONDGE		(COND(0xb))
-#define FCONDL		(COND(0x4))
-#define FCONDLE		(COND(0xd))
-#define FCONDLG		(COND(0x2))
-#define FCONDN		(COND(0x0))
-#define FCONDNE		(COND(0x1))
-#define FCONDO		(COND(0xf))
-#define FCONDU		(COND(0x7))
-#define FCONDUE		(COND(0xa))
-#define FCONDUG		(COND(0x5))
-#define FCONDUGE	(COND(0xc))
-#define FCONDUL		(COND(0x3))
-#define FCONDULE	(COND(0xe))
+#define FCONDA		(COND (0x8))
+#define FCONDE		(COND (0x9))
+#define FCONDG		(COND (0x6))
+#define FCONDGE		(COND (0xb))
+#define FCONDL		(COND (0x4))
+#define FCONDLE		(COND (0xd))
+#define FCONDLG		(COND (0x2))
+#define FCONDN		(COND (0x0))
+#define FCONDNE		(COND (0x1))
+#define FCONDO		(COND (0xf))
+#define FCONDU		(COND (0x7))
+#define FCONDUE		(COND (0xa))
+#define FCONDUG		(COND (0x5))
+#define FCONDUGE	(COND (0xc))
+#define FCONDUL		(COND (0x3))
+#define FCONDULE	(COND (0xe))
 
 #define FCONDNZ	FCONDNE
 #define FCONDZ	FCONDE
 
-#define ICC (0)	/* v9 */
-#define XCC (1<<12) /* v9 */
-#define FCC(x)	(((x)&0x3)<<11) /* v9 */
-#define FBFCC(x)	(((x)&0x3)<<20)	/* v9 */
+#define ICC 		(0)	/* v9 */
+#define XCC 		(1 << 12) /* v9 */
+#define FCC(x)		(((x) & 0x3) << 11) /* v9 */
+#define FBFCC(x)	(((x) & 0x3) << 20)	/* v9 */
 
 /* The order of the opcodes in the table is significant:
-	
+
 	* The assembler requires that all instances of the same mnemonic must
 	be consecutive.	If they aren't, the assembler will bomb at runtime.
 
-	* The disassembler should not care about the order of the opcodes.
-
-*/
+	* The disassembler should not care about the order of the opcodes.  */
 
 /* Entries for commutative arithmetic operations.  */
 /* ??? More entries can make use of this.  */
@@ -1348,13 +1344,13 @@ fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags)
 
 /* Coprocessor branches.  */
 #define CBR(opcode, mask, lose, flags, arch) \
- { opcode, (mask), ANNUL|(lose), "l",    flags|F_DELAYED, arch }, \
- { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, arch }
+ { opcode, (mask), ANNUL | (lose), "l",    flags | F_DELAYED, arch }, \
+ { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, arch }
 
 /* Floating point branches.  */
 #define FBR(opcode, mask, lose, flags) \
- { opcode, (mask), ANNUL|(lose), "l",    flags|F_DELAYED|F_FBR, v6 }, \
- { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED|F_FBR, v6 }
+ { opcode, (mask), ANNUL | (lose), "l",    flags | F_DELAYED | F_FBR, v6 }, \
+ { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, v6 }
 
 /* V9 extended floating point branches.  */
 #define FBRX(opcode, mask, lose, flags) /* v9 */ \
@@ -1829,13 +1825,8 @@ typedef struct
 
 /* Look up NAME in TABLE.  */
 
-static int lookup_name PARAMS ((const arg *, const char *));
-static const char *lookup_value PARAMS ((const arg *, int));
-
 static int
-lookup_name (table, name)
-     const arg *table;
-     const char *name;
+lookup_name (const arg *table, const char *name)
 {
   const arg *p;
 
@@ -1849,9 +1840,7 @@ lookup_name (table, name)
 /* Look up VALUE in TABLE.  */
 
 static const char *
-lookup_value (table, value)
-     const arg *table;
-     int value;
+lookup_value (const arg *table, int value)
 {
   const arg *p;
 
@@ -1859,7 +1848,7 @@ lookup_value (table, value)
     if (value == p->value)
       return p->name;
 
-  return (char *) 0;
+  return NULL;
 }
 
 /* Handle ASI's.  */
@@ -1907,8 +1896,7 @@ static arg asi_table[] =
 /* Return the value for ASI NAME, or -1 if not found.  */
 
 int
-sparc_encode_asi (name)
-     const char *name;
+sparc_encode_asi (const char *name)
 {
   return lookup_name (asi_table, name);
 }
@@ -1916,8 +1904,7 @@ sparc_encode_asi (name)
 /* Return the name for ASI value VALUE or NULL if not found.  */
 
 const char *
-sparc_decode_asi (value)
-     int value;
+sparc_decode_asi (int value)
 {
   return lookup_value (asi_table, value);
 }
@@ -1939,8 +1926,7 @@ static arg membar_table[] =
 /* Return the value for membar arg NAME, or -1 if not found.  */
 
 int
-sparc_encode_membar (name)
-     const char *name;
+sparc_encode_membar (const char *name)
 {
   return lookup_name (membar_table, name);
 }
@@ -1948,8 +1934,7 @@ sparc_encode_membar (name)
 /* Return the name for membar value VALUE or NULL if not found.  */
 
 const char *
-sparc_decode_membar (value)
-     int value;
+sparc_decode_membar (int value)
 {
   return lookup_value (membar_table, value);
 }
@@ -1970,8 +1955,7 @@ static arg prefetch_table[] =
 /* Return the value for prefetch arg NAME, or -1 if not found.  */
 
 int
-sparc_encode_prefetch (name)
-     const char *name;
+sparc_encode_prefetch (const char *name)
 {
   return lookup_name (prefetch_table, name);
 }
@@ -1979,8 +1963,7 @@ sparc_encode_prefetch (name)
 /* Return the name for prefetch value VALUE or NULL if not found.  */
 
 const char *
-sparc_decode_prefetch (value)
-     int value;
+sparc_decode_prefetch (int value)
 {
   return lookup_value (prefetch_table, value);
 }
@@ -2002,8 +1985,7 @@ static arg sparclet_cpreg_table[] =
 /* Return the value for sparclet cpreg arg NAME, or -1 if not found.  */
 
 int
-sparc_encode_sparclet_cpreg (name)
-     const char *name;
+sparc_encode_sparclet_cpreg (const char *name)
 {
   return lookup_name (sparclet_cpreg_table, name);
 }
@@ -2011,8 +1993,7 @@ sparc_encode_sparclet_cpreg (name)
 /* Return the name for sparclet cpreg value VALUE or NULL if not found.  */
 
 const char *
-sparc_decode_sparclet_cpreg (value)
-     int value;
+sparc_decode_sparclet_cpreg (int value)
 {
   return lookup_value (sparclet_cpreg_table, value);
 }
diff --git a/opcodes/sysdep.h b/opcodes/sysdep.h
index d352379..4f1efb2 100644
--- a/opcodes/sysdep.h
+++ b/opcodes/sysdep.h
@@ -2,21 +2,22 @@
    Copyright 1995, 1997, 2000 Free Software Foundation, Inc.
    Written by Ken Raeburn.
 
-This file is part of libopcodes, the opcodes library.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   This file is part of libopcodes, the opcodes library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 /* Do system-dependent stuff, mainly driven by autoconf-detected info.
 
diff --git a/opcodes/tic30-dis.c b/opcodes/tic30-dis.c
index 8373403..eac6c45 100644
--- a/opcodes/tic30-dis.c
+++ b/opcodes/tic30-dis.c
@@ -1,5 +1,5 @@
 /* Disassembly routines for TMS320C30 architecture
-   Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
+   Copyright 1998, 1999, 2000, 2002, 2005 Free Software Foundation, Inc.
    Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
 
    This program is free software; you can redistribute it and/or modify
@@ -66,63 +66,8 @@ struct instruction
   partemplate *ptm;
 };
 
-int get_tic30_instruction PARAMS ((unsigned long, struct instruction *));
-int print_two_operand
-  PARAMS ((disassemble_info *, unsigned long, struct instruction *));
-int print_three_operand
-  PARAMS ((disassemble_info *, unsigned long, struct instruction *));
-int print_par_insn
-  PARAMS ((disassemble_info *, unsigned long, struct instruction *));
-int print_branch
-  PARAMS ((disassemble_info *, unsigned long, struct instruction *));
-int get_indirect_operand PARAMS ((unsigned short, int, char *));
-int get_register_operand PARAMS ((unsigned char, char *));
-int cnvt_tmsfloat_ieee PARAMS ((unsigned long, int, float *));
-
-int
-print_insn_tic30 (pc, info)
-     bfd_vma pc;
-     disassemble_info *info;
-{
-  unsigned long insn_word;
-  struct instruction insn = { 0, NULL, NULL };
-  bfd_vma bufaddr = pc - info->buffer_vma;
-  /* Obtain the current instruction word from the buffer.  */
-  insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) |
-    (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3);
-  _pc = pc / 4;
-  /* Get the instruction refered to by the current instruction word
-     and print it out based on its type.  */
-  if (!get_tic30_instruction (insn_word, &insn))
-    return -1;
-  switch (GET_TYPE (insn_word))
-    {
-    case TWO_OPERAND_1:
-    case TWO_OPERAND_2:
-      if (!print_two_operand (info, insn_word, &insn))
-	return -1;
-      break;
-    case THREE_OPERAND:
-      if (!print_three_operand (info, insn_word, &insn))
-	return -1;
-      break;
-    case PAR_STORE:
-    case MUL_ADDS:
-      if (!print_par_insn (info, insn_word, &insn))
-	return -1;
-      break;
-    case BRANCHES:
-      if (!print_branch (info, insn_word, &insn))
-	return -1;
-      break;
-    }
-  return 4;
-}
-
-int
-get_tic30_instruction (insn_word, insn)
-     unsigned long insn_word;
-     struct instruction *insn;
+static int
+get_tic30_instruction (unsigned long insn_word, struct instruction *insn)
 {
   switch (GET_TYPE (insn_word))
     {
@@ -132,6 +77,7 @@ get_tic30_instruction (insn_word, insn)
       insn->type = NORMAL_INSN;
       {
 	template *current_optab = (template *) tic30_optab;
+
 	for (; current_optab < tic30_optab_end; current_optab++)
 	  {
 	    if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
@@ -153,15 +99,18 @@ get_tic30_instruction (insn_word, insn)
 	  }
       }
       break;
+
     case PAR_STORE:
       insn->type = PARALLEL_INSN;
       {
 	partemplate *current_optab = (partemplate *) tic30_paroptab;
+
 	for (; current_optab < tic30_paroptab_end; current_optab++)
 	  {
 	    if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
 	      {
-		if ((current_optab->base_opcode & PAR_STORE_IDEN) == (insn_word & PAR_STORE_IDEN))
+		if ((current_optab->base_opcode & PAR_STORE_IDEN)
+		    == (insn_word & PAR_STORE_IDEN))
 		  {
 		    insn->ptm = current_optab;
 		    break;
@@ -170,15 +119,18 @@ get_tic30_instruction (insn_word, insn)
 	  }
       }
       break;
+
     case MUL_ADDS:
       insn->type = PARALLEL_INSN;
       {
 	partemplate *current_optab = (partemplate *) tic30_paroptab;
+
 	for (; current_optab < tic30_paroptab_end; current_optab++)
 	  {
 	    if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
 	      {
-		if ((current_optab->base_opcode & MUL_ADD_IDEN) == (insn_word & MUL_ADD_IDEN))
+		if ((current_optab->base_opcode & MUL_ADD_IDEN)
+		    == (insn_word & MUL_ADD_IDEN))
 		  {
 		    insn->ptm = current_optab;
 		    break;
@@ -187,17 +139,20 @@ get_tic30_instruction (insn_word, insn)
 	  }
       }
       break;
+
     case BRANCHES:
       insn->type = NORMAL_INSN;
       {
 	template *current_optab = (template *) tic30_optab;
+
 	for (; current_optab < tic30_optab_end; current_optab++)
 	  {
 	    if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
 	      {
 		if (current_optab->operand_types[0] & Imm24)
 		  {
-		    if ((current_optab->base_opcode & BR_IMM_IDEN) == (insn_word & BR_IMM_IDEN))
+		    if ((current_optab->base_opcode & BR_IMM_IDEN)
+			== (insn_word & BR_IMM_IDEN))
 		      {
 			insn->tm = current_optab;
 			break;
@@ -205,7 +160,8 @@ get_tic30_instruction (insn_word, insn)
 		  }
 		else if (current_optab->operands > 0)
 		  {
-		    if ((current_optab->base_opcode & BR_COND_IDEN) == (insn_word & BR_COND_IDEN))
+		    if ((current_optab->base_opcode & BR_COND_IDEN)
+			== (insn_word & BR_COND_IDEN))
 		      {
 			insn->tm = current_optab;
 			break;
@@ -213,7 +169,8 @@ get_tic30_instruction (insn_word, insn)
 		  }
 		else
 		  {
-		    if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000)) == (insn_word & (BR_COND_IDEN | 0x00800000)))
+		    if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000))
+			== (insn_word & (BR_COND_IDEN | 0x00800000)))
 		      {
 			insn->tm = current_optab;
 			break;
@@ -229,17 +186,156 @@ get_tic30_instruction (insn_word, insn)
   return 1;
 }
 
-int
-print_two_operand (info, insn_word, insn)
-     disassemble_info *info;
-     unsigned long insn_word;
-     struct instruction *insn;
+static int
+get_register_operand (unsigned char fragment, char *buffer)
+{
+  const reg *current_reg = tic30_regtab;
+
+  if (buffer == NULL)
+    return 0;
+  for (; current_reg < tic30_regtab_end; current_reg++)
+    {
+      if ((fragment & 0x1F) == current_reg->opcode)
+	{
+	  strcpy (buffer, current_reg->name);
+	  return 1;
+	}
+    }
+  return 0;
+}
+
+static int
+get_indirect_operand (unsigned short fragment,
+		      int size,
+		      char *buffer)
+{
+  unsigned char mod;
+  unsigned arnum;
+  unsigned char disp;
+
+  if (buffer == NULL)
+    return 0;
+  /* Determine which bits identify the sections of the indirect
+     operand based on the size in bytes.  */
+  switch (size)
+    {
+    case 1:
+      mod = (fragment & 0x00F8) >> 3;
+      arnum = (fragment & 0x0007);
+      disp = 0;
+      break;
+    case 2:
+      mod = (fragment & 0xF800) >> 11;
+      arnum = (fragment & 0x0700) >> 8;
+      disp = (fragment & 0x00FF);
+      break;
+    default:
+      return 0;
+    }
+  {
+    const ind_addr_type *current_ind = tic30_indaddr_tab;
+
+    for (; current_ind < tic30_indaddrtab_end; current_ind++)
+      {
+	if (current_ind->modfield == mod)
+	  {
+	    if (current_ind->displacement == IMPLIED_DISP && size == 2)
+	      continue;
+
+	    else
+	      {
+		size_t i, len;
+		int bufcnt;
+
+		len = strlen (current_ind->syntax);
+		for (i = 0, bufcnt = 0; i < len; i++, bufcnt++)
+		  {
+		    buffer[bufcnt] = current_ind->syntax[i];
+		    if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r')
+		      buffer[++bufcnt] = arnum + '0';
+		    if (buffer[bufcnt] == '('
+			&& current_ind->displacement == DISP_REQUIRED)
+		      {
+			sprintf (&buffer[bufcnt + 1], "%u", disp);
+			bufcnt += strlen (&buffer[bufcnt + 1]);
+		      }
+		  }
+		buffer[bufcnt + 1] = '\0';
+		break;
+	      }
+	  }
+      }
+  }
+  return 1;
+}
+
+static int
+cnvt_tmsfloat_ieee (unsigned long tmsfloat, int size, float *ieeefloat)
+{
+  unsigned long exp, sign, mant;
+  union
+  {
+    unsigned long l;
+    float f;
+  } val;
+
+  if (size == 2)
+    {
+      if ((tmsfloat & 0x0000F000) == 0x00008000)
+	tmsfloat = 0x80000000;
+      else
+	{
+	  tmsfloat <<= 16;
+	  tmsfloat = (long) tmsfloat >> 4;
+	}
+    }
+  exp = tmsfloat & 0xFF000000;
+  if (exp == 0x80000000)
+    {
+      *ieeefloat = 0.0;
+      return 1;
+    }
+  exp += 0x7F000000;
+  sign = (tmsfloat & 0x00800000) << 8;
+  mant = tmsfloat & 0x007FFFFF;
+  if (exp == 0xFF000000)
+    {
+      if (mant == 0)
+	*ieeefloat = ERANGE;
+      if (sign == 0)
+	*ieeefloat = 1.0 / 0.0;
+      else
+	*ieeefloat = -1.0 / 0.0;
+      return 1;
+    }
+  exp >>= 1;
+  if (sign)
+    {
+      mant = (~mant) & 0x007FFFFF;
+      mant += 1;
+      exp += mant & 0x00800000;
+      exp &= 0x7F800000;
+      mant &= 0x007FFFFF;
+    }
+  if (tmsfloat == 0x80000000)
+    sign = mant = exp = 0;
+  tmsfloat = sign | exp | mant;
+  val.l = tmsfloat;
+  *ieeefloat = val.f;
+  return 1;
+}
+
+static int
+print_two_operand (disassemble_info *info,
+		   unsigned long insn_word,
+		   struct instruction *insn)
 {
   char name[12];
   char operand[2][13] =
   {
     {0},
-    {0}};
+    {0}
+  };
   float f_number;
 
   if (insn->tm == NULL)
@@ -249,7 +345,8 @@ print_two_operand (info, insn_word, insn)
     {
       int src_op, dest_op;
       /* Determine whether instruction is a store or a normal instruction.  */
-      if ((insn->tm->operand_types[1] & (Direct | Indirect)) == (Direct | Indirect))
+      if ((insn->tm->operand_types[1] & (Direct | Indirect))
+	  == (Direct | Indirect))
 	{
 	  src_op = 1;
 	  dest_op = 0;
@@ -306,9 +403,7 @@ print_two_operand (info, insn_word, insn)
   else if (insn->tm->operands == 1)
     {
       if (insn->tm->opcode_modifier == StackOp)
-	{
-	  get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]);
-	}
+	get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]);
     }
   /* Output instruction to stream.  */
   info->fprintf_func (info->stream, "   %s %s%c%s", name,
@@ -318,17 +413,17 @@ print_two_operand (info, insn_word, insn)
   return 1;
 }
 
-int
-print_three_operand (info, insn_word, insn)
-     disassemble_info *info;
-     unsigned long insn_word;
-     struct instruction *insn;
+static int
+print_three_operand (disassemble_info *info,
+		     unsigned long insn_word,
+		     struct instruction *insn)
 {
   char operand[3][13] =
   {
     {0},
     {0},
-    {0}};
+    {0}
+  };
 
   if (insn->tm == NULL)
     return 0;
@@ -362,11 +457,10 @@ print_three_operand (info, insn_word, insn)
   return 1;
 }
 
-int
-print_par_insn (info, insn_word, insn)
-     disassemble_info *info;
-     unsigned long insn_word;
-     struct instruction *insn;
+static int
+print_par_insn (disassemble_info *info,
+		unsigned long insn_word,
+		struct instruction *insn)
 {
   size_t i, len;
   char *name1, *name2;
@@ -375,11 +469,14 @@ print_par_insn (info, insn_word, insn)
     {
       {0},
       {0},
-      {0}},
+      {0}
+    },
     {
       {0},
       {0},
-      {0}}};
+      {0}
+    }
+  };
 
   if (insn->ptm == NULL)
     return 0;
@@ -484,16 +581,16 @@ print_par_insn (info, insn_word, insn)
   return 1;
 }
 
-int
-print_branch (info, insn_word, insn)
-     disassemble_info *info;
-     unsigned long insn_word;
-     struct instruction *insn;
+static int
+print_branch (disassemble_info *info,
+	      unsigned long insn_word,
+	      struct instruction *insn)
 {
   char operand[2][13] =
   {
     {0},
-    {0}};
+    {0}
+  };
   unsigned long address;
   int print_label = 0;
 
@@ -571,145 +668,40 @@ print_branch (info, insn_word, insn)
 }
 
 int
-get_indirect_operand (fragment, size, buffer)
-     unsigned short fragment;
-     int size;
-     char *buffer;
+print_insn_tic30 (bfd_vma pc, disassemble_info *info)
 {
-  unsigned char mod;
-  unsigned arnum;
-  unsigned char disp;
+  unsigned long insn_word;
+  struct instruction insn = { 0, NULL, NULL };
+  bfd_vma bufaddr = pc - info->buffer_vma;
 
-  if (buffer == NULL)
-    return 0;
-  /* Determine which bits identify the sections of the indirect
-     operand based on the size in bytes.  */
-  switch (size)
+  /* Obtain the current instruction word from the buffer.  */
+  insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) |
+    (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3);
+  _pc = pc / 4;
+  /* Get the instruction refered to by the current instruction word
+     and print it out based on its type.  */
+  if (!get_tic30_instruction (insn_word, &insn))
+    return -1;
+  switch (GET_TYPE (insn_word))
     {
-    case 1:
-      mod = (fragment & 0x00F8) >> 3;
-      arnum = (fragment & 0x0007);
-      disp = 0;
+    case TWO_OPERAND_1:
+    case TWO_OPERAND_2:
+      if (!print_two_operand (info, insn_word, &insn))
+	return -1;
       break;
-    case 2:
-      mod = (fragment & 0xF800) >> 11;
-      arnum = (fragment & 0x0700) >> 8;
-      disp = (fragment & 0x00FF);
+    case THREE_OPERAND:
+      if (!print_three_operand (info, insn_word, &insn))
+	return -1;
+      break;
+    case PAR_STORE:
+    case MUL_ADDS:
+      if (!print_par_insn (info, insn_word, &insn))
+	return -1;
+      break;
+    case BRANCHES:
+      if (!print_branch (info, insn_word, &insn))
+	return -1;
       break;
-    default:
-      return 0;
-    }
-  {
-    const ind_addr_type *current_ind = tic30_indaddr_tab;
-    for (; current_ind < tic30_indaddrtab_end; current_ind++)
-      {
-	if (current_ind->modfield == mod)
-	  {
-	    if (current_ind->displacement == IMPLIED_DISP && size == 2)
-	      {
-		continue;
-	      }
-	    else
-	      {
-		size_t i, len;
-		int bufcnt;
-
-		len = strlen (current_ind->syntax);
-		for (i = 0, bufcnt = 0; i < len; i++, bufcnt++)
-		  {
-		    buffer[bufcnt] = current_ind->syntax[i];
-		    if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r')
-		      buffer[++bufcnt] = arnum + '0';
-		    if (buffer[bufcnt] == '('
-			&& current_ind->displacement == DISP_REQUIRED)
-		      {
-			sprintf (&buffer[bufcnt + 1], "%u", disp);
-			bufcnt += strlen (&buffer[bufcnt + 1]);
-		      }
-		  }
-		buffer[bufcnt + 1] = '\0';
-		break;
-	      }
-	  }
-      }
-  }
-  return 1;
-}
-
-int
-get_register_operand (fragment, buffer)
-     unsigned char fragment;
-     char *buffer;
-{
-  const reg *current_reg = tic30_regtab;
-
-  if (buffer == NULL)
-    return 0;
-  for (; current_reg < tic30_regtab_end; current_reg++)
-    {
-      if ((fragment & 0x1F) == current_reg->opcode)
-	{
-	  strcpy (buffer, current_reg->name);
-	  return 1;
-	}
-    }
-  return 0;
-}
-
-int
-cnvt_tmsfloat_ieee (tmsfloat, size, ieeefloat)
-     unsigned long tmsfloat;
-     int size;
-     float *ieeefloat;
-{
-  unsigned long exp, sign, mant;
-  union {
-    unsigned long l;
-    float f;
-  } val;
-
-  if (size == 2)
-    {
-      if ((tmsfloat & 0x0000F000) == 0x00008000)
-	tmsfloat = 0x80000000;
-      else
-	{
-	  tmsfloat <<= 16;
-	  tmsfloat = (long) tmsfloat >> 4;
-	}
-    }
-  exp = tmsfloat & 0xFF000000;
-  if (exp == 0x80000000)
-    {
-      *ieeefloat = 0.0;
-      return 1;
-    }
-  exp += 0x7F000000;
-  sign = (tmsfloat & 0x00800000) << 8;
-  mant = tmsfloat & 0x007FFFFF;
-  if (exp == 0xFF000000)
-    {
-      if (mant == 0)
-	*ieeefloat = ERANGE;
-      if (sign == 0)
-	*ieeefloat = 1.0 / 0.0;
-      else
-	*ieeefloat = -1.0 / 0.0;
-      return 1;
-    }
-  exp >>= 1;
-  if (sign)
-    {
-      mant = (~mant) & 0x007FFFFF;
-      mant += 1;
-      exp += mant & 0x00800000;
-      exp &= 0x7F800000;
-      mant &= 0x007FFFFF;
     }
-  if (tmsfloat == 0x80000000)
-    sign = mant = exp = 0;
-  tmsfloat = sign | exp | mant;
-  val.l = tmsfloat;
-  *ieeefloat = val.f;
-  return 1;
+  return 4;
 }
diff --git a/opcodes/tic4x-dis.c b/opcodes/tic4x-dis.c
index 55d12d5..c0f6152 100644
--- a/opcodes/tic4x-dis.c
+++ b/opcodes/tic4x-dis.c
@@ -1,9 +1,9 @@
 /* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils.
 
-   Copyright 2002, 2003 Free Software Foundation, Inc.
+   Copyright 2002, 2003, 2005 Free Software Foundation, Inc.
 
    Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
-   
+
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
@@ -16,7 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <math.h>
 #include "libiberty.h"
@@ -26,67 +27,32 @@
 #define TIC4X_DEBUG 0
 
 #define TIC4X_HASH_SIZE   11   /* 11 (bits) and above should give unique entries.  */
-#define TIC4X_SPESOP_SIZE 8    /* Max 8. ops for special instructions */
+#define TIC4X_SPESOP_SIZE 8    /* Max 8. ops for special instructions.  */
 
 typedef enum
-  {
-    IMMED_SINT,
-    IMMED_SUINT,
-    IMMED_SFLOAT,
-    IMMED_INT,
-    IMMED_UINT,
-    IMMED_FLOAT
-  }
+{
+  IMMED_SINT,
+  IMMED_SUINT,
+  IMMED_SFLOAT,
+  IMMED_INT,
+  IMMED_UINT,
+  IMMED_FLOAT
+}
 immed_t;
 
 typedef enum
-  {
-    INDIRECT_SHORT,
-    INDIRECT_LONG,
-    INDIRECT_TIC4X
-  }
+{
+  INDIRECT_SHORT,
+  INDIRECT_LONG,
+  INDIRECT_TIC4X
+}
 indirect_t;
 
 static int tic4x_version = 0;
 static int tic4x_dp = 0;
 
-static int tic4x_pc_offset
-  PARAMS ((unsigned int));
-static int tic4x_print_char
-  PARAMS ((struct disassemble_info *, char));
-static int tic4x_print_str
-  PARAMS ((struct disassemble_info *, char *));
-static int tic4x_print_register
-  PARAMS ((struct disassemble_info *, unsigned long));
-static int tic4x_print_addr
-  PARAMS ((struct disassemble_info *, unsigned long));
-static int tic4x_print_relative
-  PARAMS ((struct disassemble_info *, unsigned long, long, unsigned long));
-void tic4x_print_ftoa
-  PARAMS ((unsigned int, FILE *, fprintf_ftype));
-static int tic4x_print_direct
-  PARAMS ((struct disassemble_info *, unsigned long));
-static int tic4x_print_immed
-  PARAMS ((struct disassemble_info *, immed_t, unsigned long));
-static int tic4x_print_cond
-  PARAMS ((struct disassemble_info *, unsigned int));
-static int tic4x_print_indirect
-  PARAMS ((struct disassemble_info *, indirect_t, unsigned long));
-static int tic4x_print_op
-  PARAMS ((struct disassemble_info *, unsigned long, tic4x_inst_t *, unsigned long));
-static void tic4x_hash_opcode_special
-  PARAMS ((tic4x_inst_t **, const tic4x_inst_t *));
-static void tic4x_hash_opcode
-  PARAMS ((tic4x_inst_t **, tic4x_inst_t **, const tic4x_inst_t *, unsigned long));
-static int tic4x_disassemble
-  PARAMS ((unsigned long, unsigned long, struct disassemble_info *));
-int print_insn_tic4x
-  PARAMS ((bfd_vma, struct disassemble_info *));
-
-
 static int
-tic4x_pc_offset (op)
-     unsigned int op;
+tic4x_pc_offset (unsigned int op)
 {
   /* Determine the PC offset for a C[34]x instruction.
      This could be simplified using some boolean algebra
@@ -107,14 +73,14 @@ tic4x_pc_offset (op)
     default:
       break;
     }
-  
+
   switch ((op & 0xffe00000) >> 20)
     {
     case 0x6a0:	/* bB */
     case 0x720: /* callB */
     case 0x740: /* trapB */
       return 1;
-      
+
     case 0x6a2: /* bBd */
     case 0x6a6: /* bBat */
     case 0x6aa: /* bBaf */
@@ -122,30 +88,28 @@ tic4x_pc_offset (op)
     case 0x748: /* latB */
     case 0x798: /* rptbd */
       return 3;
-      
+
     default:
       break;
     }
-  
+
   switch ((op & 0xfe200000) >> 20)
     {
     case 0x6e0:	/* dbB */
       return 1;
-      
+
     case 0x6e2:	/* dbBd */
       return 3;
-      
+
     default:
       break;
     }
-  
+
   return 0;
 }
 
 static int
-tic4x_print_char (info, ch)
-     struct disassemble_info * info;
-     char ch;
+tic4x_print_char (struct disassemble_info * info, char ch)
 {
   if (info != NULL)
     (*info->fprintf_func) (info->stream, "%c", ch);
@@ -153,9 +117,7 @@ tic4x_print_char (info, ch)
 }
 
 static int
-tic4x_print_str (info, str)
-     struct disassemble_info *info;
-     char *str;
+tic4x_print_str (struct disassemble_info *info, char *str)
 {
   if (info != NULL)
     (*info->fprintf_func) (info->stream, "%s", str);
@@ -163,25 +125,23 @@ tic4x_print_str (info, str)
 }
 
 static int
-tic4x_print_register (info, regno)
-     struct disassemble_info *info;
-     unsigned long regno;
+tic4x_print_register (struct disassemble_info *info, unsigned long regno)
 {
-  static tic4x_register_t **registertable = NULL;
+  static tic4x_register_t ** registertable = NULL;
   unsigned int i;
-  
+
   if (registertable == NULL)
     {
-      registertable = (tic4x_register_t **)
-	xmalloc (sizeof (tic4x_register_t *) * REG_TABLE_SIZE);
+      registertable = xmalloc (sizeof (tic4x_register_t *) * REG_TABLE_SIZE);
       for (i = 0; i < tic3x_num_registers; i++)
-	registertable[tic3x_registers[i].regno] = (void *)&tic3x_registers[i];
+	registertable[tic3x_registers[i].regno] = (tic4x_register_t *) (tic3x_registers + i);
       if (IS_CPU_TIC4X (tic4x_version))
 	{
 	  /* Add C4x additional registers, overwriting
 	     any C3x registers if necessary.  */
 	  for (i = 0; i < tic4x_num_registers; i++)
-	    registertable[tic4x_registers[i].regno] = (void *)&tic4x_registers[i];
+	    registertable[tic4x_registers[i].regno] =
+	      (tic4x_register_t *)(tic4x_registers + i);
 	}
     }
   if ((int) regno > (IS_CPU_TIC4X (tic4x_version) ? TIC4X_REG_MAX : TIC3X_REG_MAX))
@@ -192,9 +152,7 @@ tic4x_print_register (info, regno)
 }
 
 static int
-tic4x_print_addr (info, addr)
-     struct disassemble_info *info;
-     unsigned long addr;
+tic4x_print_addr (struct disassemble_info *info, unsigned long addr)
 {
   if (info != NULL)
     (*info->print_address_func)(addr, info);
@@ -202,19 +160,16 @@ tic4x_print_addr (info, addr)
 }
 
 static int
-tic4x_print_relative (info, pc, offset, opcode)
-     struct disassemble_info *info;
-     unsigned long pc;
-     long offset;
-     unsigned long opcode;
+tic4x_print_relative (struct disassemble_info *info,
+		      unsigned long pc,
+		      long offset,
+		      unsigned long opcode)
 {
   return tic4x_print_addr (info, pc + offset + tic4x_pc_offset (opcode));
 }
 
 static int
-tic4x_print_direct (info, arg)
-     struct disassemble_info *info;
-     unsigned long arg;
+tic4x_print_direct (struct disassemble_info *info, unsigned long arg)
 {
   if (info != NULL)
     {
@@ -223,60 +178,58 @@ tic4x_print_direct (info, arg)
     }
   return 1;
 }
-
+#if 0
 /* FIXME: make the floating point stuff not rely on host
    floating point arithmetic.  */
-void
-tic4x_print_ftoa (val, stream, pfunc)
-     unsigned int val;
-     FILE *stream;
-     fprintf_ftype pfunc;
+
+static void
+tic4x_print_ftoa (unsigned int val, FILE *stream, fprintf_ftype pfunc)
 {
   int e;
   int s;
   int f;
   double num = 0.0;
-  
-  e = EXTRS (val, 31, 24);	/* exponent */
+
+  e = EXTRS (val, 31, 24);	/* Exponent.  */
   if (e != -128)
     {
-      s = EXTRU (val, 23, 23);	/* sign bit */
-      f = EXTRU (val, 22, 0);	/* mantissa */
+      s = EXTRU (val, 23, 23);	/* Sign bit.  */
+      f = EXTRU (val, 22, 0);	/* Mantissa.  */
       if (s)
 	f += -2 * (1 << 23);
       else
 	f += (1 << 23);
       num = f / (double)(1 << 23);
       num = ldexp (num, e);
-    }    
+    }
   (*pfunc)(stream, "%.9g", num);
 }
+#endif
 
 static int
-tic4x_print_immed (info, type, arg)
-     struct disassemble_info *info;
-     immed_t type;
-     unsigned long arg;
+tic4x_print_immed (struct disassemble_info *info,
+		   immed_t type,
+		   unsigned long arg)
 {
   int s;
   int f;
   int e;
   double num = 0.0;
-  
+
   if (info == NULL)
     return 1;
   switch (type)
     {
     case IMMED_SINT:
     case IMMED_INT:
-      (*info->fprintf_func) (info->stream, "%d", (long)arg);
+      (*info->fprintf_func) (info->stream, "%d", (long) arg);
       break;
-      
+
     case IMMED_SUINT:
     case IMMED_UINT:
       (*info->fprintf_func) (info->stream, "%u", arg);
       break;
-      
+
     case IMMED_SFLOAT:
       e = EXTRS (arg, 15, 12);
       if (e != -8)
@@ -312,18 +265,16 @@ tic4x_print_immed (info, type, arg)
 }
 
 static int
-tic4x_print_cond (info, cond)
-     struct disassemble_info *info;
-     unsigned int cond;
+tic4x_print_cond (struct disassemble_info *info, unsigned int cond)
 {
   static tic4x_cond_t **condtable = NULL;
   unsigned int i;
-  
+
   if (condtable == NULL)
     {
-      condtable = (tic4x_cond_t **)xmalloc (sizeof (tic4x_cond_t *) * 32);
+      condtable = xmalloc (sizeof (tic4x_cond_t *) * 32);
       for (i = 0; i < tic4x_num_conds; i++)
-	condtable[tic4x_conds[i].cond] = (void *)&tic4x_conds[i];
+	condtable[tic4x_conds[i].cond] = (tic4x_cond_t *)(tic4x_conds + i);
     }
   if (cond > 31 || condtable[cond] == NULL)
     return 0;
@@ -333,10 +284,9 @@ tic4x_print_cond (info, cond)
 }
 
 static int
-tic4x_print_indirect (info, type, arg)
-     struct disassemble_info *info;
-     indirect_t type;
-     unsigned long arg;
+tic4x_print_indirect (struct disassemble_info *info,
+		      indirect_t type,
+		      unsigned long arg)
 {
   unsigned int aregno;
   unsigned int modn;
@@ -398,11 +348,10 @@ tic4x_print_indirect (info, type, arg)
 }
 
 static int
-tic4x_print_op (info, instruction, p, pc)
-     struct disassemble_info *info;
-     unsigned long instruction;
-     tic4x_inst_t *p;
-     unsigned long pc;
+tic4x_print_op (struct disassemble_info *info,
+		unsigned long instruction,
+		tic4x_inst_t *p,
+		unsigned long pc)
 {
   int val;
   char *s;
@@ -423,7 +372,7 @@ tic4x_print_op (info, instruction, p, pc)
 	    return 0;
 	  break;
 	case '_':
-	  parallel = s + 1;	/* Skip past `_' in name */
+	  parallel = s + 1;	/* Skip past `_' in name.  */
 	  break;
 	default:
 	  tic4x_print_char (info, *s);
@@ -431,7 +380,7 @@ tic4x_print_op (info, instruction, p, pc)
 	}
       s++;
     }
-  
+
   /* Print arguments.  */
   s = p->args;
   if (*s)
@@ -441,23 +390,23 @@ tic4x_print_op (info, instruction, p, pc)
     {
       switch (*s)
 	{
-	case '*': /* indirect 0--15 */
+	case '*': /* Indirect 0--15.  */
 	  if (! tic4x_print_indirect (info, INDIRECT_LONG,
-				    EXTRU (instruction, 15, 0)))
+				      EXTRU (instruction, 15, 0)))
 	    return 0;
 	  break;
 
-	case '#': /* only used for ldp, ldpk */
+	case '#': /* Only used for ldp, ldpk.  */
 	  tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
 	  break;
 
-	case '@': /* direct 0--15 */
+	case '@': /* Direct 0--15.  */
 	  tic4x_print_direct (info, EXTRU (instruction, 15, 0));
 	  break;
 
-	case 'A': /* address register 24--22 */
+	case 'A': /* Address register 24--22.  */
 	  if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) +
-				    REG_AR0))
+				      REG_AR0))
 	    return 0;
 	  break;
 
@@ -465,16 +414,16 @@ tic4x_print_op (info, instruction, p, pc)
 		     address 0--23.  */
 	  if (IS_CPU_TIC4X (tic4x_version))
 	    tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0),
-				p->opcode);
+				  p->opcode);
 	  else
 	    tic4x_print_addr (info, EXTRU (instruction, 23, 0));
 	  break;
 
-	case 'C': /* indirect (short C4x) 0--7 */
+	case 'C': /* Indirect (short C4x) 0--7.  */
 	  if (! IS_CPU_TIC4X (tic4x_version))
 	    return 0;
 	  if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
-				    EXTRU (instruction, 7, 0)))
+				      EXTRU (instruction, 7, 0)))
 	    return 0;
 	  break;
 
@@ -482,131 +431,131 @@ tic4x_print_op (info, instruction, p, pc)
 	  /* Cockup if get here...  */
 	  break;
 
-	case 'E': /* register 0--7 */
+	case 'E': /* Register 0--7.  */
         case 'e':
 	  if (! tic4x_print_register (info, EXTRU (instruction, 7, 0)))
 	    return 0;
 	  break;
 
-	case 'F': /* 16-bit float immediate 0--15 */
+	case 'F': /* 16-bit float immediate 0--15.  */
 	  tic4x_print_immed (info, IMMED_SFLOAT,
-			   EXTRU (instruction, 15, 0));
+			     EXTRU (instruction, 15, 0));
 	  break;
 
-        case 'i': /* Extended indirect 0--7 */
-          if ( EXTRU (instruction, 7, 5) == 7 )
+        case 'i': /* Extended indirect 0--7.  */
+          if (EXTRU (instruction, 7, 5) == 7)
             {
-              if( !tic4x_print_register (info, EXTRU (instruction, 4, 0)) )
+              if (!tic4x_print_register (info, EXTRU (instruction, 4, 0)))
                 return 0;
               break;
             }
           /* Fallthrough */
 
-	case 'I': /* indirect (short) 0--7 */
+	case 'I': /* Indirect (short) 0--7.  */
 	  if (! tic4x_print_indirect (info, INDIRECT_SHORT,
-				    EXTRU (instruction, 7, 0)))
+				      EXTRU (instruction, 7, 0)))
 	    return 0;
 	  break;
 
         case 'j': /* Extended indirect 8--15 */
-          if ( EXTRU (instruction, 15, 13) == 7 )
+          if (EXTRU (instruction, 15, 13) == 7)
             {
-              if( !tic4x_print_register (info, EXTRU (instruction, 12, 8)) )
+              if (! tic4x_print_register (info, EXTRU (instruction, 12, 8)))
                 return 0;
               break;
             }
 
-	case 'J': /* indirect (short) 8--15 */
+	case 'J': /* Indirect (short) 8--15.  */
 	  if (! tic4x_print_indirect (info, INDIRECT_SHORT,
-				    EXTRU (instruction, 15, 8)))
+				      EXTRU (instruction, 15, 8)))
 	    return 0;
 	  break;
 
-	case 'G': /* register 8--15 */
+	case 'G': /* Register 8--15.  */
         case 'g':
 	  if (! tic4x_print_register (info, EXTRU (instruction, 15, 8)))
 	    return 0;
 	  break;
 
-	case 'H': /* register 16--18 */
+	case 'H': /* Register 16--18.  */
 	  if (! tic4x_print_register (info, EXTRU (instruction, 18, 16)))
 	    return 0;
 	  break;
 
-	case 'K': /* register 19--21 */
+	case 'K': /* Register 19--21.  */
 	  if (! tic4x_print_register (info, EXTRU (instruction, 21, 19)))
 	    return 0;
 	  break;
 
-	case 'L': /* register 22--24 */
+	case 'L': /* Register 22--24.  */
 	  if (! tic4x_print_register (info, EXTRU (instruction, 24, 22)))
 	    return 0;
 	  break;
 
-	case 'M': /* register 22--22 */
+	case 'M': /* Register 22--22.  */
 	  tic4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2);
 	  break;
 
-	case 'N': /* register 23--23 */
+	case 'N': /* Register 23--23.  */
 	  tic4x_print_register (info, EXTRU (instruction, 23, 23) + REG_R0);
 	  break;
 
-	case 'O': /* indirect (short C4x) 8--15 */
+	case 'O': /* Indirect (short C4x) 8--15.  */
 	  if (! IS_CPU_TIC4X (tic4x_version))
 	    return 0;
 	  if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
-				    EXTRU (instruction, 15, 8)))
+				      EXTRU (instruction, 15, 8)))
 	    return 0;
 	  break;
 
-	case 'P': /* displacement 0--15 (used by Bcond and BcondD) */
+	case 'P': /* Displacement 0--15 (used by Bcond and BcondD).  */
 	  tic4x_print_relative (info, pc, EXTRS (instruction, 15, 0),
-			      p->opcode);
+				p->opcode);
 	  break;
 
-	case 'Q': /* register 0--15 */
+	case 'Q': /* Register 0--15.  */
         case 'q':
 	  if (! tic4x_print_register (info, EXTRU (instruction, 15, 0)))
 	    return 0;
 	  break;
 
-	case 'R': /* register 16--20 */
+	case 'R': /* Register 16--20.  */
         case 'r':
 	  if (! tic4x_print_register (info, EXTRU (instruction, 20, 16)))
 	    return 0;
 	  break;
 
-	case 'S': /* 16-bit signed immediate 0--15 */
+	case 'S': /* 16-bit signed immediate 0--15.  */
 	  tic4x_print_immed (info, IMMED_SINT,
-			   EXTRS (instruction, 15, 0));
+			     EXTRS (instruction, 15, 0));
 	  break;
 
-	case 'T': /* 5-bit signed immediate 16--20  (C4x stik) */
+	case 'T': /* 5-bit signed immediate 16--20  (C4x stik).  */
 	  if (! IS_CPU_TIC4X (tic4x_version))
 	    return 0;
 	  if (! tic4x_print_immed (info, IMMED_SUINT,
-				 EXTRU (instruction, 20, 16)))
+				   EXTRU (instruction, 20, 16)))
 	    return 0;
 	  break;
 
-	case 'U': /* 16-bit unsigned int immediate 0--15 */
+	case 'U': /* 16-bit unsigned int immediate 0--15.  */
 	  tic4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0));
 	  break;
 
-	case 'V': /* 5/9-bit unsigned vector 0--4/8 */
+	case 'V': /* 5/9-bit unsigned vector 0--4/8.  */
 	  tic4x_print_immed (info, IMMED_SUINT,
-			   IS_CPU_TIC4X (tic4x_version) ? 
-			   EXTRU (instruction, 8, 0) :
-			   EXTRU (instruction, 4, 0) & ~0x20);
+			     IS_CPU_TIC4X (tic4x_version) ?
+			     EXTRU (instruction, 8, 0) :
+			     EXTRU (instruction, 4, 0) & ~0x20);
 	  break;
 
-	case 'W': /* 8-bit signed immediate 0--7 */
+	case 'W': /* 8-bit signed immediate 0--7.  */
 	  if (! IS_CPU_TIC4X (tic4x_version))
 	    return 0;
 	  tic4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0));
 	  break;
 
-	case 'X': /* expansion register 4--0 */
+	case 'X': /* Expansion register 4--0.  */
 	  val = EXTRU (instruction, 4, 0) + REG_IVTP;
 	  if (val < REG_IVTP || val > REG_TVTP)
 	    return 0;
@@ -614,7 +563,7 @@ tic4x_print_op (info, instruction, p, pc)
 	    return 0;
 	  break;
 
-	case 'Y': /* address register 16--20 */
+	case 'Y': /* Address register 16--20.  */
 	  val = EXTRU (instruction, 20, 16);
 	  if (val < REG_AR0 || val > REG_SP)
 	    return 0;
@@ -622,7 +571,7 @@ tic4x_print_op (info, instruction, p, pc)
 	    return 0;
 	  break;
 
-	case 'Z': /* expansion register 16--20 */
+	case 'Z': /* Expansion register 16--20.  */
 	  val = EXTRU (instruction, 20, 16) + REG_IVTP;
 	  if (val < REG_IVTP || val > REG_TVTP)
 	    return 0;
@@ -630,7 +579,7 @@ tic4x_print_op (info, instruction, p, pc)
 	    return 0;
 	  break;
 
-	case '|':		/* Parallel instruction */
+	case '|':	/* Parallel instruction.  */
 	  tic4x_print_str (info, " || ");
 	  tic4x_print_str (info, parallel);
 	  tic4x_print_char (info, ' ');
@@ -650,26 +599,25 @@ tic4x_print_op (info, instruction, p, pc)
 }
 
 static void
-tic4x_hash_opcode_special (optable_special, inst)
-     tic4x_inst_t **optable_special;
-     const tic4x_inst_t *inst;
+tic4x_hash_opcode_special (tic4x_inst_t **optable_special,
+			   const tic4x_inst_t *inst)
 {
   int i;
 
-  for( i=0; i<TIC4X_SPESOP_SIZE; i++ )
-    if( optable_special[i] != NULL
-        && optable_special[i]->opcode == inst->opcode )
+  for (i = 0;i < TIC4X_SPESOP_SIZE; i++)
+    if (optable_special[i] != NULL
+        && optable_special[i]->opcode == inst->opcode)
       {
-        /* Collision (we have it already) - overwrite */
-        optable_special[i] = (void *)inst;
+        /* Collision (we have it already) - overwrite.  */
+        optable_special[i] = (tic4x_inst_t *) inst;
         return;
       }
 
-  for( i=0; i<TIC4X_SPESOP_SIZE; i++ )
-    if( optable_special[i] == NULL )
+  for (i = 0; i < TIC4X_SPESOP_SIZE; i++)
+    if (optable_special[i] == NULL)
       {
-        /* Add the new opcode */
-        optable_special[i] = (void *)inst;
+        /* Add the new opcode.  */
+        optable_special[i] = (tic4x_inst_t *) inst;
         return;
       }
 
@@ -677,50 +625,49 @@ tic4x_hash_opcode_special (optable_special, inst)
      instructions exceeds TIC4X_SPESOP_SIZE. Please increase the variable
      of this variable */
 #if TIC4X_DEBUG
-  printf("optable_special[] is full, please increase TIC4X_SPESOP_SIZE!\n");
+  printf ("optable_special[] is full, please increase TIC4X_SPESOP_SIZE!\n");
 #endif
 }
 
 static void
-tic4x_hash_opcode (optable, optable_special, inst, tic4x_oplevel)
-     tic4x_inst_t **optable;
-     tic4x_inst_t **optable_special;
-     const tic4x_inst_t *inst;
-     const unsigned long tic4x_oplevel;
+tic4x_hash_opcode (tic4x_inst_t **optable,
+		   tic4x_inst_t **optable_special,
+		   const tic4x_inst_t *inst,
+		   const unsigned long tic4x_oplevel)
 {
   int j;
   int opcode = inst->opcode >> (32 - TIC4X_HASH_SIZE);
   int opmask = inst->opmask >> (32 - TIC4X_HASH_SIZE);
-  
+
   /* Use a TIC4X_HASH_SIZE bit index as a hash index.  We should
      have unique entries so there's no point having a linked list
-     for each entry? */
+     for each entry?  */
   for (j = opcode; j < opmask; j++)
-    if ( (j & opmask) == opcode
-         && inst->oplevel & tic4x_oplevel )
+    if ((j & opmask) == opcode
+         && inst->oplevel & tic4x_oplevel)
       {
 #if TIC4X_DEBUG
 	/* We should only have collisions for synonyms like
 	   ldp for ldi.  */
 	if (optable[j] != NULL)
-	  printf("Collision at index %d, %s and %s\n",
-		 j, optable[j]->name, inst->name);
+	  printf ("Collision at index %d, %s and %s\n",
+		  j, optable[j]->name, inst->name);
 #endif
         /* Catch those ops that collide with others already inside the
            hash, and have a opmask greater than the one we use in the
            hash. Store them in a special-list, that will handle full
            32-bit INSN, not only the first 11-bit (or so). */
-        if ( optable[j] != NULL
-             && inst->opmask & ~(opmask << (32 - TIC4X_HASH_SIZE)) )
+        if (optable[j] != NULL
+	    && inst->opmask & ~(opmask << (32 - TIC4X_HASH_SIZE)))
           {
-            /* Add the instruction already on the list */
-            tic4x_hash_opcode_special(optable_special, optable[j]);
+            /* Add the instruction already on the list.  */
+            tic4x_hash_opcode_special (optable_special, optable[j]);
 
-            /* Add the new instruction */
-            tic4x_hash_opcode_special(optable_special, inst);
+            /* Add the new instruction.  */
+            tic4x_hash_opcode_special (optable_special, inst);
           }
 
-        optable[j] = (void *)inst;
+        optable[j] = (tic4x_inst_t *) inst;
       }
 }
 
@@ -731,53 +678,50 @@ tic4x_hash_opcode (optable, optable_special, inst, tic4x_oplevel)
    The function returns the length of this instruction in words.  */
 
 static int
-tic4x_disassemble (pc, instruction, info)
-     unsigned long pc;
-     unsigned long instruction;
-     struct disassemble_info *info;
+tic4x_disassemble (unsigned long pc,
+		   unsigned long instruction,
+		   struct disassemble_info *info)
 {
   static tic4x_inst_t **optable = NULL;
   static tic4x_inst_t **optable_special = NULL;
   tic4x_inst_t *p;
   int i;
   unsigned long tic4x_oplevel;
-  
+
   tic4x_version = info->mach;
 
   tic4x_oplevel  = (IS_CPU_TIC4X (tic4x_version)) ? OP_C4X : 0;
-  tic4x_oplevel |= OP_C3X|OP_LPWR|OP_IDLE2|OP_ENH;
-  
+  tic4x_oplevel |= OP_C3X | OP_LPWR | OP_IDLE2 | OP_ENH;
+
   if (optable == NULL)
     {
-      optable = (tic4x_inst_t **)
-	xcalloc (sizeof (tic4x_inst_t *), (1 << TIC4X_HASH_SIZE));
+      optable = xcalloc (sizeof (tic4x_inst_t *), (1 << TIC4X_HASH_SIZE));
 
-      optable_special = (tic4x_inst_t **)
-        xcalloc (sizeof (tic4x_inst_t *), TIC4X_SPESOP_SIZE );
+      optable_special = xcalloc (sizeof (tic4x_inst_t *), TIC4X_SPESOP_SIZE);
 
       /* Install opcodes in reverse order so that preferred
 	 forms overwrite synonyms.  */
       for (i = tic4x_num_insts - 1; i >= 0; i--)
-        tic4x_hash_opcode (optable, optable_special, &tic4x_insts[i], tic4x_oplevel);
+        tic4x_hash_opcode (optable, optable_special, &tic4x_insts[i],
+			   tic4x_oplevel);
 
       /* We now need to remove the insn that are special from the
          "normal" optable, to make the disasm search this extra list
-         for them.
-      */
-      for (i=0; i<TIC4X_SPESOP_SIZE; i++)
-        if ( optable_special[i] != NULL )
+         for them.  */
+      for (i = 0; i < TIC4X_SPESOP_SIZE; i++)
+        if (optable_special[i] != NULL)
           optable[optable_special[i]->opcode >> (32 - TIC4X_HASH_SIZE)] = NULL;
     }
-  
+
   /* See if we can pick up any loading of the DP register...  */
   if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70)
     tic4x_dp = EXTRU (instruction, 15, 0);
 
   p = optable[instruction >> (32 - TIC4X_HASH_SIZE)];
-  if ( p != NULL )
+  if (p != NULL)
     {
-      if ( ((instruction & p->opmask) == p->opcode)
-           && tic4x_print_op (NULL, instruction, p, pc) )
+      if (((instruction & p->opmask) == p->opcode)
+           && tic4x_print_op (NULL, instruction, p, pc))
         tic4x_print_op (info, instruction, p, pc);
       else
         (*info->fprintf_func) (info->stream, "%08x", instruction);
@@ -786,37 +730,35 @@ tic4x_disassemble (pc, instruction, info)
     {
       for (i = 0; i<TIC4X_SPESOP_SIZE; i++)
         if (optable_special[i] != NULL
-            && optable_special[i]->opcode == instruction )
+            && optable_special[i]->opcode == instruction)
           {
             (*info->fprintf_func)(info->stream, "%s", optable_special[i]->name);
             break;
           }
-      if (i==TIC4X_SPESOP_SIZE)
+      if (i == TIC4X_SPESOP_SIZE)
         (*info->fprintf_func) (info->stream, "%08x", instruction);
     }
 
   /* Return size of insn in words.  */
-  return 1;	
+  return 1;
 }
 
 /* The entry point from objdump and gdb.  */
 int
-print_insn_tic4x (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_tic4x (bfd_vma memaddr, struct disassemble_info *info)
 {
   int status;
   unsigned long pc;
   unsigned long op;
   bfd_byte buffer[4];
-  
+
   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
   if (status != 0)
     {
       (*info->memory_error_func) (status, memaddr, info);
       return -1;
     }
-  
+
   pc = memaddr;
   op = bfd_getl32 (buffer);
   info->bytes_per_line = 4;
diff --git a/opcodes/tic80-dis.c b/opcodes/tic80-dis.c
index a4793b4..09df146 100644
--- a/opcodes/tic80-dis.c
+++ b/opcodes/tic80-dis.c
@@ -1,19 +1,20 @@
 /* Print TI TMS320C80 (MVP) instructions
-   Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 2000, 2005 Free Software Foundation, Inc.
 
-This file is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <stdio.h>
 
@@ -22,20 +23,6 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 #include "dis-asm.h"
 
 static int length;
-
-static void print_operand_bitnum PARAMS ((struct disassemble_info *, long));
-static void print_operand_condition_code PARAMS ((struct disassemble_info *, long));
-static void print_operand_control_register PARAMS ((struct disassemble_info *, long));
-static void print_operand_float PARAMS ((struct disassemble_info *, long));
-static void print_operand_integer PARAMS ((struct disassemble_info *, long));
-static void print_operand PARAMS ((struct disassemble_info *, long, unsigned long,
-				   const struct tic80_operand *, bfd_vma));
-static int print_one_instruction PARAMS ((struct disassemble_info *, bfd_vma,
-				      unsigned long, const struct tic80_opcode *));
-static int print_instruction PARAMS ((struct disassemble_info *, bfd_vma, unsigned long,
-				      const struct tic80_opcode *));
-static int fill_instruction PARAMS ((struct disassemble_info *, bfd_vma,
-				     unsigned long *));
 
 /* Print an integer operand.  Try to be somewhat smart about the
    format by assuming that small positive or negative integers are
@@ -44,18 +31,12 @@ static int fill_instruction PARAMS ((struct disassemble_info *, bfd_vma,
    Larger numbers are probably better printed as hex values.  */
 
 static void
-print_operand_integer (info, value)
-     struct disassemble_info *info;
-     long value;
+print_operand_integer (struct disassemble_info *info, long value)
 {
   if ((value > 9999 || value < -9999))
-    {
-      (*info->fprintf_func) (info->stream, "%#lx", value);
-    }
+    (*info->fprintf_func) (info->stream, "%#lx", value);
   else
-    {
-      (*info->fprintf_func) (info->stream, "%ld", value);
-    }
+    (*info->fprintf_func) (info->stream, "%ld", value);
 }
 
 /* FIXME: depends upon sizeof (long) == sizeof (float) and
@@ -63,56 +44,40 @@ print_operand_integer (info, value)
    floating point format.  */
 
 static void
-print_operand_float (info, value)
-     struct disassemble_info *info;
-     long value;
+print_operand_float (struct disassemble_info *info, long value)
 {
   union { float f; long l; } fval;
 
   fval.l = value;
   (*info->fprintf_func) (info->stream, "%g", fval.f);
 }
-
+
 static void
-print_operand_control_register (info, value)
-     struct disassemble_info *info;
-     long value;
+print_operand_control_register (struct disassemble_info *info, long value)
 {
   const char *tmp;
 
   tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CR);
   if (tmp != NULL)
-    {
-      (*info->fprintf_func) (info->stream, "%s", tmp);
-    }
+    (*info->fprintf_func) (info->stream, "%s", tmp);
   else
-    {
-      (*info->fprintf_func) (info->stream, "%#lx", value);
-    }
+    (*info->fprintf_func) (info->stream, "%#lx", value);
 }
-
+
 static void
-print_operand_condition_code (info, value)
-     struct disassemble_info *info;
-     long value;
+print_operand_condition_code (struct disassemble_info *info, long value)
 {
   const char *tmp;
 
   tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CC);
   if (tmp != NULL)
-    {
-      (*info->fprintf_func) (info->stream, "%s", tmp);
-    }
+    (*info->fprintf_func) (info->stream, "%s", tmp);
   else
-    {
-      (*info->fprintf_func) (info->stream, "%ld", value);
-    }
+    (*info->fprintf_func) (info->stream, "%ld", value);
 }
-
+
 static void
-print_operand_bitnum (info, value)
-     struct disassemble_info *info;
-     long value;
+print_operand_bitnum (struct disassemble_info *info, long value)
 {
   int bitnum;
   const char *tmp;
@@ -120,13 +85,9 @@ print_operand_bitnum (info, value)
   bitnum = ~value & 0x1F;
   tmp = tic80_value_to_symbol (bitnum, TIC80_OPERAND_BITNUM);
   if (tmp != NULL)
-    {
-      (*info->fprintf_func) (info->stream, "%s", tmp);
-    }
+    (*info->fprintf_func) (info->stream, "%s", tmp);
   else
-    {
-      (*info->fprintf_func) (info->stream, "%ld", bitnum);
-    }
+    (*info->fprintf_func) (info->stream, "%ld", bitnum);
 }
 
 /* Print the operand as directed by the flags.  */
@@ -136,12 +97,11 @@ print_operand_bitnum (info, value)
 #define R_SCALED(insn,op) ((((op)->flags & TIC80_OPERAND_SCALED) != 0) && ((insn) & (1 << 11)))
 
 static void
-print_operand (info, value, insn, operand, memaddr)
-     struct disassemble_info *info;
-     long value;
-     unsigned long insn;
-     const struct tic80_operand *operand;
-     bfd_vma memaddr;
+print_operand (struct disassemble_info *info,
+	       long value,
+	       unsigned long insn,
+	       const struct tic80_operand *operand,
+	       bfd_vma memaddr)
 {
   if ((operand->flags & TIC80_OPERAND_GPR) != 0)
     {
@@ -152,58 +112,81 @@ print_operand (info, value, insn, operand, memaddr)
 	}
     }
   else if ((operand->flags & TIC80_OPERAND_FPA) != 0)
-    {
-      (*info->fprintf_func) (info->stream, "a%ld", value);
-    }
+    (*info->fprintf_func) (info->stream, "a%ld", value);
+
   else if ((operand->flags & TIC80_OPERAND_PCREL) != 0)
-    {
-      (*info->print_address_func) (memaddr + 4 * value, info);
-    }
+    (*info->print_address_func) (memaddr + 4 * value, info);
+
   else if ((operand->flags & TIC80_OPERAND_BASEREL) != 0)
-    {
-      (*info->print_address_func) (value, info);
-    }
+    (*info->print_address_func) (value, info);
+
   else if ((operand->flags & TIC80_OPERAND_BITNUM) != 0)
-    {
-      print_operand_bitnum (info, value);
-    }
+    print_operand_bitnum (info, value);
+
   else if ((operand->flags & TIC80_OPERAND_CC) != 0)
-    {
-      print_operand_condition_code (info, value);
-    }
+    print_operand_condition_code (info, value);
+
   else if ((operand->flags & TIC80_OPERAND_CR) != 0)
-    {
-      print_operand_control_register (info, value);
-    }
+    print_operand_control_register (info, value);
+
   else if ((operand->flags & TIC80_OPERAND_FLOAT) != 0)
-    {
-      print_operand_float (info, value);
-    }
+    print_operand_float (info, value);
+
   else if ((operand->flags & TIC80_OPERAND_BITFIELD))
-    {
-      (*info->fprintf_func) (info->stream, "%#lx", value);
-    }
+    (*info->fprintf_func) (info->stream, "%#lx", value);
+
   else
-    {
-      print_operand_integer (info, value);
-    }
+    print_operand_integer (info, value);
 
   /* If this is a scaled operand, then print the modifier.  */
-
   if (R_SCALED (insn, operand))
+    (*info->fprintf_func) (info->stream, ":s");
+}
+
+/* Get the next 32 bit word from the instruction stream and convert it
+   into internal format in the unsigned long INSN, for which we are
+   passed the address.  Return 0 on success, -1 on error.  */
+
+static int
+fill_instruction (struct disassemble_info *info,
+		  bfd_vma memaddr,
+		  unsigned long *insnp)
+{
+  bfd_byte buffer[4];
+  int status;
+
+  /* Get the bits for the next 32 bit word and put in buffer.  */
+  status = (*info->read_memory_func) (memaddr + length, buffer, 4, info);
+  if (status != 0)
     {
-      (*info->fprintf_func) (info->stream, ":s");
+      (*info->memory_error_func) (status, memaddr, info);
+      return -1;
     }
+
+  /* Read was successful, so increment count of bytes read and convert
+     the bits into internal format.  */
+
+  length += 4;
+  if (info->endian == BFD_ENDIAN_LITTLE)
+    *insnp = bfd_getl32 (buffer);
+
+  else if (info->endian == BFD_ENDIAN_BIG)
+    *insnp = bfd_getb32 (buffer);
+
+  else
+    /* FIXME: Should probably just default to one or the other.  */
+    abort ();
+
+  return 0;
 }
-
+
 /* We have chosen an opcode table entry.  */
 
 static int
-print_one_instruction (info, memaddr, insn, opcode)
-     struct disassemble_info *info;
-     bfd_vma memaddr;
-     unsigned long insn;
-     const struct tic80_opcode *opcode;
+print_one_instruction (struct disassemble_info *info,
+		       bfd_vma memaddr,
+		       unsigned long insn,
+		       const struct tic80_opcode *opcode)
 {
   const struct tic80_operand *operand;
   long value;
@@ -219,38 +202,31 @@ print_one_instruction (info, memaddr, insn, opcode)
 
       /* Extract the value from the instruction.  */
       if (operand->extract)
-	{
-	  value = (*operand->extract) (insn, (int *) NULL);
-	}
+	value = (*operand->extract) (insn, NULL);
+
       else if (operand->bits == 32)
 	{
 	  status = fill_instruction (info, memaddr, (unsigned long *) &value);
 	  if (status == -1)
-	    {
-	      return (status);
-	    }
+	    return status;
 	}
       else
 	{
 	  value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
+
 	  if ((operand->flags & TIC80_OPERAND_SIGNED) != 0
 	      && (value & (1 << (operand->bits - 1))) != 0)
-	    {
-	      value -= 1 << operand->bits;
-	    }
+	    value -= 1 << operand->bits;
 	}
 
       /* If this operand is enclosed in parenthesis, then print
 	 the open paren, otherwise just print the regular comma
 	 separator, except for the first operand.  */
-
       if ((operand->flags & TIC80_OPERAND_PARENS) == 0)
 	{
 	  close_paren = 0;
 	  if (opindex != opcode->operands)
-	    {
-	      (*info->fprintf_func) (info->stream, ",");
-	    }
+	    (*info->fprintf_func) (info->stream, ",");
 	}
       else
 	{
@@ -262,13 +238,11 @@ print_one_instruction (info, memaddr, insn, opcode)
 
       /* If we printed an open paren before printing this operand, close
 	 it now. The flag gets reset on each loop.  */
-
       if (close_paren)
-	{
-	  (*info->fprintf_func) (info->stream, ")");
-	}
+	(*info->fprintf_func) (info->stream, ")");
     }
-  return (length);
+
+  return length;
 }
 
 /* There are no specific bits that tell us for certain whether a vector
@@ -280,11 +254,10 @@ print_one_instruction (info, memaddr, insn, opcode)
 #define TWO_INSN(insn) ((((insn) & (0x1F << 27)) != 0) && (((insn) & (0x1F << 22)) != 0))
 
 static int
-print_instruction (info, memaddr, insn, vec_opcode)
-     struct disassemble_info *info;
-     bfd_vma memaddr;
-     unsigned long insn;
-     const struct tic80_opcode *vec_opcode;
+print_instruction (struct disassemble_info *info,
+		   bfd_vma memaddr,
+		   unsigned long insn,
+		   const struct tic80_opcode *vec_opcode)
 {
   const struct tic80_opcode *opcode;
   const struct tic80_opcode *opcode_end;
@@ -300,9 +273,7 @@ print_instruction (info, memaddr, insn, vec_opcode)
     {
       if ((insn & opcode->mask) == opcode->opcode &&
 	  opcode != vec_opcode)
-	{
-	  break;
-	}
+	break;
     }
 
   if (opcode == opcode_end)
@@ -323,55 +294,12 @@ print_instruction (info, memaddr, insn, vec_opcode)
 	  length = print_instruction (info, memaddr, insn, opcode);
 	}
     }
-  return (length);
-}
 
-/* Get the next 32 bit word from the instruction stream and convert it
-   into internal format in the unsigned long INSN, for which we are
-   passed the address.  Return 0 on success, -1 on error.  */
-
-static int
-fill_instruction (info, memaddr, insnp)
-     struct disassemble_info *info;
-     bfd_vma memaddr;
-     unsigned long *insnp;
-{
-  bfd_byte buffer[4];
-  int status;
-
-  /* Get the bits for the next 32 bit word and put in buffer.  */
-
-  status = (*info->read_memory_func) (memaddr + length, buffer, 4, info);
-  if (status != 0)
-    {
-      (*info->memory_error_func) (status, memaddr, info);
-      return (-1);
-    }
-
-  /* Read was successful, so increment count of bytes read and convert
-     the bits into internal format.  */
-
-  length += 4;
-  if (info->endian == BFD_ENDIAN_LITTLE)
-    {
-      *insnp = bfd_getl32 (buffer);
-    }
-  else if (info->endian == BFD_ENDIAN_BIG)
-    {
-      *insnp = bfd_getb32 (buffer);
-    }
-  else
-    {
-      /* FIXME: Should probably just default to one or the other.  */
-      abort ();
-    }
-  return (0);
+  return length;
 }
 
 int
-print_insn_tic80 (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_tic80 (bfd_vma memaddr, struct disassemble_info *info)
 {
   unsigned long insn;
   int status;
@@ -380,8 +308,7 @@ print_insn_tic80 (memaddr, info)
   info->bytes_per_line = 8;
   status = fill_instruction (info, memaddr, &insn);
   if (status != -1)
-    {
-      status = print_instruction (info, memaddr, insn, NULL);
-    }
-  return (status);
+    status = print_instruction (info, memaddr, insn, NULL);
+
+  return status;
 }
diff --git a/opcodes/v850-dis.c b/opcodes/v850-dis.c
index 6a0f45e..1bfc7b4 100644
--- a/opcodes/v850-dis.c
+++ b/opcodes/v850-dis.c
@@ -1,5 +1,5 @@
 /* Disassemble V850 instructions.
-   Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003
+   Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
@@ -14,57 +14,54 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 
 #include <stdio.h>
 
 #include "sysdep.h"
-#include "opcode/v850.h" 
+#include "opcode/v850.h"
 #include "dis-asm.h"
 #include "opintl.h"
 
 static const char *const v850_reg_names[] =
-{ "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7", 
-  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 
-  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 
+{ "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7",
+  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
   "r24", "r25", "r26", "r27", "r28", "r29", "ep", "lp" };
 
 static const char *const v850_sreg_names[] =
-{ "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7", 
+{ "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
   "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
-  "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23", 
+  "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23",
   "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
-  "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23", 
+  "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23",
   "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31" };
 
 static const char *const v850_cc_names[] =
-{ "v", "c/l", "z", "nh", "s/n", "t", "lt", "le", 
+{ "v", "c/l", "z", "nh", "s/n", "t", "lt", "le",
   "nv", "nc/nl", "nz", "h", "ns/p", "sa", "ge", "gt" };
 
-static int disassemble
-  PARAMS ((bfd_vma, struct disassemble_info *, unsigned long));
-
 static int
-disassemble (memaddr, info, insn)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
-     unsigned long insn;
+disassemble (bfd_vma memaddr,
+	     struct disassemble_info * info,
+	     unsigned long insn)
 {
-  struct v850_opcode *op = (struct v850_opcode *)v850_opcodes;
-  const struct v850_operand *operand;
+  struct v850_opcode * op = (struct v850_opcode *) v850_opcodes;
+  const struct v850_operand * operand;
   int match = 0;
   int short_op = ((insn & 0x0600) != 0x0600);
   int bytes_read;
   int target_processor;
-  
-  /* Special case: 32 bit MOV */
+
+  /* Special case: 32 bit MOV.  */
   if ((insn & 0xffe0) == 0x0620)
     short_op = 1;
-  
+
   bytes_read = short_op ? 2 : 4;
-  
-  /* If this is a two byte insn, then mask off the high bits. */
+
+  /* If this is a two byte insn, then mask off the high bits.  */
   if (short_op)
     insn &= 0xffff;
 
@@ -83,7 +80,7 @@ disassemble (memaddr, info, insn)
       target_processor = PROCESSOR_V850E1;
       break;
     }
-  
+
   /* Find the opcode.  */
   while (op->name)
     {
@@ -96,7 +93,6 @@ disassemble (memaddr, info, insn)
 
 	  match = 1;
 	  (*info->fprintf_func) (info->stream, "%s\t", op->name);
-/*fprintf (stderr, "match: mask: %x insn: %x, opcode: %x, name: %s\n", op->mask, insn, op->opcode, op->name );*/
 
 	  memop = op->memop;
 	  /* Now print the operands.
@@ -111,7 +107,7 @@ disassemble (memaddr, info, insn)
 	     insert commas into the output stream as well as
 	     when to insert disp[reg] expressions onto the
 	     output stream.  */
-	  
+
 	  for (opindex_ptr = op->operands, opnum = 1;
 	       *opindex_ptr != 0;
 	       opindex_ptr++, opnum++)
@@ -120,9 +116,9 @@ disassemble (memaddr, info, insn)
 	      int flag;
 	      int status;
 	      bfd_byte buffer[4];
-	      
+
 	      operand = &v850_operands[*opindex_ptr];
-	      
+
 	      if (operand->extract)
 		value = (operand->extract) (insn, 0);
 	      else
@@ -153,56 +149,70 @@ disassemble (memaddr, info, insn)
 		   Else we just need a comma.
 
 		   We may need to output a trailing ']' if the last operand
-		   in an instruction is the register for a memory address. 
+		   in an instruction is the register for a memory address.
 
 		   The exception (and there's always an exception) is the
 		   "jmp" insn which needs square brackets around it's only
 		   register argument.  */
 
-	           if (memop && opnum == memop + 1) info->fprintf_func (info->stream, "[");
-	      else if (memop && opnum == memop + 2) info->fprintf_func (info->stream, "],");
-	      else if (memop == 1 && opnum == 1
-		       && (operand->flags & V850_OPERAND_REG))
-		                                    info->fprintf_func (info->stream, "[");
-	      else if (opnum > 1)	            info->fprintf_func (info->stream, ", ");
-
-	      /* extract the flags, ignorng ones which do not effect disassembly output. */
+	           if (memop && opnum == memop + 1)
+		     info->fprintf_func (info->stream, "[");
+		   else if (memop && opnum == memop + 2)
+		     info->fprintf_func (info->stream, "],");
+		   else if (memop == 1 && opnum == 1
+			    && (operand->flags & V850_OPERAND_REG))
+		     info->fprintf_func (info->stream, "[");
+		   else if (opnum > 1)
+		     info->fprintf_func (info->stream, ", ");
+
+	      /* Extract the flags, ignorng ones which
+		 do not effect disassembly output. */
 	      flag = operand->flags;
 	      flag &= ~ V850_OPERAND_SIGNED;
 	      flag &= ~ V850_OPERAND_RELAX;
 	      flag &= - flag;
-	      
+
 	      switch (flag)
 		{
-		case V850_OPERAND_REG:  info->fprintf_func (info->stream, "%s", v850_reg_names[value]); break;
-		case V850_OPERAND_SRG:  info->fprintf_func (info->stream, "%s", v850_sreg_names[value]); break;
-		case V850_OPERAND_CC:   info->fprintf_func (info->stream, "%s", v850_cc_names[value]); break;
-		case V850_OPERAND_EP:   info->fprintf_func (info->stream, "ep"); break;
-		default:                info->fprintf_func (info->stream, "%d", value); break;
+		case V850_OPERAND_REG:
+		  info->fprintf_func (info->stream, "%s", v850_reg_names[value]);
+		  break;
+		case V850_OPERAND_SRG:
+		  info->fprintf_func (info->stream, "%s", v850_sreg_names[value]);
+		  break;
+		case V850_OPERAND_CC:
+		  info->fprintf_func (info->stream, "%s", v850_cc_names[value]);
+		  break;
+		case V850_OPERAND_EP:
+		  info->fprintf_func (info->stream, "ep");
+		  break;
+		default:
+		  info->fprintf_func (info->stream, "%d", value);
+		  break;
 		case V850_OPERAND_DISP:
 		  {
 		    bfd_vma addr = value + memaddr;
-		    
-		    /* On the v850 the top 8 bits of an address are used by an overlay manager.
-		       Thus it may happen that when we are looking for a symbol to match
-		       against an address with some of its top bits set, the search fails to
-		       turn up an exact match.  In this case we try to find an exact match
-		       against a symbol in the lower address space, and if we find one, we
-		       use that address.   We only do this for JARL instructions however, as
-		       we do not want to misinterpret branch instructions.  */
+
+		    /* On the v850 the top 8 bits of an address are used by an
+		       overlay manager.  Thus it may happen that when we are
+		       looking for a symbol to match against an address with
+		       some of its top bits set, the search fails to turn up an
+		       exact match.  In this case we try to find an exact match
+		       against a symbol in the lower address space, and if we
+		       find one, we use that address.   We only do this for
+		       JARL instructions however, as we do not want to
+		       misinterpret branch instructions.  */
 		    if (operand->bits == 22)
 		      {
 			if ( ! info->symbol_at_address_func (addr, info)
 			    && ((addr & 0xFF000000) != 0)
 			    && info->symbol_at_address_func (addr & 0x00FFFFFF, info))
-			  {
-			    addr &= 0x00FFFFFF;
-			  }
+			  addr &= 0x00FFFFFF;
 		      }
 		    info->print_address_func (addr, info);
 		    break;
 		  }
-		    
+
 		case V850E_PUSH_POP:
 		  {
 		    static int list12_regs[32]   = { 30,  0,  0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  0,  0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 };
@@ -213,17 +223,20 @@ disassemble (memaddr, info, insn)
 		    unsigned long int mask = 0;
 		    int pc = 0;
 		    int sr = 0;
-		    
-		    
+
 		    switch (operand->shift)
 		      {
 		      case 0xffe00001: regs = list12_regs; break;
 		      case 0xfff8000f: regs = list18_h_regs; break;
-		      case 0xfff8001f: regs = list18_l_regs; value &= ~0x10; break;  /* Do not include magic bit */
+		      case 0xfff8001f:
+			regs = list18_l_regs;
+			value &= ~0x10;  /* Do not include magic bit.  */
+			  break;
 		      default:
 			/* xgettext:c-format */
-			fprintf (stderr, _("unknown operand shift: %x\n"), operand->shift );
-			abort();
+			fprintf (stderr, _("unknown operand shift: %x\n"),
+				 operand->shift);
+			abort ();
 		      }
 
 		    for (i = 0; i < 32; i++)
@@ -234,7 +247,9 @@ disassemble (memaddr, info, insn)
 			      {
 			      default: mask |= (1 << regs[ i ]); break;
 				/* xgettext:c-format */
-			      case 0:  fprintf (stderr, _("unknown pop reg: %d\n"), i ); abort();
+			      case 0:
+				fprintf (stderr, _("unknown pop reg: %d\n"), i );
+				abort ();
 			      case -1: pc = 1; break;
 			      case -2: sr = 1; break;
 			      }
@@ -242,14 +257,14 @@ disassemble (memaddr, info, insn)
 		      }
 
 		    info->fprintf_func (info->stream, "{");
-		    
+
 		    if (mask || pc || sr)
 		      {
 			if (mask)
 			  {
 			    unsigned int bit;
 			    int shown_one = 0;
-			    
+
 			    for (bit = 0; bit < 32; bit++)
 			      if (mask & (1 << bit))
 				{
@@ -260,9 +275,10 @@ disassemble (memaddr, info, insn)
 				    info->fprintf_func (info->stream, ", ");
 				  else
 				    shown_one = 1;
-				  
-				  info->fprintf_func (info->stream, v850_reg_names[first]);
-				  
+
+				  info->fprintf_func (info->stream,
+						      v850_reg_names[first]);
+
 				  for (bit++; bit < 32; bit++)
 				    if ((mask & (1 << bit)) == 0)
 				      break;
@@ -270,43 +286,44 @@ disassemble (memaddr, info, insn)
 				  last = bit;
 
 				  if (last > first + 1)
-				    {
-				      info->fprintf_func (info->stream, " - %s", v850_reg_names[ last - 1 ]);
-				    }
+				    info->fprintf_func (info->stream, " - %s",
+							v850_reg_names[last - 1]);
 				}
 			  }
-			
+
 			if (pc)
 			  info->fprintf_func (info->stream, "%sPC", mask ? ", " : "");
 			if (sr)
 			  info->fprintf_func (info->stream, "%sSR", (mask || pc) ? ", " : "");
 		      }
-		    
+
 		    info->fprintf_func (info->stream, "}");
 		  }
 		break;
-		  
+
 		case V850E_IMMEDIATE16:
-		  status = info->read_memory_func (memaddr + bytes_read, buffer, 2, info);
+		  status = info->read_memory_func (memaddr + bytes_read,
+						   buffer, 2, info);
 		  if (status == 0)
 		    {
 		      bytes_read += 2;
 		      value = bfd_getl16 (buffer);
 
-		      /* If this is a DISPOSE instruction with ff set to 0x10, then shift value up by 16.  */
+		      /* If this is a DISPOSE instruction with ff
+			 set to 0x10, then shift value up by 16.  */
 		      if ((insn & 0x001fffc0) == 0x00130780)
 			value <<= 16;
 
 		      info->fprintf_func (info->stream, "0x%x", value);
 		    }
 		  else
-		    {
-		      info->memory_error_func (status, memaddr + bytes_read, info);
-		    }
+		    info->memory_error_func (status, memaddr + bytes_read,
+					     info);
 		  break;
-		  
+
 		case V850E_IMMEDIATE32:
-		  status = info->read_memory_func (memaddr + bytes_read, buffer, 4, info);
+		  status = info->read_memory_func (memaddr + bytes_read,
+						   buffer, 4, info);
 		  if (status == 0)
 		    {
 		      bytes_read += 4;
@@ -314,11 +331,10 @@ disassemble (memaddr, info, insn)
 		      info->fprintf_func (info->stream, "0x%lx", value);
 		    }
 		  else
-		    {
-		      info->memory_error_func (status, memaddr + bytes_read, info);
-		    }
+		    info->memory_error_func (status, memaddr + bytes_read,
+					     info);
 		  break;
-		}		  
+		}
 
 	      /* Handle jmp correctly.  */
 	      if (memop == 1 && opnum == 1
@@ -347,22 +363,19 @@ disassemble (memaddr, info, insn)
   return bytes_read;
 }
 
-int 
-print_insn_v850 (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info * info;
+int
+print_insn_v850 (bfd_vma memaddr, struct disassemble_info * info)
 {
   int status;
   bfd_byte buffer[4];
   unsigned long insn = 0;
 
   /* First figure out how big the opcode is.  */
-  
   status = info->read_memory_func (memaddr, buffer, 2, info);
   if (status == 0)
     {
       insn = bfd_getl16 (buffer);
-      
+
       if (   (insn & 0x0600) == 0x0600
 	  && (insn & 0xffe0) != 0x0620)
 	{
@@ -373,7 +386,7 @@ print_insn_v850 (memaddr, info)
 	    insn = bfd_getl32 (buffer);
 	}
     }
-  
+
   if (status != 0)
     {
       info->memory_error_func (status, memaddr, info);
diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index d69157d..c6dfe8b 100644
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -1,5 +1,5 @@
 /* Assemble V850 instructions.
-   Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003
+   Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
@@ -14,7 +14,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include "sysdep.h"
 #include "opcode/v850.h"
@@ -34,30 +35,6 @@
 
 /* Two-word opcodes.  */
 #define two(x,y)	((unsigned int) (x) | ((unsigned int) (y) << 16))
-
-static long unsigned insert_d9      PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_d9     PARAMS ((long unsigned, int *));
-static long unsigned insert_d22     PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_d22    PARAMS ((long unsigned, int *));
-static long unsigned insert_d16_15  PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_d16_15 PARAMS ((long unsigned, int *));
-static long unsigned insert_d8_7    PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_d8_7   PARAMS ((long unsigned, int *));
-static long unsigned insert_d8_6    PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_d8_6   PARAMS ((long unsigned, int *));
-static long unsigned insert_d5_4    PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_d5_4   PARAMS ((long unsigned, int *));
-static long unsigned insert_d16_16  PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_d16_16 PARAMS ((long unsigned, int *));
-static long unsigned insert_i9      PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_i9     PARAMS ((long unsigned, int *));
-static long unsigned insert_u9      PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_u9     PARAMS ((long unsigned, int *));
-static long unsigned insert_spe     PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_spe    PARAMS ((long unsigned, int *));
-static long unsigned insert_i5div   PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_i5div  PARAMS ((long unsigned, int *));
-
 
 /* The functions used to insert and extract complicated operands.  */
 
@@ -73,10 +50,7 @@ static const char * not_aligned  = N_ ("displacement value is not aligned");
 static const char * immediate_out_of_range = N_ ("immediate value is out of range");
 
 static unsigned long
-insert_d9 (insn, value, errmsg)
-     unsigned long insn;
-     long          value;
-     const char ** errmsg;
+insert_d9 (unsigned long insn, long value, const char ** errmsg)
 {
   if (value > 0xff || value < -0x100)
     {
@@ -88,13 +62,11 @@ insert_d9 (insn, value, errmsg)
   else if ((value % 2) != 0)
     * errmsg = _("branch to odd offset");
 
-  return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
+  return insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3);
 }
 
 static unsigned long
-extract_d9 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_d9 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
 
@@ -105,10 +77,7 @@ extract_d9 (insn, invalid)
 }
 
 static unsigned long
-insert_d22 (insn, value, errmsg)
-     unsigned long insn;
-     long          value;
-     const char ** errmsg;
+insert_d22 (unsigned long insn, long value, const char ** errmsg)
 {
   if (value > 0x1fffff || value < -0x200000)
     {
@@ -120,13 +89,11 @@ insert_d22 (insn, value, errmsg)
   else if ((value % 2) != 0)
     * errmsg = _("branch to odd offset");
 
-  return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16));
+  return insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16);
 }
 
 static unsigned long
-extract_d22 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_d22 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   signed long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16);
 
@@ -134,10 +101,7 @@ extract_d22 (insn, invalid)
 }
 
 static unsigned long
-insert_d16_15 (insn, value, errmsg)
-     unsigned long insn;
-     long          value;
-     const char ** errmsg;
+insert_d16_15 (unsigned long insn, long value, const char ** errmsg)
 {
   if (value > 0x7fff || value < -0x8000)
     {
@@ -153,9 +117,7 @@ insert_d16_15 (insn, value, errmsg)
 }
 
 static unsigned long
-extract_d16_15 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_d16_15 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   signed long ret = (insn & 0xfffe0000);
 
@@ -163,10 +125,7 @@ extract_d16_15 (insn, invalid)
 }
 
 static unsigned long
-insert_d8_7 (insn, value, errmsg)
-     unsigned long insn;
-     long          value;
-     const char ** errmsg;
+insert_d8_7 (unsigned long insn, long value, const char ** errmsg)
 {
   if (value > 0xff || value < 0)
     {
@@ -180,13 +139,11 @@ insert_d8_7 (insn, value, errmsg)
 
   value >>= 1;
 
-  return (insn | (value & 0x7f));
+  return insn | (value & 0x7f);
 }
 
 static unsigned long
-extract_d8_7 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_d8_7 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   unsigned long ret = (insn & 0x7f);
 
@@ -194,10 +151,7 @@ extract_d8_7 (insn, invalid)
 }
 
 static unsigned long
-insert_d8_6 (insn, value, errmsg)
-     unsigned long insn;
-     long          value;
-     const char ** errmsg;
+insert_d8_6 (unsigned long insn, long value, const char ** errmsg)
 {
   if (value > 0xff || value < 0)
     {
@@ -211,13 +165,11 @@ insert_d8_6 (insn, value, errmsg)
 
   value >>= 1;
 
-  return (insn | (value & 0x7e));
+  return insn | (value & 0x7e);
 }
 
 static unsigned long
-extract_d8_6 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_d8_6 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   unsigned long ret = (insn & 0x7e);
 
@@ -225,10 +177,7 @@ extract_d8_6 (insn, invalid)
 }
 
 static unsigned long
-insert_d5_4 (insn, value, errmsg)
-     unsigned long insn;
-     long          value;
-     const char ** errmsg;
+insert_d5_4 (unsigned long insn, long value, const char ** errmsg)
 {
   if (value > 0x1f || value < 0)
     {
@@ -242,13 +191,11 @@ insert_d5_4 (insn, value, errmsg)
 
   value >>= 1;
 
-  return (insn | (value & 0x0f));
+  return insn | (value & 0x0f);
 }
 
 static unsigned long
-extract_d5_4 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_d5_4 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   unsigned long ret = (insn & 0x0f);
 
@@ -256,36 +203,28 @@ extract_d5_4 (insn, invalid)
 }
 
 static unsigned long
-insert_d16_16 (insn, value, errmsg)
-     unsigned long insn;
-     signed long   value;
-     const char ** errmsg;
+insert_d16_16 (unsigned long insn, signed long value, const char ** errmsg)
 {
   if (value > 0x7fff || value < -0x8000)
     * errmsg = _(out_of_range);
 
-  return (insn | ((value & 0xfffe) << 16) | ((value & 1) << 5));
+  return insn | ((value & 0xfffe) << 16) | ((value & 1) << 5);
 }
 
 static unsigned long
-extract_d16_16 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_d16_16 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   signed long ret = insn & 0xfffe0000;
 
   ret >>= 16;
 
   ret |= ((insn & 0x20) >> 5);
-  
+
   return ret;
 }
 
 static unsigned long
-insert_i9 (insn, value, errmsg)
-     unsigned long insn;
-     signed long   value;
-     const char ** errmsg;
+insert_i9 (unsigned long insn, signed long value, const char ** errmsg)
 {
   if (value > 0xff || value < -0x100)
     * errmsg = _(immediate_out_of_range);
@@ -294,9 +233,7 @@ insert_i9 (insn, value, errmsg)
 }
 
 static unsigned long
-extract_i9 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_i9 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   signed long ret = insn & 0x003c0000;
 
@@ -304,17 +241,15 @@ extract_i9 (insn, invalid)
   ret >>= 23;
 
   ret |= (insn & 0x1f);
-  
+
   return ret;
 }
 
 static unsigned long
-insert_u9 (insn, v, errmsg)
-     unsigned long insn;
-     long v;
-     const char ** errmsg;
+insert_u9 (unsigned long insn, long v, const char ** errmsg)
 {
   unsigned long value = (unsigned long) v;
+
   if (value > 0x1ff)
     * errmsg = _(immediate_out_of_range);
 
@@ -322,24 +257,19 @@ insert_u9 (insn, v, errmsg)
 }
 
 static unsigned long
-extract_u9 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_u9 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   unsigned long ret = insn & 0x003c0000;
 
   ret >>= 13;
 
   ret |= (insn & 0x1f);
-  
+
   return ret;
 }
 
 static unsigned long
-insert_spe (insn, v, errmsg)
-     unsigned long insn;
-     long v;
-     const char ** errmsg;
+insert_spe (unsigned long insn, long v, const char ** errmsg)
 {
   unsigned long value = (unsigned long) v;
 
@@ -350,18 +280,14 @@ insert_spe (insn, v, errmsg)
 }
 
 static unsigned long
-extract_spe (insn, invalid)
-     unsigned long insn ATTRIBUTE_UNUSED;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_spe (unsigned long insn ATTRIBUTE_UNUSED,
+	     int * invalid ATTRIBUTE_UNUSED)
 {
   return 3;
 }
 
 static unsigned long
-insert_i5div (insn, v, errmsg)
-     unsigned long insn;
-     long v;
-     const char ** errmsg;
+insert_i5div (unsigned long insn, long v, const char ** errmsg)
 {
   unsigned long value = (unsigned long) v;
 
@@ -376,21 +302,19 @@ insert_i5div (insn, v, errmsg)
     * errmsg = _("immediate value must be even");
 
   value = 32 - value;
-  
+
   return insn | ((value & 0x1e) << 17);
 }
 
 static unsigned long
-extract_i5div (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_i5div (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   unsigned long ret = insn & 0x3c0000;
 
   ret >>= 17;
 
   ret = 32 - ret;
-  
+
   return ret;
 }
 
@@ -401,11 +325,11 @@ extract_i5div (insn, invalid)
 const struct v850_operand v850_operands[] =
 {
 #define UNUSED	0
-  { 0, 0, NULL, NULL, 0 }, 
+  { 0, 0, NULL, NULL, 0 },
 
 /* The R1 field in a format 1, 6, 7, or 9 insn.  */
 #define R1	(UNUSED + 1)
-  { 5, 0, NULL, NULL, V850_OPERAND_REG }, 
+  { 5, 0, NULL, NULL, V850_OPERAND_REG },
 
 /* As above, but register 0 is not allowed.  */
 #define R1_NOTR0 (R1 + 1)
@@ -421,7 +345,7 @@ const struct v850_operand v850_operands[] =
 
 /* The imm5 field in a format 2 insn.  */
 #define I5	(R2_NOTR0 + 1)
-  { 5, 0, NULL, NULL, V850_OPERAND_SIGNED }, 
+  { 5, 0, NULL, NULL, V850_OPERAND_SIGNED },
 
 /* The unsigned imm5 field in a format 2 insn.  */
 #define I5U	(I5 + 1)
@@ -429,7 +353,7 @@ const struct v850_operand v850_operands[] =
 
 /* The imm16 field in a format 6 insn.  */
 #define I16	(I5U + 1)
-  { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, 
+  { 16, 16, NULL, NULL, V850_OPERAND_SIGNED },
 
 /* The signed disp7 field in a format 4 insn.  */
 #define D7	(I16 + 1)
@@ -437,7 +361,7 @@ const struct v850_operand v850_operands[] =
 
 /* The disp16 field in a format 6 insn.  */
 #define D16_15	(D7 + 1)
-  { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, 
+  { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED },
 
 /* The 3 bit immediate field in format 8 insn.  */
 #define B3	(D16_15 + 1)
@@ -465,7 +389,7 @@ const struct v850_operand v850_operands[] =
 
 /* The imm16 field (unsigned) in a format 6 insn.  */
 #define I16U	(EP + 1)
-  { 16, 16, NULL, NULL, 0}, 
+  { 16, 16, NULL, NULL, 0},
 
 /* The R2 field as a system register.  */
 #define SR2	(I16U + 1)
@@ -473,7 +397,7 @@ const struct v850_operand v850_operands[] =
 
 /* The disp16 field in a format 8 insn.  */
 #define D16	(SR2 + 1)
-  { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, 
+  { 16, 16, NULL, NULL, V850_OPERAND_SIGNED },
 
 /* The DISP9 field in a format 3 insn, relaxable.  */
 #define D9_RELAX	(D16 + 1)
@@ -495,7 +419,7 @@ const struct v850_operand v850_operands[] =
 
 /* The disp16 field in an format 7 unsigned byte load insn.  */
 #define D16_16	(D5_4 + 1)
-  { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 }, 
+  { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 },
 
 /* Third register in conditional moves.  */
 #define R3	(D16_16 + 1)
@@ -507,31 +431,31 @@ const struct v850_operand v850_operands[] =
 
 /* The imm9 field in a multiply word.  */
 #define I9	(MOVCC + 1)
-  { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED }, 
+  { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED },
 
 /* The unsigned imm9 field in a multiply word.  */
 #define U9	(I9 + 1)
-  { 9, 0, insert_u9, extract_u9, 0 }, 
+  { 9, 0, insert_u9, extract_u9, 0 },
 
 /* A list of registers in a prepare/dispose instruction.  */
 #define LIST12	(U9 + 1)
-  { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP }, 
+  { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP },
 
 /* The IMM6 field in a call instruction.  */
 #define I6	(LIST12 + 1)
-  { 6, 0, NULL, NULL, 0 }, 
+  { 6, 0, NULL, NULL, 0 },
 
 /* The 16 bit immediate following a 32 bit instruction.  */
 #define IMM16	(I6 + 1)
-  { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 }, 
+  { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 },
 
 /* The 32 bit immediate following a 32 bit instruction.  */
 #define IMM32	(IMM16 + 1)
-  { 0, 0, NULL, NULL, V850E_IMMEDIATE32 }, 
+  { 0, 0, NULL, NULL, V850E_IMMEDIATE32 },
 
 /* The imm5 field in a push/pop instruction.  */
 #define IMM5	(IMM32 + 1)
-  { 5, 1, NULL, NULL, 0 }, 
+  { 5, 1, NULL, NULL, 0 },
 
 /* Reg2 in dispose instruction.  */
 #define R2DISPOSE	(IMM5 + 1)
@@ -543,17 +467,17 @@ const struct v850_operand v850_operands[] =
 
 /* The IMM5 field in a divide N step instruction.  */
 #define I5DIV	(SP + 1)
-  { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED }, 
+  { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED },
 
   /* The list of registers in a PUSHMH/POPMH instruction.  */
 #define LIST18_H (I5DIV + 1)
-  { -1, 0xfff8000f, NULL, NULL, V850E_PUSH_POP }, 
+  { -1, 0xfff8000f, NULL, NULL, V850E_PUSH_POP },
 
   /* The list of registers in a PUSHML/POPML instruction.  */
 #define LIST18_L (LIST18_H + 1)
   /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c.  */
   { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP },
-} ; 
+};
 
 
 /* Reg - Reg instruction format (Format I).  */
@@ -586,7 +510,7 @@ const struct v850_operand v850_operands[] =
    OPERANDS is the list of operands.
    MEMOP specifies which operand (if any) is a memory operand.
    PROCESSORS specifies which CPU(s) support the opcode.
-   
+
    The disassembler reads the table in order and prints the first
    instruction which matches, so this table is sorted to put more
    specific instructions before more general instructions.  It is also
@@ -609,7 +533,7 @@ const struct v850_opcode v850_opcodes[] =
 { "dbtrap",	one (0xf840),		one (0xffff),		{UNUSED},   		0, PROCESSOR_V850E1 },
 
 { "jmp",	one (0x0060),		one (0xffe0),	      	{R1}, 			1, PROCESSOR_ALL },
-  
+
 /* Load/store instructions.  */
 { "sld.bu",     one (0x0060),		one (0x07f0),         	{D4,   EP,   R2_NOTR0},	1, PROCESSOR_V850E1 },
 { "sld.bu",     one (0x0060),		one (0x07f0),         	{D4,   EP,   R2_NOTR0},	1, PROCESSOR_V850E },
@@ -641,7 +565,7 @@ const struct v850_opcode v850_opcodes[] =
 { "ld.h",	two (0x0720, 0x0000),	two (0x07e0, 0x0001), 	{D16_15, R1, R2}, 	1, PROCESSOR_ALL },
 { "ld.w",	two (0x0720, 0x0001),	two (0x07e0, 0x0001), 	{D16_15, R1, R2}, 	1, PROCESSOR_ALL },
 { "ld.bu",	two (0x0780, 0x0001),   two (0x07c0, 0x0001), 	{D16_16, R1, R2_NOTR0},	1, PROCESSOR_NOT_V850 },
-{ "ld.hu",	two (0x07e0, 0x0001),   two (0x07e0, 0x0001), 	{D16_15, R1, R2_NOTR0},	1, PROCESSOR_NOT_V850 },  
+{ "ld.hu",	two (0x07e0, 0x0001),   two (0x07e0, 0x0001), 	{D16_15, R1, R2_NOTR0},	1, PROCESSOR_NOT_V850 },
 { "st.b",	two (0x0740, 0x0000),	two (0x07e0, 0x0000), 	{R2, D16, R1}, 		2, PROCESSOR_ALL },
 { "st.h",	two (0x0760, 0x0000),	two (0x07e0, 0x0001), 	{R2, D16_15, R1}, 	2, PROCESSOR_ALL },
 { "st.w",	two (0x0760, 0x0001),	two (0x07e0, 0x0001), 	{R2, D16_15, R1}, 	2, PROCESSOR_ALL },
@@ -675,7 +599,7 @@ const struct v850_opcode v850_opcodes[] =
 { "divhu",	two (0x07e0, 0x0282),   two (0x07e0, 0x07ff), 	{R1, R2, R3}, 		0, PROCESSOR_NOT_V850 },
 { "divh",	two (0x07e0, 0x0280),   two (0x07e0, 0x07ff), 	{R1, R2, R3}, 		0, PROCESSOR_NOT_V850 },
 { "divh",	OP  (0x02),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
-  
+
 { "nop",	one (0x00),		one (0xffff),		{0}, 			0, PROCESSOR_ALL },
 { "mov",	OP  (0x10),		OP_MASK,		{I5, R2_NOTR0},		0, PROCESSOR_ALL },
 { "mov",	one (0x0620),		one (0xffe0),		{IMM32, R1_NOTR0},	0, PROCESSOR_NOT_V850 },
@@ -692,7 +616,7 @@ const struct v850_opcode v850_opcodes[] =
 { "mulhi",	OP  (0x37),		OP_MASK,		{I16, R1, R2_NOTR0},	0, PROCESSOR_ALL },
 { "cmp",	OP  (0x0f),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
 { "cmp",	OP  (0x13),		OP_MASK,		IF2, 			0, PROCESSOR_ALL },
-  
+
 /* Saturated operation instructions.  */
 { "satadd",	OP (0x11),		OP_MASK,		{I5, R2_NOTR0},		0, PROCESSOR_ALL },
 { "satadd",	OP (0x06),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
@@ -772,9 +696,9 @@ const struct v850_opcode v850_opcodes[] =
 { "jnz",	BOP (0xa),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "jsa",	BOP (0xd),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "jbr",	BOP (0x5),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
-  
+
 { "jr",		one (0x0780),		two (0xffc0, 0x0001),	{D22}, 			0, PROCESSOR_ALL },
-{ "jarl",	one (0x0780),		two (0x07c0, 0x0001),	{D22, R2}, 		0, PROCESSOR_ALL}, 
+{ "jarl",	one (0x0780),		two (0x07c0, 0x0001),	{D22, R2}, 		0, PROCESSOR_ALL },
 
 /* Bit manipulation instructions.  */
 { "set1",	two (0x07c0, 0x0000),	two (0xc7e0, 0x0000),	{B3, D16, R1}, 		2, PROCESSOR_ALL },
diff --git a/opcodes/vax-dis.c b/opcodes/vax-dis.c
index 8b5935a..0b96414 100644
--- a/opcodes/vax-dis.c
+++ b/opcodes/vax-dis.c
@@ -15,7 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <setjmp.h>
 #include <string.h>
@@ -23,14 +24,6 @@
 #include "opcode/vax.h"
 #include "dis-asm.h"
 
-/* Local function prototypes */
-static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *));
-static int print_insn_arg
-  PARAMS ((const char *, unsigned char *, bfd_vma, disassemble_info *));
-static int print_insn_mode
-  PARAMS ((const char *, int, unsigned char *, bfd_vma, disassemble_info *));
-
-
 static char *reg_names[] =
 {
   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
@@ -53,11 +46,7 @@ static char *entry_mask_bit[] =
 };
 
 /* Sign-extend an (unsigned char). */
-#if __STDC__ == 1
 #define COERCE_SIGNED_CHAR(ch) ((signed char)(ch))
-#else
-#define COERCE_SIGNED_CHAR(ch) ((int)(((ch) ^ 0x80) & 0xFF) - 128)
-#endif
 
 /* Get a 1 byte signed integer.  */
 #define NEXTBYTE(p)  \
@@ -96,9 +85,7 @@ struct private
    ? 1 : fetch_data ((info), (addr)))
 
 static int
-fetch_data (info, addr)
-     struct disassemble_info *info;
-     bfd_byte *addr;
+fetch_data (struct disassemble_info *info, bfd_byte *addr)
 {
   int status;
   struct private *priv = (struct private *) info->private_data;
@@ -208,13 +195,165 @@ is_function_entry (struct disassemble_info *info, bfd_vma addr)
   return FALSE;
 }
 
+static int
+print_insn_mode (const char *d,
+		 int size,
+		 unsigned char *p0,
+		 bfd_vma addr,	/* PC for this arg to be relative to.  */
+		 disassemble_info *info)
+{
+  unsigned char *p = p0;
+  unsigned char mode, reg;
+
+  /* Fetch and interpret mode byte.  */
+  mode = (unsigned char) NEXTBYTE (p);
+  reg = mode & 0xF;
+  switch (mode & 0xF0)
+    {
+    case 0x00:
+    case 0x10:
+    case 0x20:
+    case 0x30: /* Literal mode			$number.  */
+      if (d[1] == 'd' || d[1] == 'f' || d[1] == 'g' || d[1] == 'h')
+	(*info->fprintf_func) (info->stream, "$0x%x [%c-float]", mode, d[1]);
+      else
+        (*info->fprintf_func) (info->stream, "$0x%x", mode);
+      break;
+    case 0x40: /* Index:			base-addr[Rn] */
+      p += print_insn_mode (d, size, p0 + 1, addr + 1, info);
+      (*info->fprintf_func) (info->stream, "[%s]", reg_names[reg]);
+      break;
+    case 0x50: /* Register:			Rn */
+      (*info->fprintf_func) (info->stream, "%s", reg_names[reg]);
+      break;
+    case 0x60: /* Register deferred:		(Rn) */
+      (*info->fprintf_func) (info->stream, "(%s)", reg_names[reg]);
+      break;
+    case 0x70: /* Autodecrement:		-(Rn) */
+      (*info->fprintf_func) (info->stream, "-(%s)", reg_names[reg]);
+      break;
+    case 0x80: /* Autoincrement:		(Rn)+ */
+      if (reg == 0xF)
+	{	/* Immediate?  */
+	  int i;
+
+	  FETCH_DATA (info, p + size);
+	  (*info->fprintf_func) (info->stream, "$0x");
+	  if (d[1] == 'd' || d[1] == 'f' || d[1] == 'g' || d[1] == 'h')
+	    {
+	      int float_word;
+
+	      float_word = p[0] | (p[1] << 8);
+	      if ((d[1] == 'd' || d[1] == 'f')
+		  && (float_word & 0xff80) == 0x8000)
+		{
+		  (*info->fprintf_func) (info->stream, "[invalid %c-float]",
+					 d[1]);
+		}
+	      else
+		{
+	          for (i = 0; i < size; i++)
+		    (*info->fprintf_func) (info->stream, "%02x",
+		                           p[size - i - 1]);
+	          (*info->fprintf_func) (info->stream, " [%c-float]", d[1]);
+		}
+	    }
+	  else
+	    {
+	      for (i = 0; i < size; i++)
+	        (*info->fprintf_func) (info->stream, "%02x", p[size - i - 1]);
+	    }
+	  p += size;
+	}
+      else
+	(*info->fprintf_func) (info->stream, "(%s)+", reg_names[reg]);
+      break;
+    case 0x90: /* Autoincrement deferred:	@(Rn)+ */
+      if (reg == 0xF)
+	(*info->fprintf_func) (info->stream, "*0x%x", NEXTLONG (p));
+      else
+	(*info->fprintf_func) (info->stream, "@(%s)+", reg_names[reg]);
+      break;
+    case 0xB0: /* Displacement byte deferred:	*displ(Rn).  */
+      (*info->fprintf_func) (info->stream, "*");
+    case 0xA0: /* Displacement byte:		displ(Rn).  */
+      if (reg == 0xF)
+	(*info->print_address_func) (addr + 2 + NEXTBYTE (p), info);
+      else
+	(*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTBYTE (p),
+			       reg_names[reg]);
+      break;
+    case 0xD0: /* Displacement word deferred:	*displ(Rn).  */
+      (*info->fprintf_func) (info->stream, "*");
+    case 0xC0: /* Displacement word:		displ(Rn).  */
+      if (reg == 0xF)
+	(*info->print_address_func) (addr + 3 + NEXTWORD (p), info);
+      else
+	(*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTWORD (p),
+			       reg_names[reg]);
+      break;
+    case 0xF0: /* Displacement long deferred:	*displ(Rn).  */
+      (*info->fprintf_func) (info->stream, "*");
+    case 0xE0: /* Displacement long:		displ(Rn).  */
+      if (reg == 0xF)
+	(*info->print_address_func) (addr + 5 + NEXTLONG (p), info);
+      else
+	(*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTLONG (p),
+			       reg_names[reg]);
+      break;
+    }
+
+  return p - p0;
+}
+
+/* Returns number of bytes "eaten" by the operand, or return -1 if an
+   invalid operand was found, or -2 if an opcode tabel error was
+   found. */
+
+static int
+print_insn_arg (const char *d,
+		unsigned char *p0,
+		bfd_vma addr,	/* PC for this arg to be relative to.  */
+		disassemble_info *info)
+{
+  int arg_len;
+
+  /* Check validity of addressing length.  */
+  switch (d[1])
+    {
+    case 'b' : arg_len = 1;	break;
+    case 'd' : arg_len = 8;	break;
+    case 'f' : arg_len = 4;	break;
+    case 'g' : arg_len = 8;	break;
+    case 'h' : arg_len = 16;	break;
+    case 'l' : arg_len = 4;	break;
+    case 'o' : arg_len = 16;	break;
+    case 'w' : arg_len = 2;	break;
+    case 'q' : arg_len = 8;	break;
+    default  : abort ();
+    }
+
+  /* Branches have no mode byte.  */
+  if (d[0] == 'b')
+    {
+      unsigned char *p = p0;
+
+      if (arg_len == 1)
+	(*info->print_address_func) (addr + 1 + NEXTBYTE (p), info);
+      else
+	(*info->print_address_func) (addr + 2 + NEXTWORD (p), info);
+
+      return p - p0;
+    }
+
+  return print_insn_mode (d, arg_len, p0, addr, info);
+}
+
 /* Print the vax instruction at address MEMADDR in debugged memory,
    on INFO->STREAM.  Returns length of the instruction, in bytes.  */
 
 int
-print_insn_vax (memaddr, info)
-     bfd_vma memaddr;
-     disassemble_info *info;
+print_insn_vax (bfd_vma memaddr, disassemble_info *info)
 {
   static bfd_boolean parsed_disassembler_options = FALSE;
   const struct vot *votp;
@@ -223,7 +362,7 @@ print_insn_vax (memaddr, info)
   struct private priv;
   bfd_byte *buffer = priv.the_buffer;
 
-  info->private_data = (PTR) &priv;
+  info->private_data = & priv;
   priv.max_fetched = priv.the_buffer;
   priv.insn_start = memaddr;
 
@@ -237,10 +376,8 @@ print_insn_vax (memaddr, info)
     }
 
   if (setjmp (priv.bailout) != 0)
-    {
-      /* Error return.  */
-      return -1;
-    }
+    /* Error return.  */
+    return -1;
 
   argp = NULL;
   /* Check if the info buffer has more than one byte left since
@@ -275,7 +412,7 @@ print_insn_vax (memaddr, info)
 
   for (votp = &votstrs[0]; votp->name[0]; votp++)
     {
-      register vax_opcodeT opcode = votp->detail.code;
+      vax_opcodeT opcode = votp->detail.code;
 
       /* 2 byte codes match 2 buffer pos. */
       if ((bfd_byte) opcode == buffer[0]
@@ -315,158 +452,3 @@ print_insn_vax (memaddr, info)
   return arg - buffer;
 }
 
-/* Returns number of bytes "eaten" by the operand, or return -1 if an
-   invalid operand was found, or -2 if an opcode tabel error was
-   found. */
-
-static int
-print_insn_arg (d, p0, addr, info)
-     const char *d;
-     unsigned char *p0;
-     bfd_vma addr;		/* PC for this arg to be relative to */
-     disassemble_info *info;
-{
-  int arg_len;
-
-  /* check validity of addressing length */
-  switch (d[1])
-    {
-    case 'b' : arg_len = 1;	break;
-    case 'd' : arg_len = 8;	break;
-    case 'f' : arg_len = 4;	break;
-    case 'g' : arg_len = 8;	break;
-    case 'h' : arg_len = 16;	break;
-    case 'l' : arg_len = 4;	break;
-    case 'o' : arg_len = 16;	break;
-    case 'w' : arg_len = 2;	break;
-    case 'q' : arg_len = 8;	break;
-    default  : abort();
-    }
-
-  /* branches have no mode byte */
-  if (d[0] == 'b')
-    {
-      unsigned char *p = p0;
-
-      if (arg_len == 1)
-	(*info->print_address_func) (addr + 1 + NEXTBYTE (p), info);
-      else
-	(*info->print_address_func) (addr + 2 + NEXTWORD (p), info);
-
-      return p - p0;
-    }
-
-  return print_insn_mode (d, arg_len, p0, addr, info);
-}
-
-static int
-print_insn_mode (d, size, p0, addr, info)
-     const char *d;
-     int size;
-     unsigned char *p0;
-     bfd_vma addr;		/* PC for this arg to be relative to */
-     disassemble_info *info;
-{
-  unsigned char *p = p0;
-  unsigned char mode, reg;
-
-  /* fetch and interpret mode byte */
-  mode = (unsigned char) NEXTBYTE (p);
-  reg = mode & 0xF;
-  switch (mode & 0xF0)
-    {
-    case 0x00:
-    case 0x10:
-    case 0x20:
-    case 0x30: /* literal mode			$number */
-      if (d[1] == 'd' || d[1] == 'f' || d[1] == 'g' || d[1] == 'h')
-	(*info->fprintf_func) (info->stream, "$0x%x [%c-float]", mode, d[1]);
-      else
-        (*info->fprintf_func) (info->stream, "$0x%x", mode);
-      break;
-    case 0x40: /* index:			base-addr[Rn] */
-      p += print_insn_mode (d, size, p0 + 1, addr + 1, info);
-      (*info->fprintf_func) (info->stream, "[%s]", reg_names[reg]);
-      break;
-    case 0x50: /* register:			Rn */
-      (*info->fprintf_func) (info->stream, "%s", reg_names[reg]);
-      break;
-    case 0x60: /* register deferred:		(Rn) */
-      (*info->fprintf_func) (info->stream, "(%s)", reg_names[reg]);
-      break;
-    case 0x70: /* autodecrement:		-(Rn) */
-      (*info->fprintf_func) (info->stream, "-(%s)", reg_names[reg]);
-      break;
-    case 0x80: /* autoincrement:		(Rn)+ */
-      if (reg == 0xF)
-	{	/* immediate? */
-	  int i;
-
-	  FETCH_DATA (info, p + size);
-	  (*info->fprintf_func) (info->stream, "$0x");
-	  if (d[1] == 'd' || d[1] == 'f' || d[1] == 'g' || d[1] == 'h')
-	    {
-	      int float_word;
-
-	      float_word = p[0] | (p[1] << 8);
-	      if ((d[1] == 'd' || d[1] == 'f')
-		  && (float_word & 0xff80) == 0x8000)
-		{
-		  (*info->fprintf_func) (info->stream, "[invalid %c-float]",
-					 d[1]);
-		}
-	      else
-		{
-	          for (i = 0; i < size; i++)
-		    (*info->fprintf_func) (info->stream, "%02x",
-		                           p[size - i - 1]);
-	          (*info->fprintf_func) (info->stream, " [%c-float]", d[1]);
-		}
-	    }
-	  else
-	    {
-	      for (i = 0; i < size; i++)
-	        (*info->fprintf_func) (info->stream, "%02x", p[size - i - 1]);
-	    }
-	  p += size;
-	}
-      else
-	(*info->fprintf_func) (info->stream, "(%s)+", reg_names[reg]);
-      break;
-    case 0x90: /* autoincrement deferred:	@(Rn)+ */
-      if (reg == 0xF)
-	(*info->fprintf_func) (info->stream, "*0x%x", NEXTLONG (p));
-      else
-	(*info->fprintf_func) (info->stream, "@(%s)+", reg_names[reg]);
-      break;
-    case 0xB0: /* displacement byte deferred:	*displ(Rn) */
-      (*info->fprintf_func) (info->stream, "*");
-    case 0xA0: /* displacement byte:		displ(Rn) */
-      if (reg == 0xF)
-	(*info->print_address_func) (addr + 2 + NEXTBYTE (p), info);
-      else
-	(*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTBYTE (p),
-			       reg_names[reg]);
-      break;
-    case 0xD0: /* displacement word deferred:	*displ(Rn) */
-      (*info->fprintf_func) (info->stream, "*");
-    case 0xC0: /* displacement word:		displ(Rn) */
-      if (reg == 0xF)
-	(*info->print_address_func) (addr + 3 + NEXTWORD (p), info);
-      else
-	(*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTWORD (p),
-			       reg_names[reg]);
-      break;
-    case 0xF0: /* displacement long deferred:	*displ(Rn) */
-      (*info->fprintf_func) (info->stream, "*");
-    case 0xE0: /* displacement long:		displ(Rn) */
-      if (reg == 0xF)
-	(*info->print_address_func) (addr + 5 + NEXTLONG (p), info);
-      else
-	(*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTLONG (p),
-			       reg_names[reg]);
-      break;
-    }
-
-  return p - p0;
-}
diff --git a/opcodes/w65-dis.c b/opcodes/w65-dis.c
index b9b5ccf..26e11a1 100644
--- a/opcodes/w65-dis.c
+++ b/opcodes/w65-dis.c
@@ -2,19 +2,20 @@
    Copyright 1995, 1998, 2000, 2001, 2002, 2005
    Free Software Foundation, Inc.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "sysdep.h"
@@ -28,25 +29,8 @@ static fprintf_ftype fpr;
 static void *stream;
 static struct disassemble_info *local_info;
 
-static void print_operand PARAMS ((int, char *, int *));
-
-#if 0
-static char *lname[] = { "r0","r1","r2","r3","r4","r5","r6","r7","s0" };
-
-static char *
-findname (val)
-     unsigned int val;
-{
-  if (val >= 0x10 && val <= 0x20)
-    return lname[(val - 0x10) / 2];
-  return 0;
-}
-#endif
 static void
-print_operand (lookup, format, args)
-     int lookup;
-     char *format;
-     int *args;
+print_operand (int lookup, char *format, int *args)
 {
   int val;
   int c;
@@ -58,15 +42,7 @@ print_operand (lookup, format, args)
 	case '$':
 	  val = args[(*format++) - '0'];
 	  if (lookup)
-	    {
-#if 0
-	      name = findname (val);
-	      if (name)
-		fpr (stream, "%s", name);
-	      else
-#endif
-		local_info->print_address_func (val, local_info);
-	    }
+	    local_info->print_address_func (val, local_info);
 	  else
 	    fpr (stream, "0x%x", val);
 
@@ -79,9 +55,7 @@ print_operand (lookup, format, args)
 }
 
 int
-print_insn_w65 (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_w65 (bfd_vma memaddr, struct disassemble_info *info)
 {
   int status = 0;
   unsigned char insn[4];
@@ -90,13 +64,13 @@ print_insn_w65 (memaddr, info)
   int X = 0;
   int M = 0;
   int args[2];
+
   stream = info->stream;
   fpr = info->fprintf_func;
   local_info = info;
+
   for (i = 0; i < 4 && status == 0; i++)
-    {
-      status = info->read_memory_func (memaddr + i, insn + i, 1, info);
-    }
+    status = info->read_memory_func (memaddr + i, insn + i, 1, info);
 
   for (op = optable; op->val != insn[0]; op++)
     ;
diff --git a/opcodes/xstormy16-asm.c b/opcodes/xstormy16-asm.c
index 74a6ecb..0b10878 100644
--- a/opcodes/xstormy16-asm.c
+++ b/opcodes/xstormy16-asm.c
@@ -1,26 +1,27 @@
 /* Assembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-asm.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-asm.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -48,12 +49,6 @@ static const char * parse_insn_normal
 /* -- assembler routines inserted here.  */
 
 /* -- asm.c */
-static const char * parse_mem8
-  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_small_immediate
-  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
-static const char * parse_immediate16
-  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
 
 /* The machine-independent code doesn't know how to disambiguate
      mov (foo),r3
@@ -62,11 +57,10 @@ static const char * parse_immediate16
    where 'foo' is a label.  This helps it out. */
 
 static const char *
-parse_mem8 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_mem8 (CGEN_CPU_DESC cd,
+	    const char **strp,
+	    int opindex,
+	    unsigned long *valuep)
 {
   if (**strp == '(')
     {
@@ -101,11 +95,10 @@ parse_mem8 (cd, strp, opindex, valuep)
    of the small size.  This is somewhat tricky.  */
    
 static const char *
-parse_small_immediate (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_small_immediate (CGEN_CPU_DESC cd,
+		       const char **strp,
+		       int opindex,
+		       unsigned long *valuep)
 {
   bfd_vma value;
   enum cgen_parse_operand_result result;
@@ -116,7 +109,7 @@ parse_small_immediate (cd, strp, opindex, valuep)
 
   errmsg = (* cd->parse_operand_fn)
     (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE,
-     &result, &value);
+     & result, & value);
   
   if (errmsg)
     return errmsg;
@@ -128,14 +121,13 @@ parse_small_immediate (cd, strp, opindex, valuep)
   return NULL;
 }
 
-/* Literal scan be either a normal literal, a @hi() or @lo relocation. */
+/* Literal scan be either a normal literal, a @hi() or @lo relocation.  */
    
 static const char *
-parse_immediate16 (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+parse_immediate16 (CGEN_CPU_DESC cd,
+		   const char **strp,
+		   int opindex,
+		   unsigned long *valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result;
@@ -178,7 +170,7 @@ parse_immediate16 (cd, strp, opindex, valuep)
 /* -- */
 
 const char * xstormy16_cgen_parse_operand
-  PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
 
 /* Main entry point for operand parsing.
 
@@ -194,11 +186,10 @@ const char * xstormy16_cgen_parse_operand
    the handlers.  */
 
 const char *
-xstormy16_cgen_parse_operand (cd, opindex, strp, fields)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     const char ** strp;
-     CGEN_FIELDS * fields;
+xstormy16_cgen_parse_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   const char ** strp,
+			   CGEN_FIELDS * fields)
 {
   const char * errmsg = NULL;
   /* Used by scalar operands that still need to be parsed.  */
@@ -294,8 +285,7 @@ cgen_parse_fn * const xstormy16_cgen_parse_handlers[] =
 };
 
 void
-xstormy16_cgen_init_asm (cd)
-     CGEN_CPU_DESC cd;
+xstormy16_cgen_init_asm (CGEN_CPU_DESC cd)
 {
   xstormy16_cgen_init_opcode_table (cd);
   xstormy16_cgen_init_ibld_table (cd);
@@ -678,30 +668,3 @@ xstormy16_cgen_assemble_insn (CGEN_CPU_DESC cd,
     return NULL;
   }
 }
-
-#if 0 /* This calls back to GAS which we can't do without care.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   This lets GAS parse registers for us.
-   ??? Interesting idea but not currently used.  */
-
-/* Record each member of OPVALS in the assembler's symbol table.
-   FIXME: Not currently used.  */
-
-void
-xstormy16_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
-{
-  CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
-  const CGEN_KEYWORD_ENTRY * ke;
-
-  while ((ke = cgen_keyword_search_next (& search)) != NULL)
-    {
-#if 0 /* Unnecessary, should be done in the search routine.  */
-      if (! xstormy16_cgen_opval_supported (ke))
-	continue;
-#endif
-      cgen_asm_record_register (cd, ke->name, ke->value);
-    }
-}
-
-#endif /* 0 */
diff --git a/opcodes/xstormy16-desc.c b/opcodes/xstormy16-desc.c
index 6f639b9..a63a451 100644
--- a/opcodes/xstormy16-desc.c
+++ b/opcodes/xstormy16-desc.c
@@ -1160,27 +1160,23 @@ static const CGEN_IBASE xstormy16_cgen_insn_table[MAX_INSNS] =
 #undef A
 
 /* Initialize anything needed to be done once, before any cpu_open call.  */
-static void init_tables PARAMS ((void));
 
 static void
-init_tables ()
+init_tables (void)
 {
 }
 
-static const CGEN_MACH * lookup_mach_via_bfd_name
-  PARAMS ((const CGEN_MACH *, const char *));
-static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
-static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
-static void xstormy16_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
+static void build_hw_table      (CGEN_CPU_TABLE *);
+static void build_ifield_table  (CGEN_CPU_TABLE *);
+static void build_operand_table (CGEN_CPU_TABLE *);
+static void build_insn_table    (CGEN_CPU_TABLE *);
+static void xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *);
 
 /* Subroutine of xstormy16_cgen_cpu_open to look up a mach via its bfd name.  */
 
 static const CGEN_MACH *
-lookup_mach_via_bfd_name (table, name)
-     const CGEN_MACH *table;
-     const char *name;
+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
 {
   while (table->name)
     {
@@ -1194,8 +1190,7 @@ lookup_mach_via_bfd_name (table, name)
 /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_hw_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_hw_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -1221,8 +1216,7 @@ build_hw_table (cd)
 /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_ifield_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_ifield_table (CGEN_CPU_TABLE *cd)
 {
   cd->ifld_table = & xstormy16_cgen_ifld_table[0];
 }
@@ -1230,8 +1224,7 @@ build_ifield_table (cd)
 /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.  */
 
 static void
-build_operand_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_operand_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   int machs = cd->machs;
@@ -1239,8 +1232,7 @@ build_operand_table (cd)
   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
      However each entry is indexed by it's enum so there can be holes in
      the table.  */
-  const CGEN_OPERAND **selected =
-    (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
 
   cd->operand_table.init_entries = init;
   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@@ -1263,12 +1255,11 @@ build_operand_table (cd)
    operand elements to be in the table [which they mightn't be].  */
 
 static void
-build_insn_table (cd)
-     CGEN_CPU_TABLE *cd;
+build_insn_table (CGEN_CPU_TABLE *cd)
 {
   int i;
   const CGEN_IBASE *ib = & xstormy16_cgen_insn_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
 
   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
   for (i = 0; i < MAX_INSNS; ++i)
@@ -1281,8 +1272,7 @@ build_insn_table (cd)
 /* Subroutine of xstormy16_cgen_cpu_open to rebuild the tables.  */
 
 static void
-xstormy16_cgen_rebuild_tables (cd)
-     CGEN_CPU_TABLE *cd;
+xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
   unsigned int isas = cd->isas;
@@ -1294,7 +1284,7 @@ xstormy16_cgen_rebuild_tables (cd)
 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
   cd->default_insn_bitsize = UNSET;
   cd->base_insn_bitsize = UNSET;
-  cd->min_insn_bitsize = 65535; /* some ridiculously big number */
+  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
     if (((1 << i) & isas) != 0)
@@ -1306,7 +1296,7 @@ xstormy16_cgen_rebuild_tables (cd)
 	if (cd->default_insn_bitsize == UNSET)
 	  cd->default_insn_bitsize = isa->default_insn_bitsize;
 	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -1315,7 +1305,7 @@ xstormy16_cgen_rebuild_tables (cd)
 	if (cd->base_insn_bitsize == UNSET)
 	  cd->base_insn_bitsize = isa->base_insn_bitsize;
 	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
-	  ; /* this is ok */
+	  ; /* This is ok.  */
 	else
 	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
@@ -1427,12 +1417,12 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     }
   va_end (ap);
 
-  /* mach unspecified means "all" */
+  /* Mach unspecified means "all".  */
   if (machs == 0)
     machs = (1 << MAX_MACHS) - 1;
-  /* base mach is always selected */
+  /* Base mach is always selected.  */
   machs |= 1;
-  /* isa unspecified means "all" */
+  /* ISA unspecified means "all".  */
   if (isas == 0)
     isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
@@ -1465,9 +1455,7 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
    MACH_NAME is the bfd name of the mach.  */
 
 CGEN_CPU_DESC
-xstormy16_cgen_cpu_open_1 (mach_name, endian)
-     const char *mach_name;
-     enum cgen_endian endian;
+xstormy16_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
 {
   return xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
 			       CGEN_CPU_OPEN_ENDIAN, endian,
@@ -1480,8 +1468,7 @@ xstormy16_cgen_cpu_open_1 (mach_name, endian)
    place as some simulator ports use this but they don't use libopcodes.  */
 
 void
-xstormy16_cgen_cpu_close (cd)
-     CGEN_CPU_DESC cd;
+xstormy16_cgen_cpu_close (CGEN_CPU_DESC cd)
 {
   unsigned int i;
   const CGEN_INSN *insns;
@@ -1490,23 +1477,17 @@ xstormy16_cgen_cpu_close (cd)
     {
       insns = cd->macro_insn_table.init_entries;
       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX ((insns)))
-	    regfree (CGEN_INSN_RX (insns));
-	}
+	if (CGEN_INSN_RX ((insns)))
+	  regfree (CGEN_INSN_RX (insns));
     }
 
   if (cd->insn_table.init_entries)
     {
       insns = cd->insn_table.init_entries;
       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
-	{
-	  if (CGEN_INSN_RX (insns))
-	    regfree (CGEN_INSN_RX (insns));
-	}
-    }
-
-  
+	if (CGEN_INSN_RX (insns))
+	  regfree (CGEN_INSN_RX (insns));
+    }  
 
   if (cd->macro_insn_table.init_entries)
     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
diff --git a/opcodes/xstormy16-dis.c b/opcodes/xstormy16-dis.c
index b23b156..91cde6b 100644
--- a/opcodes/xstormy16-dis.c
+++ b/opcodes/xstormy16-dis.c
@@ -1,27 +1,27 @@
 /* Disassembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-dis.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-dis.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
-Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -56,12 +56,11 @@ static int read_insn
   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
    unsigned long *);
 
-/* -- disassembler routines inserted here */
+/* -- disassembler routines inserted here.  */
 
 
 void xstormy16_cgen_print_operand
-  PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
-           void const *, bfd_vma, int));
+  (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
 
 /* Main entry point for printing operands.
    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@@ -79,16 +78,15 @@ void xstormy16_cgen_print_operand
    the handlers.  */
 
 void
-xstormy16_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     PTR xinfo;
-     CGEN_FIELDS *fields;
-     void const *attrs ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     int length;
+xstormy16_cgen_print_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   void * xinfo,
+			   CGEN_FIELDS *fields,
+			   void const *attrs ATTRIBUTE_UNUSED,
+			   bfd_vma pc,
+			   int length)
 {
- disassemble_info *info = (disassemble_info *) xinfo;
+  disassemble_info *info = (disassemble_info *) xinfo;
 
   switch (opindex)
     {
@@ -180,8 +178,7 @@ cgen_print_fn * const xstormy16_cgen_print_handlers[] =
 
 
 void
-xstormy16_cgen_init_dis (cd)
-     CGEN_CPU_DESC cd;
+xstormy16_cgen_init_dis (CGEN_CPU_DESC cd)
 {
   xstormy16_cgen_init_opcode_table (cd);
   xstormy16_cgen_init_ibld_table (cd);
@@ -233,7 +230,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 
   /* Print the operand as directed by the attributes.  */
   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
-    ; /* nothing to do */
+    ; /* Nothing to do.  */
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
     (*info->print_address_func) (value, info);
   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@@ -315,6 +312,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
+
   if (status != 0)
     {
       (*info->memory_error_func) (status, pc, info);
@@ -419,13 +417,13 @@ print_insn (CGEN_CPU_DESC cd,
 	    length = CGEN_EXTRACT_FN (cd, insn)
 	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 
-	  /* length < 0 -> error */
+	  /* Length < 0 -> error.  */
 	  if (length < 0)
 	    return length;
 	  if (length > 0)
 	    {
 	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
-	      /* length is in bits, result is in bytes */
+	      /* Length is in bits, result is in bytes.  */
 	      return length / 8;
 	    }
 	}
@@ -475,7 +473,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
    Print one instruction from PC on INFO->STREAM.
    Return the size of the instruction (in bytes).  */
 
-typedef struct cpu_desc_list {
+typedef struct cpu_desc_list
+{
   struct cpu_desc_list *next;
   int isa;
   int mach;
@@ -560,7 +559,7 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info)
       if (!cd)
 	abort ();
 
-      /* save this away for future reference */
+      /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
       cl->isa = isa;
diff --git a/opcodes/xstormy16-ibld.c b/opcodes/xstormy16-ibld.c
index 16b9f9d..57ef85c 100644
--- a/opcodes/xstormy16-ibld.c
+++ b/opcodes/xstormy16-ibld.c
@@ -1,25 +1,26 @@
 /* Instruction building/extraction support for xstormy16. -*- C -*-
 
-THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
-- the resultant file is machine generated, cgen-ibld.in isn't
+   THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+   - the resultant file is machine generated, cgen-ibld.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
 
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
    Keep that in mind.  */
@@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #include "opintl.h"
 #include "safe-ctype.h"
 
-#undef min
+#undef  min
 #define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
+#undef  max
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 /* Used by the ifield rtx function.  */
@@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
   if (length == 0)
     return NULL;
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
 
 #if CGEN_INT_INSN_P
 /* Cover function to store an insn value into an integral insn.  Must go here
- because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
+   because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
       int shift = insn_length - length;
       /* Written this way to avoid undefined behaviour.  */
       CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
       *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
     }
 }
@@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
 {
   unsigned long x;
   int shift;
-#if 0
-  int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
-#endif
+
   x = cgen_get_insn_value (cd, bufp, word_length);
 
   if (CGEN_INSN_LSB0_P)
@@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
       return 1;
     }
 
-#if 0
-  if (CGEN_INT_INSN_P
-      && word_offset != 0)
-    abort ();
-#endif
-
   if (word_length > 32)
     abort ();
 
@@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
   return CGEN_INSN_BITSIZE (insn);
 }
 
-/* machine generated code added here */
+/* Machine generated code added here.  */
 
 const char * xstormy16_cgen_insert_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 
 /* Main entry point for operand insertion.
 
@@ -559,12 +547,11 @@ const char * xstormy16_cgen_insert_operand
    resolved during parsing.  */
 
 const char *
-xstormy16_cgen_insert_operand (cd, opindex, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+xstormy16_cgen_insert_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     CGEN_INSN_BYTES_PTR buffer,
+			     bfd_vma pc ATTRIBUTE_UNUSED)
 {
   const char * errmsg = NULL;
   unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@@ -686,8 +673,7 @@ xstormy16_cgen_insert_operand (cd, opindex, fields, buffer, pc)
 }
 
 int xstormy16_cgen_extract_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-           CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 
 /* Main entry point for operand extraction.
    The result is <= 0 for error, >0 for success.
@@ -705,13 +691,12 @@ int xstormy16_cgen_extract_operand
    the handlers.  */
 
 int
-xstormy16_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     int opindex;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS * fields;
-     bfd_vma pc;
+xstormy16_cgen_extract_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_EXTRACT_INFO *ex_info,
+			     CGEN_INSN_INT insn_value,
+			     CGEN_FIELDS * fields,
+			     bfd_vma pc)
 {
   /* Assume success (for those operands that are nops).  */
   int length = 1;
@@ -843,10 +828,8 @@ cgen_extract_fn * const xstormy16_cgen_extract_handlers[] =
   extract_insn_normal,
 };
 
-int xstormy16_cgen_get_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
-bfd_vma xstormy16_cgen_get_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+int xstormy16_cgen_get_int_operand     (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+bfd_vma xstormy16_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
 
 /* Getting values from cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they return.
@@ -854,10 +837,9 @@ bfd_vma xstormy16_cgen_get_vma_operand
    not appropriate.  */
 
 int
-xstormy16_cgen_get_int_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+xstormy16_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   int value;
 
@@ -947,10 +929,9 @@ xstormy16_cgen_get_int_operand (cd, opindex, fields)
 }
 
 bfd_vma
-xstormy16_cgen_get_vma_operand (cd, opindex, fields)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     const CGEN_FIELDS * fields;
+xstormy16_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
 {
   bfd_vma value;
 
@@ -1039,10 +1020,8 @@ xstormy16_cgen_get_vma_operand (cd, opindex, fields)
   return value;
 }
 
-void xstormy16_cgen_set_int_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
-void xstormy16_cgen_set_vma_operand
-  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+void xstormy16_cgen_set_int_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
+void xstormy16_cgen_set_vma_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
 
 /* Stuffing values in cgen_fields is handled by a collection of functions.
    They are distinguished by the type of the VALUE argument they accept.
@@ -1050,11 +1029,10 @@ void xstormy16_cgen_set_vma_operand
    not appropriate.  */
 
 void
-xstormy16_cgen_set_int_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     int value;
+xstormy16_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     int value)
 {
   switch (opindex)
     {
@@ -1140,11 +1118,10 @@ xstormy16_cgen_set_int_operand (cd, opindex, fields, value)
 }
 
 void
-xstormy16_cgen_set_vma_operand (cd, opindex, fields, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     int opindex;
-     CGEN_FIELDS * fields;
-     bfd_vma value;
+xstormy16_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     bfd_vma value)
 {
   switch (opindex)
     {
@@ -1232,8 +1209,7 @@ xstormy16_cgen_set_vma_operand (cd, opindex, fields, value)
 /* Function to call before using the instruction builder tables.  */
 
 void
-xstormy16_cgen_init_ibld_table (cd)
-     CGEN_CPU_DESC cd;
+xstormy16_cgen_init_ibld_table (CGEN_CPU_DESC cd)
 {
   cd->insert_handlers = & xstormy16_cgen_insert_handlers[0];
   cd->extract_handlers = & xstormy16_cgen_extract_handlers[0];
diff --git a/opcodes/xstormy16-opc.c b/opcodes/xstormy16-opc.c
index 19ed0ce..8237472 100644
--- a/opcodes/xstormy16-opc.c
+++ b/opcodes/xstormy16-opc.c
@@ -33,10 +33,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* The hash functions are recorded here to help keep assembler code out of
    the disassembler and vice versa.  */
 
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static int asm_hash_insn_p        (const CGEN_INSN *);
+static unsigned int asm_hash_insn (const char *);
+static int dis_hash_insn_p        (const CGEN_INSN *);
+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
 
 /* Instruction formats.  */
 
@@ -1144,14 +1144,10 @@ dis_hash_insn (buf, value)
   return CGEN_DIS_HASH (buf, value);
 }
 
-static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
-
 /* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
 
 static void
-set_fields_bitsize (fields, size)
-     CGEN_FIELDS *fields;
-     int size;
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
 {
   CGEN_FIELDS_BITSIZE (fields) = size;
 }
@@ -1160,15 +1156,15 @@ set_fields_bitsize (fields, size)
    This plugs the opcode entries and macro instructions into the cpu table.  */
 
 void
-xstormy16_cgen_init_opcode_table (cd)
-     CGEN_CPU_DESC cd;
+xstormy16_cgen_init_opcode_table (CGEN_CPU_DESC cd)
 {
   int i;
   int num_macros = (sizeof (xstormy16_cgen_macro_insn_table) /
 		    sizeof (xstormy16_cgen_macro_insn_table[0]));
   const CGEN_IBASE *ib = & xstormy16_cgen_macro_insn_table[0];
   const CGEN_OPCODE *oc = & xstormy16_cgen_macro_insn_opcode_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
+  CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
+
   memset (insns, 0, num_macros * sizeof (CGEN_INSN));
   for (i = 0; i < num_macros; ++i)
     {
diff --git a/opcodes/z8kgen.c b/opcodes/z8kgen.c
index 5adbfec..9970100 100644
--- a/opcodes/z8kgen.c
+++ b/opcodes/z8kgen.c
@@ -1,4 +1,4 @@
-/* Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
+/* Copyright 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
 
    This file is part of GNU Binutils.
 
@@ -904,7 +904,7 @@ static void
 internal (void)
 {
   int c = count ();
-  struct op *new = (struct op *) xmalloc (sizeof (struct op) * c);
+  struct op *new = xmalloc (sizeof (struct op) * c);
   struct op *p = opt;
   memcpy (new, p, c * sizeof (struct op));
 
@@ -960,12 +960,12 @@ gas (void)
   struct op *p = opt;
   int idx = -1;
   char *oldname = "";
-  struct op *new = (struct op *) xmalloc (sizeof (struct op) * c);
+  struct op *new = xmalloc (sizeof (struct op) * c);
 
   memcpy (new, p, c * sizeof (struct op));
 
   /* Sort all names in table alphabetically.  */
-  qsort (new, c, sizeof (struct op), (int (*)(const void *, const void *))func);
+  qsort (new, c, sizeof (struct op), (int (*)(const void *, const void *)) func);
 
   printf ("/* DO NOT EDIT!  -*- buffer-read-only: t -*-\n");
   printf ("   This file is automatically generated by z8kgen.  */\n\n");
@@ -1251,7 +1251,7 @@ gas (void)
   printf ("#endif\n");
   printf ("  const char *name;\n");
   printf ("  unsigned char opcode;\n");
-  printf ("  void (*func) PARAMS ((void));\n");
+  printf ("  void (*func) (void);\n");
   printf ("  unsigned int arg_info[4];\n");
   printf ("  unsigned int byte_info[%d];\n", BYTE_INFO_LEN);
   printf ("  int noperands;\n");