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| author | Gianluca Guida <gianluca@rivosinc.com> | 2023-05-31 17:28:56 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-18 14:35:50 +0800 |
| commit | 88729e96162f0293177d2324fc8dc6cd78aac793 (patch) | |
| tree | 9bb7bbe7394dbc46add1801b711f30d2a7680c7d /opcodes/riscv-opc.c | |
| parent | 0915235d341841ac7f13bd3136991c19b4a6746b (diff) | |
| download | binutils-88729e96162f0293177d2324fc8dc6cd78aac793.zip binutils-88729e96162f0293177d2324fc8dc6cd78aac793.tar.gz binutils-88729e96162f0293177d2324fc8dc6cd78aac793.tar.bz2 | |
RISC-V: Support Zacas extension.
https://github.com/riscvarchive/riscv-zacas/releases/tag/v1.0
The Zacas extension introduce compare-and-swap instructions to operate
on 32-bit, 64-bit and 128-bit (RV64 only) data values.
It introduces three new instructions:
- amocas.w (32-bit CAS)
- amocas.d (64-bit CAS)
- amocas.q (128-bit CAS, RV64 only)
Like other AMOs in the A extension, Zacas instructions have '.aq',
'.rl' and '.aqrl' variations.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): 'A' implied by 'Zacas'.
(riscv_supported_std_z_ext): Add 'Zacas' extension.
(riscv_multi_subset_supports, riscv_multi_subset_supports_ext):
Handle INSN_CLASS_ZACAS case.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Updated.
* testsuite/gas/riscv/zacas-32.d: New test (RV32).
* testsuite/gas/riscv/zacas-fail-32.d: Likewise.
* testsuite/gas/riscv/zacas-64.d: New test (RV64).
* testsuite/gas/riscv/zacas-fail-64.d: Likewise.
* testsuite/gas/riscv/zacas.s: New test source.
* testsuite/gas/riscv/zacas-fail.s: Likewise.
* testsuite/gas/riscv/zacas-fail-32.l: New file.
* testsuite/gas/riscv/zacas-fail-64.l: Likewise.
include/ChangeLog:
* include/opcode/riscv.h (INSN_CLASS_ZACAS): New definition.
* include/opcode/riscv-opc.h (MATCH_AMOCAS_W, MASK_AMOCAS_W)
(MATCH_AMOCAS_D, MASK_AMOCAS_D, MATCH_AMOCAS_Q, MASK_AMOCAS_Q):
Likewise.
(amocas_w, amocas_d, amocas_q): Declare instructions.
opcodes/ChangeLog:
* riscv-opc.c (match_rs2_rd_even): New function.
(amocas_w, amocas_d, amocas_q, amocas_w.aq)
(amocas_d.aq, amocas_q.aq, amocas_w.rl, amocas_d.rl, amocas_q.rl)
(amocas_w.aqrl, amocas_d.aqrl, amocas_q.aqrl): Add instructions.
Diffstat (limited to 'opcodes/riscv-opc.c')
| -rw-r--r-- | opcodes/riscv-opc.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index ff08bd5..e101c3d 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -198,6 +198,14 @@ match_rs1_eq_rs2 (const struct riscv_opcode *op, insn_t insn) } static int +match_rs2_rd_even (const struct riscv_opcode *op, insn_t insn) +{ + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rd = (insn & MASK_RD) >> OP_SH_RD; + return ((rs2 & 1) == 0) && ((rd & 1) == 0) && match_opcode (op, insn); +} + +static int match_rd_nonzero (const struct riscv_opcode *op, insn_t insn) { return (op->pinfo == INSN_MACRO || match_opcode (op, insn)) @@ -748,6 +756,24 @@ const struct riscv_opcode riscv_opcodes[] = {"amomin.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_AQRL, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, {"amominu.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_AQRL, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +/* Zacas instruction subset. */ +{"amocas.w", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"amocas.d", 32, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D, MASK_AMOCAS_D|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_8_BYTE }, +{"amocas.d", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"amocas.q", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q, MASK_AMOCAS_Q|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_16_BYTE }, +{"amocas.w.aq", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W|MASK_AQ, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"amocas.d.aq", 32, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQ, MASK_AMOCAS_D|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_8_BYTE }, +{"amocas.d.aq", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQ, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"amocas.q.aq", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q|MASK_AQ, MASK_AMOCAS_Q|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_16_BYTE }, +{"amocas.w.rl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W|MASK_RL, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"amocas.d.rl", 32, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_RL, MASK_AMOCAS_D|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_8_BYTE }, +{"amocas.d.rl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_RL, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"amocas.q.rl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q|MASK_RL, MASK_AMOCAS_Q|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_16_BYTE }, +{"amocas.w.aqrl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W|MASK_AQRL, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"amocas.d.aqrl", 32, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQRL, MASK_AMOCAS_D|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_8_BYTE }, +{"amocas.d.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQRL, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"amocas.q.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q|MASK_AQRL, MASK_AMOCAS_Q|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_16_BYTE }, + /* Multiply/Divide instruction subset. */ {"mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Cw,Ct", MATCH_C_MUL, MASK_C_MUL, match_opcode, INSN_ALIAS }, {"mul", 0, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, |