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author | Maciej W. Rozycki <macro@redhat.com> | 2024-07-19 19:01:53 +0100 |
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committer | Maciej W. Rozycki <macro@redhat.com> | 2024-07-19 19:01:53 +0100 |
commit | 0ffc7246996b40cd189694fca7b297913a9ea000 (patch) | |
tree | 6ef19af2423e4f3d8962bc25263592ec5e10b891 /opcodes/mips-opc.c | |
parent | d8b73b41a207a5e4263848c323d81e1d3882ac7d (diff) | |
download | binutils-0ffc7246996b40cd189694fca7b297913a9ea000.zip binutils-0ffc7246996b40cd189694fca7b297913a9ea000.tar.gz binutils-0ffc7246996b40cd189694fca7b297913a9ea000.tar.bz2 |
MIPS/opcodes: Mark MT thread context move assembly idioms as aliases
A number of instructions in the regular MIPS opcode table are assembly
idioms for the MT thread context move MFTR and MTTR instructions, so
mark them as aliases accordingly. Add suitable test cases, which also
cover the PAUSE assembly idiom.
Diffstat (limited to 'opcodes/mips-opc.c')
-rw-r--r-- | opcodes/mips-opc.c | 76 |
1 files changed, 38 insertions, 38 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index ebc6f58..7b1aa5f 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -986,9 +986,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {"cfc1", "t,S", 0x44400000, 0xffe007ff, WR_1|RD_C1|LC, 0, I1, 0, 0 }, /* cfc2 is at the bottom of the table. */ /* cfc3 is at the bottom of the table. */ -{"cftc1", "d,y", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, 0, 0, MT32, 0 }, -{"cftc1", "d,T", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, 0, 0, MT32, 0 }, -{"cftc2", "d,y", 0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LC, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, +{"cftc1", "d,y", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 }, +{"cftc1", "d,T", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 }, +{"cftc2", "d,y", 0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LC, AL, 0, MT32, IOCT|IOCTP|IOCT2 }, {"cins32", "t,r,+p,+s", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, {"cins", "t,r,+P,+S", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* cins32 */ {"cins", "t,r,+p,+S", 0x70000032, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, @@ -1003,9 +1003,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, /* ctc2 is at the bottom of the table. */ /* ctc3 is at the bottom of the table. */ -{"cttc1", "t,g", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, 0 }, -{"cttc1", "t,S", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, 0 }, -{"cttc2", "t,g", 0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, +{"cttc1", "t,g", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, 0 }, +{"cttc1", "t,S", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, 0 }, +{"cttc2", "t,g", 0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, IOCT|IOCTP|IOCT2 }, {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, @@ -1432,22 +1432,22 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, WR_1|RD_C0|LC, 0, M1|N5|EE, 0, 0 }, /* mfps is above mfc0. */ {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 }, -{"mftacx", "d", 0x41020021, 0xffff07ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, -{"mftacx", "d,*", 0x41020021, 0xfff307ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, -{"mftc0", "d,E", 0x41000000, 0xffe007ff, WR_1|RD_C0|TRAP|LC, 0, 0, MT32, 0 }, -{"mftc0", "d,E,H", 0x41000000, 0xffe007f8, WR_1|RD_C0|TRAP|LC, 0, 0, MT32, 0 }, -{"mftc1", "d,T", 0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_S, 0, 0, MT32, 0 }, -{"mftc1", "d,E", 0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_S, 0, 0, MT32, 0 }, -{"mftc2", "d,E", 0x41000024, 0xffe007ff, WR_1|RD_C2|TRAP|LC, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, -{"mftdsp", "d", 0x41100021, 0xffff07ff, WR_1|TRAP, 0, 0, MT32, 0 }, -{"mftgpr", "d,t", 0x41000020, 0xffe007ff, WR_1|RD_2|TRAP, 0, 0, MT32, 0 }, -{"mfthc1", "d,T", 0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_D, 0, 0, MT32, 0 }, -{"mfthc1", "d,E", 0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_D, 0, 0, MT32, 0 }, -{"mfthc2", "d,E", 0x41000034, 0xffe007ff, WR_1|RD_C2|TRAP|LC, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, -{"mfthi", "d", 0x41010021, 0xffff07ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, -{"mfthi", "d,*", 0x41010021, 0xfff307ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, -{"mftlo", "d", 0x41000021, 0xffff07ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, -{"mftlo", "d,*", 0x41000021, 0xfff307ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, +{"mftacx", "d", 0x41020021, 0xffff07ff, WR_1|RD_a|TRAP, AL, 0, MT32, 0 }, +{"mftacx", "d,*", 0x41020021, 0xfff307ff, WR_1|RD_a|TRAP, AL, 0, MT32, 0 }, +{"mftc0", "d,E", 0x41000000, 0xffe007ff, WR_1|RD_C0|TRAP|LC, AL, 0, MT32, 0 }, +{"mftc0", "d,E,H", 0x41000000, 0xffe007f8, WR_1|RD_C0|TRAP|LC, AL, 0, MT32, 0 }, +{"mftc1", "d,T", 0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_S, AL, 0, MT32, 0 }, +{"mftc1", "d,E", 0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_S, AL, 0, MT32, 0 }, +{"mftc2", "d,E", 0x41000024, 0xffe007ff, WR_1|RD_C2|TRAP|LC, AL, 0, MT32, IOCT|IOCTP|IOCT2 }, +{"mftdsp", "d", 0x41100021, 0xffff07ff, WR_1|TRAP, AL, 0, MT32, 0 }, +{"mftgpr", "d,t", 0x41000020, 0xffe007ff, WR_1|RD_2|TRAP, AL, 0, MT32, 0 }, +{"mfthc1", "d,T", 0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_D, AL, 0, MT32, 0 }, +{"mfthc1", "d,E", 0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_D, AL, 0, MT32, 0 }, +{"mfthc2", "d,E", 0x41000034, 0xffe007ff, WR_1|RD_C2|TRAP|LC, AL, 0, MT32, IOCT|IOCTP|IOCT2 }, +{"mfthi", "d", 0x41010021, 0xffff07ff, WR_1|RD_a|TRAP, AL, 0, MT32, 0 }, +{"mfthi", "d,*", 0x41010021, 0xfff307ff, WR_1|RD_a|TRAP, AL, 0, MT32, 0 }, +{"mftlo", "d", 0x41000021, 0xffff07ff, WR_1|RD_a|TRAP, AL, 0, MT32, 0 }, +{"mftlo", "d,*", 0x41000021, 0xfff307ff, WR_1|RD_a|TRAP, AL, 0, MT32, 0 }, {"mftr", "d,E,!,H,$", 0x41000000, 0xffe007c8, WR_1|TRAP, 0, 0, MT32, 0 }, {"min", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, ALX, 0, 0 }, {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, @@ -1566,22 +1566,22 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mtsa", "s", 0x00000029, 0xfc1fffff, RD_1, 0, EE, 0, 0 }, {"mtsab", "s,j", 0x04180000, 0xfc1f0000, RD_1, 0, EE, 0, 0 }, {"mtsah", "s,j", 0x04190000, 0xfc1f0000, RD_1, 0, EE, 0, 0 }, -{"mttacx", "t", 0x41801021, 0xffe0ffff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, -{"mttacx", "t,&", 0x41801021, 0xffe09fff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, -{"mttc0", "t,G", 0x41800000, 0xffe007ff, RD_1|WR_C0|WR_CC|TRAP|CM, 0, 0, MT32, 0 }, -{"mttc0", "t,G,H", 0x41800000, 0xffe007f8, RD_1|WR_C0|WR_CC|TRAP|CM, 0, 0, MT32, 0 }, -{"mttc1", "t,S", 0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0, 0, MT32, 0 }, -{"mttc1", "t,G", 0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0, 0, MT32, 0 }, -{"mttc2", "t,G", 0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, -{"mttdsp", "t", 0x41808021, 0xffe0ffff, RD_1|TRAP, 0, 0, MT32, 0 }, -{"mttgpr", "t,d", 0x41800020, 0xffe007ff, RD_1|WR_2|TRAP, 0, 0, MT32, 0 }, -{"mtthc1", "t,S", 0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, 0, 0, MT32, 0 }, -{"mtthc1", "t,G", 0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, 0, 0, MT32, 0 }, -{"mtthc2", "t,G", 0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, -{"mtthi", "t", 0x41800821, 0xffe0ffff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, -{"mtthi", "t,&", 0x41800821, 0xffe09fff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, -{"mttlo", "t", 0x41800021, 0xffe0ffff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, -{"mttlo", "t,&", 0x41800021, 0xffe09fff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, +{"mttacx", "t", 0x41801021, 0xffe0ffff, RD_1|WR_a|TRAP, AL, 0, MT32, 0 }, +{"mttacx", "t,&", 0x41801021, 0xffe09fff, RD_1|WR_a|TRAP, AL, 0, MT32, 0 }, +{"mttc0", "t,G", 0x41800000, 0xffe007ff, RD_1|WR_C0|WR_CC|TRAP|CM, AL, 0, MT32, 0 }, +{"mttc0", "t,G,H", 0x41800000, 0xffe007f8, RD_1|WR_C0|WR_CC|TRAP|CM, AL, 0, MT32, 0 }, +{"mttc1", "t,S", 0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, AL, 0, MT32, 0 }, +{"mttc1", "t,G", 0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, AL, 0, MT32, 0 }, +{"mttc2", "t,G", 0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, AL, 0, MT32, IOCT|IOCTP|IOCT2 }, +{"mttdsp", "t", 0x41808021, 0xffe0ffff, RD_1|TRAP, AL, 0, MT32, 0 }, +{"mttgpr", "t,d", 0x41800020, 0xffe007ff, RD_1|WR_2|TRAP, AL, 0, MT32, 0 }, +{"mtthc1", "t,S", 0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, AL, 0, MT32, 0 }, +{"mtthc1", "t,G", 0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, AL, 0, MT32, 0 }, +{"mtthc2", "t,G", 0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, AL, 0, MT32, IOCT|IOCTP|IOCT2 }, +{"mtthi", "t", 0x41800821, 0xffe0ffff, RD_1|WR_a|TRAP, AL, 0, MT32, 0 }, +{"mtthi", "t,&", 0x41800821, 0xffe09fff, RD_1|WR_a|TRAP, AL, 0, MT32, 0 }, +{"mttlo", "t", 0x41800021, 0xffe0ffff, RD_1|WR_a|TRAP, AL, 0, MT32, 0 }, +{"mttlo", "t,&", 0x41800021, 0xffe09fff, RD_1|WR_a|TRAP, AL, 0, MT32, 0 }, {"mttr", "t,G,!,H,$", 0x41800000, 0xffe007c8, RD_1|TRAP, 0, 0, MT32, 0 }, {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, |