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authorJim Wilson <wilson@tuliptree.org>2002-12-05 02:08:02 +0000
committerJim Wilson <wilson@tuliptree.org>2002-12-05 02:08:02 +0000
commitc10d9d8fc3e815f9cbbf3be2188ddb94e4635ac9 (patch)
tree060d0f181868d4dfeac327c4111706a2221bf3fa /opcodes/ia64-opc-x.c
parent27e829d0372c529518abf58c384aa80936677a95 (diff)
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Patch to update IA-64 port to SDM 2.1.
bfd/ChangeLog * cpu-ia64-opc.c: Add operand constant "ar.csd". gas/ChangeLog * config/tc-ia64.c (pseudo_func): Add "@pause" constant for "hint" instruction. (emit_one_bundle): Handle "hint" instruction. (operand_match): Match IA64_OPND_AR_CSD. gas/testsuite/ChangeLog * gas/ia64/opc-b.d: Update for instructions added by SDM2.1. * gas/ia64/opc-b.s: Ditto. * gas/ia64/opc-f.d: Ditto. * gas/ia64/opc-f.s: Ditto. * gas/ia64/opc-i.d: Ditto. * gas/ia64/opc-i.s: Ditto. * gas/ia64/opc-m.d: Ditto. * gas/ia64/opc-m.s: Ditto. * gas/ia64/opc-x.d: Ditto. * gas/ia64/opc-x.s: Ditto. include/opcode/ChangeLog * ia64.h: Fix copyright message. (IA64_OPND_AR_CSD): New operand kind. opcodes/ChangeLog * ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction. * ia64-opc-b.c: Add "hint.b" instruction. * ia64-opc-f.c: Add "hint.f" instruction. * ia64-opc-i.c: Add "hint.i" instruction. * ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and "cmp8xchg16" instructions. * ia64-opc-x.c: Add "hint.x" instruction. * ia64-opc.h (AR_CSD): New macro. * ia64-ic.tbl: Update according to SDM2.1. * ia64-raw.tbl: Ditto. * ia64-waw.tbl: Ditto. * ia64-gen.c (in_iclass): Handle "hint" like "nop". (lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD], AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR]. * ia64-asmtab.c: Regenerate.
Diffstat (limited to 'opcodes/ia64-opc-x.c')
-rw-r--r--opcodes/ia64-opc-x.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/ia64-opc-x.c b/opcodes/ia64-opc-x.c
index 9d9a6c1..e1d4345 100644
--- a/opcodes/ia64-opc-x.c
+++ b/opcodes/ia64-opc-x.c
@@ -34,6 +34,7 @@
#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33)
#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33)
#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
+#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26)
#define mBtype bBtype (-1)
#define mD bD (-1)
@@ -43,9 +44,12 @@
#define mWha bWha (-1)
#define mX3 bX3 (-1)
#define mX6 bX6 (-1)
+#define mY bY (-1)
#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \
(mOp | mX3 | mX6)
+#define OpX3X6Y(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bY(d)), \
+ (mOp | mX3 | mX6 | mY)
#define OpVc(a,b) (bOp (a) | bVc (b)), (mOp | mVc)
#define OpPaWhaD(a,b,c,d) \
(bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD)
@@ -58,8 +62,9 @@
struct ia64_opcode ia64_opcodes_x[] =
{
- {"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}, 0, 0, NULL},
- {"nop.x", X0, OpX3X6 (0, 0, 0x01), {IMMU62}, 0, 0, NULL},
+ {"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}, 0, 0, NULL},
+ {"nop.x", X0, OpX3X6Y (0, 0, 0x01, 0), {IMMU62}, 0, 0, NULL},
+ {"hint.x", X0, OpX3X6Y (0, 0, 0x01, 1), {IMMU62}, 0, 0, NULL},
{"movl", X, OpVc (6, 0), {R1, IMMU64}, 0, 0, NULL},
#define BRL(a,b) \
X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, PSEUDO, 0, NULL