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| author | Haochen Jiang <haochen.jiang@intel.com> | 2023-12-19 16:35:00 +0800 |
|---|---|---|
| committer | Haochen Jiang <haochen.jiang@intel.com> | 2023-12-19 16:35:24 +0800 |
| commit | fa88a361f99ecfddce4cc7228932ccc35879a6e8 (patch) | |
| tree | 37239d85026e8de195943163c45e3028b7cba86b /opcodes/i386-opc.h | |
| parent | 15aacf324fb871871e2162ea8769a9f82c043909 (diff) | |
| download | binutils-fa88a361f99ecfddce4cc7228932ccc35879a6e8.zip binutils-fa88a361f99ecfddce4cc7228932ccc35879a6e8.tar.gz binutils-fa88a361f99ecfddce4cc7228932ccc35879a6e8.tar.bz2 | |
x86: Remove the restriction for size of the mask register in AVX10
Since AVX10.1/256 will also allow 64 bit mask register, we will
remove the restriction for size of the mask register in AVX10.
gas/ChangeLog:
* config/tc-i386.c (VSZ128, VSZ256, VSZ512): New.
(VEX_check_encoding): Remove opcode_modifier check for vsz.
* testsuite/gas/i386/avx10-vsz.l: Remove testcases for mask
registers since they are not needed.
* testsuite/gas/i386/avx10-vsz.s: Ditto.
opcodes/ChangeLog:
* i386-gen.c: Remove Vsz.
* i386-opc.h: Ditto.
* i386-opc.tbl: Remove kvsz.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index b76f9ec..03b02bd 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -716,16 +716,6 @@ enum #define DISP8_SHIFT_VL 7 Disp8MemShift, - /* insn has vector size restrictions, requiring a minimum of: - 0: 128 bits. - 1: 256 bits. - 2: 512 bits. - */ -#define VSZ128 0 /* Not to be used in templates. */ -#define VSZ256 1 -#define VSZ512 2 - Vsz, - /* Support encoding optimization. */ Optimize, @@ -786,7 +776,6 @@ typedef struct i386_opcode_modifier unsigned int staticrounding:1; unsigned int sae:1; unsigned int disp8memshift:3; - unsigned int vsz:3; unsigned int optimize:1; unsigned int dialect:2; unsigned int isa64:2; |