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| author | Cui, Lili <lili.cui@intel.com> | 2024-06-18 10:45:49 +0800 |
|---|---|---|
| committer | Cui, Lili <lili.cui@intel.com> | 2024-06-18 10:52:40 +0800 |
| commit | d8ba1c40371a664fe6fa3ed768dbf78289548359 (patch) | |
| tree | 8087faa358f411cbdb586ef6453c6ad90ef9b799 /opcodes/i386-opc.h | |
| parent | 8864c4afdf2ff75e7edda6075286e07b9714ce12 (diff) | |
| download | binutils-d8ba1c40371a664fe6fa3ed768dbf78289548359.zip binutils-d8ba1c40371a664fe6fa3ed768dbf78289548359.tar.gz binutils-d8ba1c40371a664fe6fa3ed768dbf78289548359.tar.bz2 | |
Support APX CCMP and CTEST
CCMP and CTEST are two new sets of instructions for conditional CMP
and TEST, SCC and OSZC flags are given as suffixes of CCMP or CTEST
in the instruction mnemonic, e.g.:
ccmp<cc> { dfv=sf , cf , of } %eax, %ecx
also add
{evex} cmp/test %eax, %ecx
as an alias for ccmpt.
For the encoder part, add function check_Scc_OszcOperation to parse
'{ dfv=of , sf, sf, cf}', store scc in the lower 4 bits of base_opcode,
and adjust base_opcode to its normal meaning in install_template.
For the decoder part, add 'SC' and 'DF' macros to add scc and oszc flags
suffixes.
gas/ChangeLog:
* config/tc-i386.c (OSZC_CF): New.
(OSZC_ZF): Ditto.
(OSZC_SF): Ditto.
(OSZC_OF): Ditto.
(set_oszc_flags): Set oszc flags and report error for using the same oszc flags twice.
(check_Scc_OszcOperations): Handle SCC OSZC flags.
(install_template): Add scc and oszc_flags.
(build_apx_evex_prefix): Encode SCC and oszc flags bits.
(parse_insn): Handle check_Scc_OszcOperations.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add ivalid test case.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Add test for ccmp and ctest.
* testsuite/gas/i386/x86-64-apx-ccmp-ctest-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.l: Ditto.
* testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.s: Ditto.
* testsuite/gas/i386/x86-64-apx-ccmp-ctest.d: Ditto.
* testsuite/gas/i386/x86-64-apx-ccmp-ctest.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex-reg.h: Add ccmp and ctest.
* i386-dis-evex.h: Ditto.
* i386-dis.c (struct instr_info): add scc.
(struct dis386): Add new micro 'NE','SC' and'DF'.
(get_valid_dis386): Get scc value and move MAP4 invalid check to print_insn.
(putop): Handle %NE, %SC and %DF.
* i386-opc.h (SCC): New.
* i386-opc.tbl: Add ccmp/ctest and evex format for cmp/test.
* i386-mnem.h: Regenerated.
* i386-tbl.h: Ditto.
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 38b8e64..7400428 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -581,6 +581,8 @@ enum #define IMPLICIT_STACK_OP 9 /* Instruction zeroes upper part of register. */ #define ZERO_UPPER 10 + /* Instruction support SCC. */ +#define SCC 11 OperandConstraint, /* instruction ignores operand size prefix and in Intel mode ignores mnemonic size suffix check. */ |