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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-11-20 20:40:10 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-09 10:16:41 +0000 |
| commit | 9af8f6711831f2851bf88c46a1f0f2a43fb49be8 (patch) | |
| tree | e43d08a9a5c8ab7dd7a04ade9d9219620d09a55c /opcodes/aarch64-dis.c | |
| parent | 33ccb0e0dbd9707b537e385dc06eaf0a5b389d8e (diff) | |
| download | binutils-9af8f6711831f2851bf88c46a1f0f2a43fb49be8.zip binutils-9af8f6711831f2851bf88c46a1f0f2a43fb49be8.tar.gz binutils-9af8f6711831f2851bf88c46a1f0f2a43fb49be8.tar.bz2 | |
aarch64: Add support for 128-bit system register mrrs and msrr insns
With the addition of 128-bit system registers to the Arm architecture
starting with Armv9.4-a, a mechanism for manipulating their contents
is introduced with the `msrr' and `mrrs' instruction pair.
These move values from one such 128-bit system register into a pair of
contiguous general-purpose registers and vice-versa, as for example:
msrr ttlb0_el1, x0, x1
mrrs x0, x1, ttlb0_el1
This patch adds the necessary support for these instructions, adding
checks for system-register width by defining a new operand type in the
form of `AARCH64_OPND_SYSREG128' and the `aarch64_sys_reg_128bit_p'
predicate, responsible for checking whether the requested system
register table entry is marked as implemented in the 128-bit mode via
the F_REG_128 flag.
Diffstat (limited to 'opcodes/aarch64-dis.c')
| -rw-r--r-- | opcodes/aarch64-dis.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 7eee365..7e088a9 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -302,6 +302,7 @@ aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_op aarch64_operand_error *errors ATTRIBUTE_UNUSED) { assert (info->idx == 1 + || info->idx == 2 || info->idx == 3 || info->idx == 5); |