RISC-V: Improve multiple relax passes problem.

According to the commit abd20cb637008da9d32018b4b03973e119388a0a, an
intersting thing is that - the more relax passes, the more chances of
relaxations are reduced [1].  Originally, we set the boolean `again`
to TRUE once the code is actually deleted, and then we run the relaxations
repeatedly if `again` is still TRUE.  But `again` only works for the
relax pass itself, and won't affect others.  That is - we can not use
`again` to re-run the relax pass when we already enter into the following
passes (can not run the relax passes backwards).  Besides, we must seperate
the PCREL relaxations into two relax passes for some reasons [2], it make
us lose some relax opportunities.

This patch try to fix the problem, and the basic idea was come from Jim
Wilson - we use a new boolean, restart_relax, to determine if we need to
run the whole relax passes again from 0 to 2.  Once we have deleted the
code between relax pass 0 to 2, the restart_relax will be set to TRUE,
we should run the whole relaxations again to give them more chances to
shorten the code.  We will only enter into the relax pass 3 when the
restart_relax is FALSE, since we can't relax anything else once we start
to handle the alignments.

I have passed the gcc/binutils regressions by riscv-gnu-toolchain, and
looks fine for now.

[1] https://sourceware.org/pipermail/binutils/2020-November/114223.html
[2] https://sourceware.org/pipermail/binutils/2020-November/114235.html

bfd/
    * elfnn-riscv.c (riscv_elf_link_hash_table): New boolean restart_relax,
    used to check if we need to run the whole relaxations from relax pass 0
    to 2 again.
    (riscv_elf_link_hash_table_create): Init restart_relax to FALSE.
    (_bfd_riscv_relax_align): Remove obsolete sec_flg0 set.
    (_bfd_riscv_relax_delete): Set again to TRUE if we do delete the code.
    (bfd_elfNN_riscv_restart_relax_sections): New function.  Called by
    after_allocation to check if we need to run the whole relaxations again.
    (_bfd_riscv_relax_section): We will only enter into the relax pass 3 when
    the restart_relax is FALSE; At last set restart_relax to TRUE if again is
    TRUE, too.
    * elfxx-riscv.h (bfd_elf32_riscv_restart_relax_sections): Declaration.
    (bfd_elf64_riscv_restart_relax_sections): Likewise.
ld/
    * emultempl/riscvelf.em (after_allocation): Run ldelf_map_segments many
    times if riscv_restart_relax_sections returns TRUE.
    * testsuite/ld-riscv-elf/restart-relax.d: New testcase.  Before applying
    this patch, the call won't be relaxed to jal; But now we have more chances
    to do relaxations.
    * testsuite/ld-riscv-elf/restart-relax.s: Likewise.
    * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.

5 files changed, 47 insertions, 1 deletions

diff --git a/ld/ChangeLog b/ld/ChangeLog
index ec78541..b5298b98 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,13 @@
+2021-03-11  Nelson Chu  <nelson.chu@sifive.com>
+
+	* emultempl/riscvelf.em (after_allocation): Run ldelf_map_segments
+	many times if riscv_restart_relax_sections returns TRUE.
+	* testsuite/ld-riscv-elf/restart-relax.d: New testcase.  Before
+	applying this patch, the call won't be relaxed to jal; But now we
+	have more chances to do relaxations.
+	* testsuite/ld-riscv-elf/restart-relax.s: Likewise.
+	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
+
 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 
 	* testsuite/ld-scripts/pr22267.t: Avoid symbol value with more
diff --git a/ld/emultempl/riscvelf.em b/ld/emultempl/riscvelf.em
index 735eae0..5fa7c77 100644
--- a/ld/emultempl/riscvelf.em
+++ b/ld/emultempl/riscvelf.em
@@ -62,7 +62,11 @@ gld${EMULATION_NAME}_after_allocation (void)
 	}
     }
 
-  ldelf_map_segments (need_layout);
+  do
+    {
+      ldelf_map_segments (need_layout);
+    }
+  while (bfd_elf${ELFSIZE}_riscv_restart_relax_sections (&link_info));
 }
 
 /* This is a convenient point to tell BFD about target specific flags.
diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index 7081af1..f3ff95c 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -86,6 +86,7 @@ if [istarget "riscv*-*-*"] {
     run_dump_test "disas-jalr"
     run_dump_test "pcrel-lo-addend"
     run_dump_test "pcrel-lo-addend-2"
+    run_dump_test "restart-relax"
     run_dump_test "attr-merge-arch-01"
     run_dump_test "attr-merge-arch-02"
     run_dump_test "attr-merge-arch-03"
diff --git a/ld/testsuite/ld-riscv-elf/restart-relax.d b/ld/testsuite/ld-riscv-elf/restart-relax.d
new file mode 100644
index 0000000..57b62eb
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/restart-relax.d
@@ -0,0 +1,14 @@
+#source: restart-relax.s
+#as:
+#ld:
+#objdump: -d
+
+#...
+Disassembly of section .text:
+
+0+[0-9a-f]+ <_start>:
+.*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+.*
+#...
+.*:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+ra,[0-9a-f]+ <_start>
+.*:[ 	]+[0-9a-f]+[ 	]+add[ 	]+a0,a1,a2
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/restart-relax.s b/ld/testsuite/ld-riscv-elf/restart-relax.s
new file mode 100644
index 0000000..efc881d
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/restart-relax.s
@@ -0,0 +1,17 @@
+	.text
+	.global _start
+_start:
+	lla	a0, data_g
+.rept 0x3fffe
+	nop
+.endr
+	call _start
+	.option rvc
+	.align 2
+	add	a0, a1, a2
+
+	.data
+	.global data_g
+	.dword 0x0
+data_g:
+	.word 0x1000