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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-02-10 09:27:28 +0000 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-02-10 11:01:51 +0000 |
| commit | 779b2502783107368c03421597b095c648f47a3a (patch) | |
| tree | 7d0d8087226280ef0af9c99f5ebc358527576014 /ld | |
| parent | 80aa6647b1678fe84b5af5595ad939b48febf6a0 (diff) | |
| download | binutils-779b2502783107368c03421597b095c648f47a3a.zip binutils-779b2502783107368c03421597b095c648f47a3a.tar.gz binutils-779b2502783107368c03421597b095c648f47a3a.tar.bz2 | |
RISC-V: Reduce effective linker relaxation passses
Commit 43025f01a0c9 ("RISC-V: Improve link time complexity.") reduced the
time complexity of the linker relaxation but some code portions did not
reflect this change.
This commit fixes a comment describing each relaxation pass and reduces
actual number of passes for the RISC-V linker relaxation from 3 to 2.
Though it does not change the functionality, it marginally improves the
performance while linking large programs (with many relocations).
bfd/ChangeLog:
* elfnn-riscv.c (_bfd_riscv_relax_section): Fix a comment to
reflect current roles of each relaxation pass.
ld/ChangeLog:
* emultempl/riscvelf.em: Reduce the number of linker relaxation
passes from 3 to 2.
Diffstat (limited to 'ld')
| -rw-r--r-- | ld/emultempl/riscvelf.em | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ld/emultempl/riscvelf.em b/ld/emultempl/riscvelf.em index b7435d6..b12d150 100644 --- a/ld/emultempl/riscvelf.em +++ b/ld/emultempl/riscvelf.em @@ -42,7 +42,7 @@ riscv_elf_before_allocation (void) ENABLE_RELAXATION; } - link_info.relax_pass = 3; + link_info.relax_pass = 2; } static void |