MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membership

Adjust opcode table entries for coprocessor instructions that have been
removed from certain ISA levels or CPU implementations as follows:

- remove CP0 memory access instructions from MIPS II up as the LWC0 and
  SWC0 opcodes have been reused for the LL and SC instructions
  respectively[1]; strictly speaking LWC0 and SWC0 have never really
  been defined in the first place[2], but let's keep them for now in
  case an odd implementation did,

- remove CP0 branch instructions from MIPS IV[3] and MIPS32[4] up, as
  they have been removed as from those ISAs,

- remove CP0 control register move instructions from MIPS32 up, as they
  have been removed as from that ISA[5],

- remove the RFE instruction from MIPS III[6] and MIPS32[7] up, as it
  has been removed as from those ISAs in favour to ERET,

- remove CP2 instructions from Vr5400 CPUs as their encodings have been
  reused for the multimedia instruction set extensions[8] and no CP2
  registers exist[9],

- remove CP3 memory access instructions from MIPS III up as coprocessor
  3 has been removed as from that ISA[10][11] and from MIPS32 up as the
  LWC3 opcode has been reused for the PREF instruction and consequently
  all the four memory access instructions removed from the ISA (though
  the COP3 opcode has been retained)[12].

Update the testsuite accordingly.

References:

[1]  Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
     Revision 3.2, September, 1995, Table A-38 "CPU Instruction Encoding
     - MIPS II Architecture", p. A-178

[2]  same, Section A.2.5.1 "Coprocessor Load and Store", p. A-12

[3]  "MIPS R10000 Microprocessor User's Manual", Version 2.0, MIPS
     Technologies, Inc., January 29, 1997, Section 14.25 "CP0
     Instructions", Subsection "Branch on Coprocessor 0", p. 285

[4]  "MIPS32 Architecture For Programmers, Volume II: The MIPS32
     Instruction Set", MIPS Technologies, Inc., Document Number:
     MD00086, Revision 1.00, June 9, 2003, Table A-9 "MIPS32 COP0
     Encoding of rs Field", p. 242

[5]  same

[6]  Joe Heinrich, "MIPS R4000 Microprocessor User's Manual", Second
     Edition, MIPS Technologies, Inc., April 1, 1994, Figure A-2 "R4000
     Opcode Bit Encoding", p. A-182

[8]  "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 1",
     NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000,
     Section 1.2.3 "CPU Instruction Set Overview", p. 9

[9]  "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 2",
     NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000,
     Section 19.2 "Multimedia Instruction Format", p. 681

[10] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
     Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 -
     COP3 and CP3 load/store", p. A-176

[11] same, Table A-39 "CPU Instruction Encoding - MIPS III
     Architecture", p. A-179

[12] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
     Instruction Set", MIPS Technologies, Inc., Document Number:
     MD00086, Revision 1.00, August 29, 2002, Table A-2 "MIPS32 Encoding
     of the Opcode Field", p. 241

	opcodes/
	* mips-opc.c (mips_builtin_opcodes): Update exclusion list for
	"ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
	"swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
	"bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
	"bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
	"mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
	"cop2", and "cop3" entries.

	gas/
	* testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3
	instruction removal.
	* testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.

0 files changed, 0 insertions, 0 deletions