diff options
| author | Sudakshina Das <sudi.das@arm.com> | 2018-11-12 13:09:55 +0000 |
|---|---|---|
| committer | Sudakshina Das <sudi.das@arm.com> | 2018-11-12 13:09:55 +0000 |
| commit | fb3265b371a141c4ffc97dcf8cc66e090c516dc8 (patch) | |
| tree | ffb3d94c4a2dec1ef9b6b0caecb4e60d863e2df0 /include | |
| parent | b731bc3b1bd122872a6aff68aafba1eda64a98d1 (diff) | |
| download | binutils-fb3265b371a141c4ffc97dcf8cc66e090c516dc8.zip binutils-fb3265b371a141c4ffc97dcf8cc66e090c516dc8.tar.gz binutils-fb3265b371a141c4ffc97dcf8cc66e090c516dc8.tar.bz2 | |
[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag setting instructions from
MTE which consists of the following instructions:
- STG [<Xn|SP>, #<simm>]
- STG [<Xn|SP>, #<simm>]!
- STG [<Xn|SP>], #<simm>
- STZG [<Xn|SP>, #<simm>]
- STZG [<Xn|SP>, #<simm>]!
- STZG [<Xn|SP>], #<simm>
- ST2G [<Xn|SP>, #<simm>]
- ST2G [<Xn|SP>, #<simm>]!
- ST2G [<Xn|SP>], #<simm>
- STZ2G [<Xn|SP>, #<simm>]
- STZ2G [<Xn|SP>, #<simm>]!
- STZ2G [<Xn|SP>], #<simm>
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
- STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>
where
<Xn|SP> : Is the 64-bit GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range -4096 to 4080, defaulting to 0.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
and AARCH64_OPND_ADDR_SIMM13.
(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
for AARCH64_OPND_QLF_imm_tag.
(operand_general_constraint_met_p): Add case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
(aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
for both offset and pre/post indexed versions.
(AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(fix_insn): Likewise.
(warn_unpredictable_ldst): Exempt STGP.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
stzg, stz2g and stgp.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 8 |
2 files changed, 14 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 2bdee25..491bbd4 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,11 @@ 2018-11-12 Sudakshina Das <sudi.das@arm.com> + * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11 + and AARCH64_OPND_ADDR_SIMM13. + (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag. + +2018-11-12 Sudakshina Das <sudi.das@arm.com> + * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index d6e639d..c4c573a 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -286,7 +286,11 @@ enum aarch64_opnd the mnemonic name for LDUR/STUR instructions wherever there is no ambiguity. */ AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */ + AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of + 16) immediate. */ AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ + AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of + 16) immediate. */ AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */ AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ @@ -467,6 +471,10 @@ enum aarch64_opnd_qualifier AARCH64_OPND_QLF_P_Z, AARCH64_OPND_QLF_P_M, + /* Used in scaled signed immediate that are scaled by a Tag granule + like in stg, st2g, etc. */ + AARCH64_OPND_QLF_imm_tag, + /* Constraint on value. */ AARCH64_OPND_QLF_CR, /* CRn, CRm. */ AARCH64_OPND_QLF_imm_0_7, |