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| author | Jerry Zhang Jian <jerry.zhangjian@sifive.com> | 2025-03-24 22:10:11 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2025-03-26 10:16:05 +0800 |
| commit | a7ecc1ba9715ac8f3a7772b9d7155f4c00ae2daf (patch) | |
| tree | c0fc70b70b5e76b154d0e6839f0f9460aa91c32f /include | |
| parent | e5db6129d8d51befe492434d3ebea065cab9adcb (diff) | |
| download | binutils-a7ecc1ba9715ac8f3a7772b9d7155f4c00ae2daf.zip binutils-a7ecc1ba9715ac8f3a7772b9d7155f4c00ae2daf.tar.gz binutils-a7ecc1ba9715ac8f3a7772b9d7155f4c00ae2daf.tar.bz2 | |
RISC-V: add Smrnmi 1.0 instruction support
Add instruction `mnret' support
Ref:
https://github.com/riscv/riscv-isa-manual/blob/bb8b9127f81965eeff2d150c211d1c89376591c4/src/rnmi.adoc
https://github.com/riscv/riscv-opcodes/blob/946eb673874b3a0f2474d1424dc28bc7ee53c306/extensions/rv_smrnmi
bfd/ChangeLog:
* elfxx-riscv.c: Add new Smrnmi instruction class handling
gas/ChangeLog:
* testsuite/gas/riscv/smrnmi.s: New test for mnret
* testsuite/gas/riscv/rmrnmi.d: Likewise
include/ChangeLog:
* opcode/ricsv-opc.h: Add MATCH_MNRET, MASK_MNRET
* opcode/riscv.h: Add new instruction class
opcodes/ChangeLog:
* riscv-opc.c: Add `mnret' instruction
Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 5 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 |
2 files changed, 6 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 1f56317..fea4948 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2311,6 +2311,9 @@ /* Smctr/Ssctr instruction. */ #define MATCH_SCTRCLR 0x10400073 #define MASK_SCTRCLR 0xffffffff +/* Smrnmi instruction. */ +#define MATCH_MNRET 0x70200073 +#define MASK_MNRET 0xffffffff /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -4808,6 +4811,8 @@ DECLARE_INSN(cm_jt, MATCH_CM_JT, MASK_CM_JT) DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT) /* Smctr/Ssctr instruction. */ DECLARE_INSN(sctrclr, MATCH_SCTRCLR, MASK_SCTRCLR) +/* Smrnmi instruction */ +DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 1f4bede..d76bcdb 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -526,6 +526,7 @@ enum riscv_insn_class INSN_CLASS_ZCMP, INSN_CLASS_ZCMT, INSN_CLASS_SMCTR_OR_SSCTR, + INSN_CLASS_SMRNMI, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, |