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| author | Kito Cheng <kito.cheng@sifive.com> | 2025-06-11 16:33:49 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2025-06-24 18:14:45 +0800 |
| commit | 9b4b518eceaa1f59acfb88013406b4203f6a3016 (patch) | |
| tree | b4164fe767affa3a4e07b121246d21499f3bc02f /include | |
| parent | 84eb7d284b3ae07ee894a1f21defc3c9669297b7 (diff) | |
| download | binutils-9b4b518eceaa1f59acfb88013406b4203f6a3016.zip binutils-9b4b518eceaa1f59acfb88013406b4203f6a3016.tar.gz binutils-9b4b518eceaa1f59acfb88013406b4203f6a3016.tar.bz2 | |
RISC-V: Support for unlabeled landing pad PLT generation
This patch adds support for generating unlabeled landing pad PLT entries
for the RISC-V architecture. Unlabeled landing pad will place a LPAD
instruction at the PLT entry and PLT header, also PLT header will have
few changes due to the offset is different from the original one.
Ref: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 7fca806..2b146af 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -421,6 +421,7 @@ static inline unsigned int riscv_insn_length (insn_t insn) /* ABI names for selected x-registers. */ +#define X_ZERO 0 #define X_RA 1 #define X_SP 2 #define X_GP 3 |